siliconcompiler 0.33.2__py3-none-any.whl → 0.34.1__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/__init__.py +2 -0
- siliconcompiler/_metadata.py +1 -1
- siliconcompiler/apps/_common.py +1 -1
- siliconcompiler/apps/sc.py +1 -1
- siliconcompiler/apps/sc_issue.py +6 -4
- siliconcompiler/apps/sc_remote.py +3 -20
- siliconcompiler/apps/sc_show.py +2 -2
- siliconcompiler/apps/utils/replay.py +4 -4
- siliconcompiler/checklist.py +202 -1
- siliconcompiler/core.py +62 -293
- siliconcompiler/data/templates/email/general.j2 +3 -3
- siliconcompiler/data/templates/email/summary.j2 +1 -1
- siliconcompiler/data/templates/issue/README.txt +1 -1
- siliconcompiler/data/templates/report/sc_report.j2 +7 -7
- siliconcompiler/dependencyschema.py +392 -0
- siliconcompiler/design.py +758 -0
- siliconcompiler/flowgraph.py +79 -13
- siliconcompiler/optimizer/vizier.py +2 -2
- siliconcompiler/package/__init__.py +383 -223
- siliconcompiler/package/git.py +75 -77
- siliconcompiler/package/github.py +70 -97
- siliconcompiler/package/https.py +77 -93
- siliconcompiler/packageschema.py +260 -0
- siliconcompiler/pdk.py +5 -5
- siliconcompiler/remote/client.py +33 -15
- siliconcompiler/remote/server.py +2 -2
- siliconcompiler/report/dashboard/cli/__init__.py +6 -6
- siliconcompiler/report/dashboard/cli/board.py +4 -4
- siliconcompiler/report/dashboard/web/components/__init__.py +5 -5
- siliconcompiler/report/dashboard/web/components/flowgraph.py +4 -4
- siliconcompiler/report/dashboard/web/components/graph.py +2 -2
- siliconcompiler/report/dashboard/web/state.py +1 -1
- siliconcompiler/report/dashboard/web/utils/__init__.py +5 -5
- siliconcompiler/report/html_report.py +1 -1
- siliconcompiler/report/report.py +4 -4
- siliconcompiler/report/summary_table.py +2 -2
- siliconcompiler/report/utils.py +5 -5
- siliconcompiler/scheduler/__init__.py +3 -1382
- siliconcompiler/scheduler/docker.py +263 -0
- siliconcompiler/scheduler/run_node.py +10 -21
- siliconcompiler/scheduler/scheduler.py +311 -0
- siliconcompiler/scheduler/schedulernode.py +944 -0
- siliconcompiler/scheduler/send_messages.py +3 -3
- siliconcompiler/scheduler/slurm.py +149 -163
- siliconcompiler/scheduler/taskscheduler.py +45 -57
- siliconcompiler/schema/__init__.py +3 -3
- siliconcompiler/schema/baseschema.py +234 -11
- siliconcompiler/schema/editableschema.py +4 -0
- siliconcompiler/schema/journal.py +210 -0
- siliconcompiler/schema/namedschema.py +55 -2
- siliconcompiler/schema/parameter.py +14 -1
- siliconcompiler/schema/parametervalue.py +1 -34
- siliconcompiler/schema/schema_cfg.py +210 -349
- siliconcompiler/tool.py +412 -148
- siliconcompiler/tools/__init__.py +2 -0
- siliconcompiler/tools/builtin/_common.py +5 -5
- siliconcompiler/tools/builtin/concatenate.py +7 -7
- siliconcompiler/tools/builtin/minimum.py +4 -4
- siliconcompiler/tools/builtin/mux.py +4 -4
- siliconcompiler/tools/builtin/nop.py +4 -4
- siliconcompiler/tools/builtin/verify.py +8 -9
- siliconcompiler/tools/execute/exec_input.py +1 -1
- siliconcompiler/tools/genfasm/genfasm.py +1 -6
- siliconcompiler/tools/openroad/_apr.py +5 -1
- siliconcompiler/tools/openroad/antenna_repair.py +1 -1
- siliconcompiler/tools/openroad/macro_placement.py +1 -1
- siliconcompiler/tools/openroad/power_grid.py +1 -1
- siliconcompiler/tools/openroad/scripts/common/procs.tcl +32 -25
- siliconcompiler/tools/opensta/timing.py +26 -3
- siliconcompiler/tools/slang/__init__.py +2 -2
- siliconcompiler/tools/surfer/__init__.py +0 -0
- siliconcompiler/tools/surfer/show.py +53 -0
- siliconcompiler/tools/surfer/surfer.py +30 -0
- siliconcompiler/tools/vpr/route.py +82 -0
- siliconcompiler/tools/vpr/vpr.py +23 -6
- siliconcompiler/tools/yosys/__init__.py +1 -1
- siliconcompiler/tools/yosys/scripts/procs.tcl +143 -0
- siliconcompiler/tools/yosys/{sc_synth_asic.tcl → scripts/sc_synth_asic.tcl} +4 -0
- siliconcompiler/tools/yosys/{sc_synth_fpga.tcl → scripts/sc_synth_fpga.tcl} +24 -77
- siliconcompiler/tools/yosys/syn_fpga.py +14 -0
- siliconcompiler/toolscripts/_tools.json +9 -13
- siliconcompiler/toolscripts/rhel9/install-vpr.sh +0 -2
- siliconcompiler/toolscripts/ubuntu22/install-surfer.sh +33 -0
- siliconcompiler/toolscripts/ubuntu24/install-surfer.sh +33 -0
- siliconcompiler/utils/__init__.py +4 -24
- siliconcompiler/utils/flowgraph.py +29 -28
- siliconcompiler/utils/issue.py +23 -29
- siliconcompiler/utils/logging.py +37 -7
- siliconcompiler/utils/showtools.py +6 -1
- {siliconcompiler-0.33.2.dist-info → siliconcompiler-0.34.1.dist-info}/METADATA +16 -25
- {siliconcompiler-0.33.2.dist-info → siliconcompiler-0.34.1.dist-info}/RECORD +98 -91
- siliconcompiler/scheduler/docker_runner.py +0 -254
- siliconcompiler/schema/journalingschema.py +0 -242
- siliconcompiler/tools/yosys/procs.tcl +0 -71
- siliconcompiler/toolscripts/rhel9/install-yosys-parmys.sh +0 -68
- siliconcompiler/toolscripts/ubuntu22/install-yosys-parmys.sh +0 -68
- siliconcompiler/toolscripts/ubuntu24/install-yosys-parmys.sh +0 -68
- /siliconcompiler/tools/yosys/{sc_lec.tcl → scripts/sc_lec.tcl} +0 -0
- /siliconcompiler/tools/yosys/{sc_screenshot.tcl → scripts/sc_screenshot.tcl} +0 -0
- /siliconcompiler/tools/yosys/{syn_strategies.tcl → scripts/syn_strategies.tcl} +0 -0
- {siliconcompiler-0.33.2.dist-info → siliconcompiler-0.34.1.dist-info}/WHEEL +0 -0
- {siliconcompiler-0.33.2.dist-info → siliconcompiler-0.34.1.dist-info}/entry_points.txt +0 -0
- {siliconcompiler-0.33.2.dist-info → siliconcompiler-0.34.1.dist-info}/licenses/LICENSE +0 -0
- {siliconcompiler-0.33.2.dist-info → siliconcompiler-0.34.1.dist-info}/top_level.txt +0 -0
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@@ -110,7 +110,9 @@ def schema_cfg(schema):
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cfg = schema_constraint(cfg)
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# Options
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cfg =
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cfg = schema_option_frontend(cfg)
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cfg = schema_option_runtime(cfg)
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cfg = schema_option_other(cfg)
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cfg = schema_arg(cfg)
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# Technology configuration
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@@ -212,7 +214,7 @@ def schema_fpga(cfg):
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###############################################################################
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def schema_pdk(cfg):
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from siliconcompiler.pdk import PDKSchema
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cfg.insert("pdk", "default", PDKSchema())
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cfg.insert("pdk", "default", PDKSchema(None))
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return cfg
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@@ -1016,7 +1018,7 @@ def schema_datasheet(cfg):
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###############################################################################
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def schema_flowgraph(cfg):
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from siliconcompiler.flowgraph import FlowgraphSchema
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cfg.insert("flowgraph", "default", FlowgraphSchema())
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cfg.insert("flowgraph", "default", FlowgraphSchema(None))
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return cfg
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@@ -1086,10 +1088,111 @@ def schema_record(cfg):
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###########################################################################
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# Run Options
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###########################################################################
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def
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def schema_option_other(cfg):
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''' Technology agnostic run time options
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'''
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# Compilation
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scparam(cfg, ['option', 'pdk'],
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sctype='str',
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scope=Scope.JOB,
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shorthelp="Option: PDK target",
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switch="-pdk <str>",
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example=["cli: -pdk freepdk45",
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"api: chip.set('option', 'pdk', 'freepdk45')"],
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schelp="""
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Target PDK used during compilation.""")
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scparam(cfg, ['option', 'stackup'],
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sctype='str',
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scope=Scope.JOB,
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shorthelp="Option: stackup target",
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switch="-stackup <str>",
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example=["cli: -stackup 2MA4MB2MC",
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"api: chip.set('option', 'stackup', '2MA4MB2MC')"],
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schelp="""
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Target stackup used during compilation. The stackup is required
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parameter for PDKs with multiple metal stackups.""")
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scparam(cfg, ['option', 'cfg'],
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sctype='[file]',
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scope=Scope.JOB,
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shorthelp="Option: configuration manifest",
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switch="-cfg <file>",
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example=["cli: -cfg mypdk.json",
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"api: chip.set('option', 'cfg', 'mypdk.json')"],
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schelp="""
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List of filepaths to JSON formatted schema configuration
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manifests. The files are read in automatically when using the
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'sc' command line application. In Python programs, JSON manifests
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can be merged into the current working manifest using the
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:meth:`Chip.read_manifest()` method.""")
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key = 'default'
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scparam(cfg, ['option', 'env', key],
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scope=Scope.JOB,
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shorthelp="Option: environment variables",
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switch="-env 'key <str>'",
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example=[
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"cli: -env 'PDK_HOME /disk/mypdk'",
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"api: chip.set('option', 'env', 'PDK_HOME', '/disk/mypdk')"],
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schelp="""
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Certain tools and reference flows require global environment
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variables to be set. These variables can be managed externally or
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specified through the env variable.""")
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scparam(cfg, ['option', 'var', key],
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sctype='[str]',
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scope=Scope.JOB,
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shorthelp="Option: custom variables",
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switch="-var 'key <str>'",
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example=[
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"cli: -var 'openroad_place_density 0.4'",
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"api: chip.set('option', 'var', 'openroad_place_density', '0.4')"],
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schelp="""
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List of key/value strings specified. Certain tools and
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reference flows require special parameters, this
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should only be used for specifying variables that are
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not directly supported by the SiliconCompiler schema.""")
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scparam(cfg, ['option', 'file', key],
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sctype='[file]',
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scope=Scope.JOB,
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copy=True,
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shorthelp="Option: custom files",
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switch="-file 'key <file>'",
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example=[
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"cli: -file 'openroad_tapcell ./tapcell.tcl'",
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"api: chip.set('option', 'file', 'openroad_tapcell', './tapcell.tcl')"],
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schelp="""
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List of named files specified. Certain tools and
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reference flows require special parameters, this
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parameter should only be used for specifying files that are
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not directly supported by the schema.""")
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scparam(cfg, ['option', 'dir', key],
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sctype='[dir]',
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copy=True,
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shorthelp="Option: custom directories",
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switch="-dir 'key <dir>'",
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example=[
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"api: chip.set('option', 'dir', 'openroad_files', './openroad_support/')"],
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List of named directories specified. Certain tools and
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reference flows require special parameters, this
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parameter should only be used for specifying directories that are
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not directly supported by the schema.""")
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return cfg
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def schema_option_runtime(cfg):
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''' Runtime run time options
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'''
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If the parameter is undefined, nice will not be used. For more information see
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`Unix 'nice' <https://en.wikipedia.org/wiki/Nice_(Unix)>`_.""")
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# Compilation
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scparam(cfg, ['option', 'pdk'],
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switch="-pdk <str>",
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example=["cli: -pdk freepdk45",
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"api: chip.set('option', 'pdk', 'freepdk45')"],
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schelp="""
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scparam(cfg, ['option', 'stackup'],
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switch="-stackup <str>",
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parameter for PDKs with multiple metal stackups.""")
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(O99) = Experimental highest possible effort, may be unstable
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manifests. The files are read in automatically when using the
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can be merged into the current working manifest using the
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:meth:`Chip.read_manifest()` method.""")
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variables to be set. These variables can be managed externally or
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switch="-var 'key <str>'",
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example=[
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not directly supported by the SiliconCompiler schema.""")
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switch="-file 'key <file>'",
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example=[
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reference flows require special parameters, this
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|
1266
|
-
parameter should only be used for specifying files that are
|
|
1267
|
-
not directly supported by the schema.""")
|
|
1268
|
-
|
|
1269
|
-
scparam(cfg, ['option', 'dir', key],
|
|
1270
|
-
sctype='[dir]',
|
|
1271
|
-
scope=Scope.JOB,
|
|
1272
|
-
copy=True,
|
|
1273
|
-
shorthelp="Option: custom directories",
|
|
1274
|
-
switch="-dir 'key <dir>'",
|
|
1275
|
-
example=[
|
|
1276
|
-
"cli: -dir 'openroad_tapcell ./tapcell.tcl'",
|
|
1277
|
-
"api: chip.set('option', 'dir', 'openroad_files', './openroad_support/')"],
|
|
1278
|
-
schelp="""
|
|
1279
|
-
List of named directories specified. Certain tools and
|
|
1280
|
-
reference flows require special parameters, this
|
|
1281
|
-
parameter should only be used for specifying directories that are
|
|
1282
|
-
not directly supported by the schema.""")
|
|
1283
|
-
|
|
1284
1293
|
scparam(cfg, ['option', 'loglevel'],
|
|
1285
1294
|
sctype='<info,warning,error,critical,debug,quiet>',
|
|
1286
1295
|
pernode=PerNode.OPTIONAL,
|
|
@@ -1374,18 +1383,6 @@ def schema_option(cfg):
|
|
|
1374
1383
|
EDA tool. If the step is a command line tool, then the flow
|
|
1375
1384
|
drops into a Python interpreter.""")
|
|
1376
1385
|
|
|
1377
|
-
scparam(cfg, ['option', 'library'],
|
|
1378
|
-
sctype='[str]',
|
|
1379
|
-
scope=Scope.JOB,
|
|
1380
|
-
pernode=PerNode.OPTIONAL,
|
|
1381
|
-
shorthelp="Option: library list",
|
|
1382
|
-
switch="-library <str>",
|
|
1383
|
-
example=["cli: -library lambdalib_asap7",
|
|
1384
|
-
"api: chip.set('option', 'library', 'lambdalib_asap7')"],
|
|
1385
|
-
schelp="""
|
|
1386
|
-
List of soft libraries to be linked in during import.""")
|
|
1387
|
-
|
|
1388
|
-
# Booleans
|
|
1389
1386
|
scparam(cfg, ['option', 'clean'],
|
|
1390
1387
|
sctype='bool',
|
|
1391
1388
|
scope=Scope.JOB,
|
|
@@ -1478,100 +1475,6 @@ def schema_option(cfg):
|
|
|
1478
1475
|
being recorded in the manifest so only turn on this feature
|
|
1479
1476
|
if you have control of the final manifest.""")
|
|
1480
1477
|
|
|
1481
|
-
scparam(cfg, ['option', 'entrypoint'],
|
|
1482
|
-
sctype='str',
|
|
1483
|
-
pernode=PerNode.OPTIONAL,
|
|
1484
|
-
shorthelp="Option: program entry point",
|
|
1485
|
-
switch="-entrypoint <str>",
|
|
1486
|
-
example=["cli: -entrypoint top",
|
|
1487
|
-
"api: chip.set('option', 'entrypoint', 'top')"],
|
|
1488
|
-
schelp="""Alternative entrypoint for compilation and
|
|
1489
|
-
simulation. The default entry point is :keypath:`design`.""")
|
|
1490
|
-
|
|
1491
|
-
scparam(cfg, ['option', 'idir'],
|
|
1492
|
-
sctype='[dir]',
|
|
1493
|
-
shorthelp="Option: design search paths",
|
|
1494
|
-
copy=True,
|
|
1495
|
-
switch=['+incdir+<dir>',
|
|
1496
|
-
'-I <dir>',
|
|
1497
|
-
'-idir <dir>'],
|
|
1498
|
-
example=[
|
|
1499
|
-
"cli: +incdir+./mylib",
|
|
1500
|
-
"cli: -I ./mylib",
|
|
1501
|
-
"cli: -idir ./mylib",
|
|
1502
|
-
"api: chip.set('option', 'idir', './mylib')"],
|
|
1503
|
-
schelp="""
|
|
1504
|
-
Search paths to look for files included in the design using
|
|
1505
|
-
the ```include`` statement.""")
|
|
1506
|
-
|
|
1507
|
-
scparam(cfg, ['option', 'ydir'],
|
|
1508
|
-
sctype='[dir]',
|
|
1509
|
-
shorthelp="Option: design module search paths",
|
|
1510
|
-
copy=True,
|
|
1511
|
-
switch=['-y <dir>',
|
|
1512
|
-
'-ydir <dir>'],
|
|
1513
|
-
example=[
|
|
1514
|
-
"cli: -y './mylib'",
|
|
1515
|
-
"cli: -ydir './mylib'",
|
|
1516
|
-
"api: chip.set('option', 'ydir', './mylib')"],
|
|
1517
|
-
schelp="""
|
|
1518
|
-
Search paths to look for verilog modules found in the the
|
|
1519
|
-
source list. The import engine will look for modules inside
|
|
1520
|
-
files with the specified :keypath:`option,libext` param suffix.""")
|
|
1521
|
-
|
|
1522
|
-
scparam(cfg, ['option', 'vlib'],
|
|
1523
|
-
sctype='[file]',
|
|
1524
|
-
shorthelp="Option: design libraries",
|
|
1525
|
-
copy=True,
|
|
1526
|
-
switch=['-v <file>',
|
|
1527
|
-
'-vlib <file>'],
|
|
1528
|
-
example=["cli: -v './mylib.v'",
|
|
1529
|
-
"cli: -vlib './mylib.v'",
|
|
1530
|
-
"api: chip.set('option', 'vlib', './mylib.v')"],
|
|
1531
|
-
schelp="""
|
|
1532
|
-
List of library files to be read in. Modules found in the
|
|
1533
|
-
libraries are not interpreted as root modules.""")
|
|
1534
|
-
|
|
1535
|
-
scparam(cfg, ['option', 'define'],
|
|
1536
|
-
sctype='[str]',
|
|
1537
|
-
shorthelp="Option: design pre-processor symbol",
|
|
1538
|
-
switch=["-D<str>",
|
|
1539
|
-
"-define <str>"],
|
|
1540
|
-
example=["cli: -DCFG_ASIC=1",
|
|
1541
|
-
"cli: -define CFG_ASIC=1",
|
|
1542
|
-
"api: chip.set('option', 'define', 'CFG_ASIC=1')"],
|
|
1543
|
-
schelp="""Symbol definition for source preprocessor.""")
|
|
1544
|
-
|
|
1545
|
-
scparam(cfg, ['option', 'libext'],
|
|
1546
|
-
sctype='[str]',
|
|
1547
|
-
shorthelp="Option: design file extensions",
|
|
1548
|
-
switch=["+libext+<str>",
|
|
1549
|
-
"-libext <str>"],
|
|
1550
|
-
example=[
|
|
1551
|
-
"cli: +libext+sv",
|
|
1552
|
-
"cli: -libext sv",
|
|
1553
|
-
"api: chip.set('option', 'libext', 'sv')"],
|
|
1554
|
-
schelp="""
|
|
1555
|
-
List of file extensions that should be used for finding modules.
|
|
1556
|
-
For example, if :keypath:`option,ydir` is specified as ./lib", and '.v'
|
|
1557
|
-
is specified as libext then the files ./lib/\\*.v ", will be searched for
|
|
1558
|
-
module matches.""")
|
|
1559
|
-
|
|
1560
|
-
name = 'default'
|
|
1561
|
-
scparam(cfg, ['option', 'param', name],
|
|
1562
|
-
sctype='str',
|
|
1563
|
-
shorthelp="Option: design parameter",
|
|
1564
|
-
switch="-param 'name <str>'",
|
|
1565
|
-
example=[
|
|
1566
|
-
"cli: -param 'N 64'",
|
|
1567
|
-
"api: chip.set('option', 'param', 'N', '64')"],
|
|
1568
|
-
schelp="""
|
|
1569
|
-
Sets a top verilog level design module parameter. The value
|
|
1570
|
-
is limited to basic data literals. The parameter override is
|
|
1571
|
-
passed into tools such as Verilator and Yosys. The parameters
|
|
1572
|
-
support Verilog integer literals (64'h4, 2'b0, 4) and strings.
|
|
1573
|
-
Name of the top level module to compile.""")
|
|
1574
|
-
|
|
1575
1478
|
scparam(cfg, ['option', 'continue'],
|
|
1576
1479
|
sctype='bool',
|
|
1577
1480
|
pernode=PerNode.OPTIONAL,
|
|
@@ -1754,175 +1657,133 @@ def schema_option(cfg):
|
|
|
1754
1657
|
return cfg
|
|
1755
1658
|
|
|
1756
1659
|
|
|
1757
|
-
|
|
1758
|
-
|
|
1759
|
-
|
|
1760
|
-
def schema_package(cfg):
|
|
1761
|
-
|
|
1762
|
-
userid = 'default'
|
|
1660
|
+
def schema_option_frontend(cfg):
|
|
1661
|
+
''' Frontend options
|
|
1662
|
+
'''
|
|
1763
1663
|
|
|
1764
|
-
scparam(cfg, ['
|
|
1765
|
-
sctype='str',
|
|
1766
|
-
scope=Scope.
|
|
1767
|
-
|
|
1768
|
-
|
|
1769
|
-
|
|
1770
|
-
|
|
1771
|
-
|
|
1772
|
-
schelp="""
|
|
1773
|
-
|
|
1664
|
+
scparam(cfg, ['option', 'library'],
|
|
1665
|
+
sctype='[str]',
|
|
1666
|
+
scope=Scope.JOB,
|
|
1667
|
+
pernode=PerNode.OPTIONAL,
|
|
1668
|
+
shorthelp="Option: library list",
|
|
1669
|
+
switch="-library <str>",
|
|
1670
|
+
example=["cli: -library lambdalib_asap7",
|
|
1671
|
+
"api: chip.set('option', 'library', 'lambdalib_asap7')"],
|
|
1672
|
+
schelp="""
|
|
1673
|
+
List of soft libraries to be linked in during import.""")
|
|
1774
1674
|
|
|
1775
|
-
scparam(cfg, ['
|
|
1675
|
+
scparam(cfg, ['option', 'entrypoint'],
|
|
1776
1676
|
sctype='str',
|
|
1777
|
-
|
|
1778
|
-
shorthelp="
|
|
1779
|
-
switch="-
|
|
1780
|
-
example=[
|
|
1781
|
-
|
|
1782
|
-
|
|
1783
|
-
|
|
1784
|
-
managers and summary reports.""")
|
|
1677
|
+
pernode=PerNode.OPTIONAL,
|
|
1678
|
+
shorthelp="Option: program entry point",
|
|
1679
|
+
switch="-entrypoint <str>",
|
|
1680
|
+
example=["cli: -entrypoint top",
|
|
1681
|
+
"api: chip.set('option', 'entrypoint', 'top')"],
|
|
1682
|
+
schelp="""Alternative entrypoint for compilation and
|
|
1683
|
+
simulation. The default entry point is :keypath:`design`.""")
|
|
1785
1684
|
|
|
1786
|
-
scparam(cfg, ['
|
|
1787
|
-
sctype='
|
|
1788
|
-
|
|
1789
|
-
|
|
1790
|
-
switch=
|
|
1685
|
+
scparam(cfg, ['option', 'idir'],
|
|
1686
|
+
sctype='[dir]',
|
|
1687
|
+
shorthelp="Option: design search paths",
|
|
1688
|
+
copy=True,
|
|
1689
|
+
switch=['+incdir+<dir>',
|
|
1690
|
+
'-I <dir>',
|
|
1691
|
+
'-idir <dir>'],
|
|
1791
1692
|
example=[
|
|
1792
|
-
"cli:
|
|
1793
|
-
"
|
|
1794
|
-
|
|
1795
|
-
|
|
1796
|
-
|
|
1797
|
-
|
|
1798
|
-
|
|
1799
|
-
switch="-package_doc_homepage <str>",
|
|
1800
|
-
example=[
|
|
1801
|
-
"cli: -package_doc_homepage index.html",
|
|
1802
|
-
"api: chip.set('package', 'doc', 'homepage', 'index.html')"],
|
|
1803
|
-
schelp="""
|
|
1804
|
-
Package documentation homepage. Filepath to design docs homepage.
|
|
1805
|
-
Complex designs can can include a long non standard list of
|
|
1806
|
-
documents dependent. A single html entry point can be used to
|
|
1807
|
-
present an organized documentation dashboard to the designer.""")
|
|
1808
|
-
|
|
1809
|
-
doctypes = ['datasheet',
|
|
1810
|
-
'reference',
|
|
1811
|
-
'userguide',
|
|
1812
|
-
'quickstart',
|
|
1813
|
-
'releasenotes',
|
|
1814
|
-
'testplan',
|
|
1815
|
-
'signoff',
|
|
1816
|
-
'tutorial']
|
|
1817
|
-
|
|
1818
|
-
for item in doctypes:
|
|
1819
|
-
scparam(cfg, ['package', 'doc', item],
|
|
1820
|
-
sctype='[file]',
|
|
1821
|
-
scope=Scope.GLOBAL,
|
|
1822
|
-
shorthelp=f"Package: {item} document",
|
|
1823
|
-
switch=f"-package_doc_{item} <file>",
|
|
1824
|
-
example=[
|
|
1825
|
-
f"cli: -package_doc_{item} {item}.pdf",
|
|
1826
|
-
f"api: chip.set('package', 'doc', '{item}', '{item}.pdf')"],
|
|
1827
|
-
schelp=f"""Package list of {item} documents.""")
|
|
1693
|
+
"cli: +incdir+./mylib",
|
|
1694
|
+
"cli: -I ./mylib",
|
|
1695
|
+
"cli: -idir ./mylib",
|
|
1696
|
+
"api: chip.set('option', 'idir', './mylib')"],
|
|
1697
|
+
schelp="""
|
|
1698
|
+
Search paths to look for files included in the design using
|
|
1699
|
+
the ```include`` statement.""")
|
|
1828
1700
|
|
|
1829
|
-
scparam(cfg, ['
|
|
1830
|
-
sctype='[
|
|
1831
|
-
|
|
1832
|
-
|
|
1833
|
-
switch=
|
|
1701
|
+
scparam(cfg, ['option', 'ydir'],
|
|
1702
|
+
sctype='[dir]',
|
|
1703
|
+
shorthelp="Option: design module search paths",
|
|
1704
|
+
copy=True,
|
|
1705
|
+
switch=['-y <dir>',
|
|
1706
|
+
'-ydir <dir>'],
|
|
1834
1707
|
example=[
|
|
1835
|
-
"cli: -
|
|
1836
|
-
"
|
|
1837
|
-
|
|
1708
|
+
"cli: -y './mylib'",
|
|
1709
|
+
"cli: -ydir './mylib'",
|
|
1710
|
+
"api: chip.set('option', 'ydir', './mylib')"],
|
|
1711
|
+
schelp="""
|
|
1712
|
+
Search paths to look for verilog modules found in the the
|
|
1713
|
+
source list. The import engine will look for modules inside
|
|
1714
|
+
files with the specified :keypath:`option,libext` param suffix.""")
|
|
1838
1715
|
|
|
1839
|
-
scparam(cfg, ['
|
|
1716
|
+
scparam(cfg, ['option', 'vlib'],
|
|
1840
1717
|
sctype='[file]',
|
|
1841
|
-
|
|
1842
|
-
|
|
1843
|
-
switch=
|
|
1844
|
-
|
|
1845
|
-
|
|
1846
|
-
|
|
1847
|
-
|
|
1848
|
-
|
|
1849
|
-
|
|
1718
|
+
shorthelp="Option: design libraries",
|
|
1719
|
+
copy=True,
|
|
1720
|
+
switch=['-v <file>',
|
|
1721
|
+
'-vlib <file>'],
|
|
1722
|
+
example=["cli: -v './mylib.v'",
|
|
1723
|
+
"cli: -vlib './mylib.v'",
|
|
1724
|
+
"api: chip.set('option', 'vlib', './mylib.v')"],
|
|
1725
|
+
schelp="""
|
|
1726
|
+
List of library files to be read in. Modules found in the
|
|
1727
|
+
libraries are not interpreted as root modules.""")
|
|
1850
1728
|
|
|
1851
|
-
scparam(cfg, ['
|
|
1729
|
+
scparam(cfg, ['option', 'define'],
|
|
1852
1730
|
sctype='[str]',
|
|
1853
|
-
|
|
1854
|
-
|
|
1855
|
-
|
|
1856
|
-
example=[
|
|
1857
|
-
|
|
1858
|
-
|
|
1859
|
-
schelp="""
|
|
1860
|
-
blank if not applicable.""")
|
|
1861
|
-
|
|
1862
|
-
record = ['name',
|
|
1863
|
-
'email',
|
|
1864
|
-
'username',
|
|
1865
|
-
'location',
|
|
1866
|
-
'organization',
|
|
1867
|
-
'publickey']
|
|
1868
|
-
|
|
1869
|
-
for item in record:
|
|
1870
|
-
scparam(cfg, ['package', 'author', userid, item],
|
|
1871
|
-
sctype='str',
|
|
1872
|
-
scope=Scope.GLOBAL,
|
|
1873
|
-
shorthelp=f"Package: author {item}",
|
|
1874
|
-
switch=f"-package_author_{item} 'userid <str>'",
|
|
1875
|
-
example=[
|
|
1876
|
-
f"cli: -package_author_{item} 'wiley wiley@acme.com'",
|
|
1877
|
-
f"api: chip.set('package', 'author', 'wiley', '{item}', 'wiley@acme.com')"],
|
|
1878
|
-
schelp=f"""Package author {item} provided with full name as key and
|
|
1879
|
-
{item} as value.""")
|
|
1880
|
-
|
|
1881
|
-
source = 'default'
|
|
1731
|
+
shorthelp="Option: design pre-processor symbol",
|
|
1732
|
+
switch=["-D<str>",
|
|
1733
|
+
"-define <str>"],
|
|
1734
|
+
example=["cli: -DCFG_ASIC=1",
|
|
1735
|
+
"cli: -define CFG_ASIC=1",
|
|
1736
|
+
"api: chip.set('option', 'define', 'CFG_ASIC=1')"],
|
|
1737
|
+
schelp="""Symbol definition for source preprocessor.""")
|
|
1882
1738
|
|
|
1883
|
-
scparam(cfg, ['
|
|
1884
|
-
sctype='str',
|
|
1885
|
-
|
|
1886
|
-
|
|
1887
|
-
|
|
1888
|
-
example=[
|
|
1889
|
-
"cli:
|
|
1890
|
-
"
|
|
1891
|
-
"api: chip.set('
|
|
1892
|
-
|
|
1893
|
-
|
|
1894
|
-
|
|
1895
|
-
|
|
1896
|
-
|
|
1897
|
-
* file:///path/on/network/drive
|
|
1898
|
-
* git+https://github.com/xyz/xyz
|
|
1899
|
-
* git://github.com/xyz/xyz
|
|
1900
|
-
* git+ssh://github.com/xyz/xyz
|
|
1901
|
-
* ssh://github.com/xyz/xyz
|
|
1902
|
-
* https://github.com/xyz/xyz/archive
|
|
1903
|
-
* https://zeroasic.com/xyz.tar.gz
|
|
1904
|
-
* python://siliconcompiler
|
|
1905
|
-
""")
|
|
1739
|
+
scparam(cfg, ['option', 'libext'],
|
|
1740
|
+
sctype='[str]',
|
|
1741
|
+
shorthelp="Option: design file extensions",
|
|
1742
|
+
switch=["+libext+<str>",
|
|
1743
|
+
"-libext <str>"],
|
|
1744
|
+
example=[
|
|
1745
|
+
"cli: +libext+sv",
|
|
1746
|
+
"cli: -libext sv",
|
|
1747
|
+
"api: chip.set('option', 'libext', 'sv')"],
|
|
1748
|
+
schelp="""
|
|
1749
|
+
List of file extensions that should be used for finding modules.
|
|
1750
|
+
For example, if :keypath:`option,ydir` is specified as ./lib", and '.v'
|
|
1751
|
+
is specified as libext then the files ./lib/\\*.v ", will be searched for
|
|
1752
|
+
module matches.""")
|
|
1906
1753
|
|
|
1907
|
-
|
|
1754
|
+
name = 'default'
|
|
1755
|
+
scparam(cfg, ['option', 'param', name],
|
|
1908
1756
|
sctype='str',
|
|
1909
|
-
|
|
1910
|
-
|
|
1911
|
-
switch="-package_source_ref 'source <str>'",
|
|
1757
|
+
shorthelp="Option: design parameter",
|
|
1758
|
+
switch="-param 'name <str>'",
|
|
1912
1759
|
example=[
|
|
1913
|
-
"cli: -
|
|
1914
|
-
"api: chip.set('
|
|
1915
|
-
schelp="""
|
|
1760
|
+
"cli: -param 'N 64'",
|
|
1761
|
+
"api: chip.set('option', 'param', 'N', '64')"],
|
|
1762
|
+
schelp="""
|
|
1763
|
+
Sets a top verilog level design module parameter. The value
|
|
1764
|
+
is limited to basic data literals. The parameter override is
|
|
1765
|
+
passed into tools such as Verilator and Yosys. The parameters
|
|
1766
|
+
support Verilog integer literals (64'h4, 2'b0, 4) and strings.
|
|
1767
|
+
Name of the top level module to compile.""")
|
|
1916
1768
|
|
|
1917
1769
|
return cfg
|
|
1918
1770
|
|
|
1919
1771
|
|
|
1772
|
+
############################################
|
|
1773
|
+
# Package information
|
|
1774
|
+
############################################
|
|
1775
|
+
def schema_package(cfg):
|
|
1776
|
+
from siliconcompiler.packageschema import PackageSchema
|
|
1777
|
+
cfg.insert("package", PackageSchema())
|
|
1778
|
+
return cfg
|
|
1779
|
+
|
|
1780
|
+
|
|
1920
1781
|
############################################
|
|
1921
1782
|
# Design Checklist
|
|
1922
1783
|
############################################
|
|
1923
1784
|
def schema_checklist(cfg):
|
|
1924
1785
|
from siliconcompiler.checklist import ChecklistSchema
|
|
1925
|
-
cfg.insert("checklist", "default", ChecklistSchema())
|
|
1786
|
+
cfg.insert("checklist", "default", ChecklistSchema(None))
|
|
1926
1787
|
return cfg
|
|
1927
1788
|
|
|
1928
1789
|
|