siliconcompiler 0.33.2__py3-none-any.whl → 0.34.1__py3-none-any.whl

siliconcompiler/tools/__init__.py

@@ -18,6 +18,7 @@ from siliconcompiler.tools import openroad
 from siliconcompiler.tools import opensta
 from siliconcompiler.tools import slang
 from siliconcompiler.tools import surelog
+from siliconcompiler.tools import surfer
 from siliconcompiler.tools.sv2v import sv2v
 from siliconcompiler.tools.verilator import verilator
 from siliconcompiler.tools.vivado import vivado
@@ -53,6 +54,7 @@ def get_tools():
             opensta,
             slang,
             surelog,
+            surfer,
             sv2v,
             verilator,
             vivado,

siliconcompiler/tools/builtin/_common.py

@@ -83,10 +83,10 @@ def _minmax(chip, *nodes, op=None):
                     real = chip.get('metric', metric, step=step, index=index)
                     if real is None:
                         raise SiliconCompilerError(
-                            f'Metric {metric} has goal for {step}{index} '
+                            f'Metric {metric} has goal for {step}/{index} '
                             'but it has not been set.', chip=chip)
                     if abs(real) > goal:
-                        chip.logger.warning(f"Step {step}{index} failed "
+                        chip.logger.warning(f"Step {step}/{index} failed "
                                             f"because it didn't meet goals for '{metric}' "
                                             "metric.")
                         failed[step][index] = True
@@ -122,7 +122,7 @@ def _minmax(chip, *nodes, op=None):
             real = chip.get('metric', metric, step=step, index=index)
             if real is None:
                 raise SiliconCompilerError(
-                    f'Metric {metric} has weight for {step}{index} '
+                    f'Metric {metric} has weight for {step}/{index} '
                     'but it has not been set.', chip=chip)
 
             if not (max_val[metric] - min_val[metric]) == 0:
@@ -153,10 +153,10 @@ def _select_inputs(chip, step, index):
 
     flow = chip.get('option', 'flow')
 
-    flow_schema = chip.schema.get("flowgraph", flow, field="schema")
+    flow_schema = chip.get("flowgraph", flow, field="schema")
     runtime = RuntimeFlowgraph(
         flow_schema,
         from_steps=set([step for step, _ in flow_schema.get_entry_nodes()]),
         prune_nodes=chip.get('option', 'prune'))
 
-    return runtime.get_node_inputs(step, index, record=chip.schema.get("record", field="schema"))
+    return runtime.get_node_inputs(step, index, record=chip.get("record", field="schema"))

siliconcompiler/tools/builtin/concatenate.py

@@ -3,7 +3,7 @@ import os
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
-from siliconcompiler import scheduler
+from siliconcompiler.scheduler.schedulernode import SchedulerNode
 
 
 def make_docs(chip):
@@ -11,8 +11,8 @@ def make_docs(chip):
     _make_docs(chip)
     chip.set('option', 'flow', 'asicflow')
 
-    for step, index in chip.schema.get("flowgraph", "asicflow", field="schema").get_entry_nodes():
-        scheduler._setup_node(chip, step, index)
+    for step, index in chip.get("flowgraph", "asicflow", field="schema").get_entry_nodes():
+        SchedulerNode(chip, step, index).setup()
 
     chip.set('arg', 'step', 'import.combine')
     chip.set('arg', 'index', '0')
@@ -64,10 +64,10 @@ def _gather_outputs(chip, step, index):
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
     in_task_outputs = []
     for in_step, in_index in in_nodes:
-        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
-        task_class = chip.get("tool", in_tool, field="schema")
-        task_class.set_runtime(chip, step=in_step, index=in_index)
-        in_task_outputs.append(task_class.get_output_files())
+        in_tool, in_task = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, "task", in_task, field="schema")
+        with task_class.runtime(chip, step=in_step, index=in_index) as task:
+            in_task_outputs.append(task.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].union(*in_task_outputs[1:])

siliconcompiler/tools/builtin/minimum.py

@@ -43,10 +43,10 @@ def _gather_outputs(chip, step, index):
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
     in_task_outputs = []
     for in_step, in_index in in_nodes:
-        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
-        task_class = chip.get("tool", in_tool, field="schema")
-        task_class.set_runtime(chip, step=in_step, index=in_index)
-        in_task_outputs.append(task_class.get_output_files())
+        in_tool, in_task = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, "task", in_task, field="schema")
+        with task_class.runtime(chip, step=in_step, index=in_index) as task:
+            in_task_outputs.append(task.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].intersection(*in_task_outputs[1:])

siliconcompiler/tools/builtin/mux.py

@@ -57,10 +57,10 @@ def _gather_outputs(chip, step, index):
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
     in_task_outputs = []
     for in_step, in_index in in_nodes:
-        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
-        task_class = chip.get("tool", in_tool, field="schema")
-        task_class.set_runtime(chip, step=in_step, index=in_index)
-        in_task_outputs.append(task_class.get_output_files())
+        in_tool, in_task = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, "task", in_task, field="schema")
+        with task_class.runtime(chip, step=in_step, index=in_index) as task:
+            in_task_outputs.append(task.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].intersection(*in_task_outputs[1:])

siliconcompiler/tools/builtin/nop.py

@@ -24,10 +24,10 @@ def _gather_outputs(chip, step, index):
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
     in_task_outputs = []
     for in_step, in_index in in_nodes:
-        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
-        task_class = chip.get("tool", in_tool, field="schema")
-        task_class.set_runtime(chip, step=in_step, index=in_index)
-        in_task_outputs.append(task_class.get_output_files())
+        in_tool, in_task = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, "task", in_task, field="schema")
+        with task_class.runtime(chip, step=in_step, index=in_index) as task:
+            in_task_outputs.append(task.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].union(*in_task_outputs[1:])

siliconcompiler/tools/builtin/verify.py

@@ -1,6 +1,5 @@
 from siliconcompiler.tools.builtin import _common
 from siliconcompiler.schema.parametertype import NodeType
-from siliconcompiler.scheduler import _haltstep
 from siliconcompiler.tools.builtin.builtin import set_io_files
 from siliconcompiler import utils, SiliconCompilerError
 from siliconcompiler.tools._common import get_tool_task
@@ -26,13 +25,13 @@ def _select_inputs(chip, step, index):
     inputs = _common._select_inputs(chip, step, index)
     if len(inputs) != 1:
         raise SiliconCompilerError(
-            f'{step}{index} receives {len(inputs)} inputs, but only supports one', chip=chip)
+            f'{step}/{index} receives {len(inputs)} inputs, but only supports one', chip=chip)
     inputs = inputs[0]
     flow = chip.get('option', 'flow')
     arguments = chip.get('flowgraph', flow, step, index, 'args')
 
     if len(arguments) == 0:
-        raise SiliconCompilerError(f'{step}{index} requires arguments for verify', chip=chip)
+        raise SiliconCompilerError(f'{step}/{index} requires arguments for verify', chip=chip)
 
     passes = True
     for criteria in arguments:
@@ -56,10 +55,10 @@ def _select_inputs(chip, step, index):
         metric_type = chip.get('metric', metric, field=None)
         goal = NodeType.normalize(goal, metric_type.get(field='type'))
         if not utils.safecompare(chip, value, op, goal):
-            chip.error(f"{step}{index} fails '{metric}' metric: {value}{op}{goal}")
+            chip.error(f"{step}/{index} fails '{metric}' metric: {value}{op}{goal}")
 
     if not passes:
-        _haltstep(chip, flow, step, index)
+        return []
 
     return inputs
 
@@ -70,10 +69,10 @@ def _gather_outputs(chip, step, index):
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
     in_task_outputs = []
     for in_step, in_index in in_nodes:
-        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
-        task_class = chip.get("tool", in_tool, field="schema")
-        task_class.set_runtime(chip, step=in_step, index=in_index)
-        in_task_outputs.append(task_class.get_output_files())
+        in_tool, in_task = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, "task", in_task, field="schema")
+        with task_class.runtime(chip, step=in_step, index=in_index) as task:
+            in_task_outputs.append(task.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].intersection(*in_task_outputs[1:])

siliconcompiler/tools/execute/exec_input.py

@@ -34,7 +34,7 @@ def pre_process(chip):
         break
 
     if not exec:
-        chip.error(f'{step}{index} did not receive an executable file')
+        chip.error(f'{step}/{index} did not receive an executable file')
 
     chip.set('tool', tool, 'exe', exec)
 

siliconcompiler/tools/genfasm/genfasm.py

@@ -1,5 +1,4 @@
 from siliconcompiler.tools.vpr.vpr import parse_version as vpr_parse_version
-from siliconcompiler.tools.vpr.vpr import normalize_version as vpr_normalize_version
 from siliconcompiler.tools.vpr.vpr import add_tool_requirements as add_vpr_requirements
 
 '''
@@ -24,7 +23,7 @@ def make_docs(chip):
 def setup(chip):
     chip.set('tool', 'genfasm', 'exe', 'genfasm', clobber=False)
     chip.set('tool', 'genfasm', 'vswitch', '--version')
-    chip.set('tool', 'genfasm', 'version', '>=9.0.0', clobber=False)
+    chip.set('tool', 'genfasm', 'version', '>=v8.0.0-12677', clobber=False)
 
     add_tool_requirements(chip)
 
@@ -37,10 +36,6 @@ def parse_version(chip):
     return vpr_parse_version(chip)
 
 
-def normalize_version(chip):
-    return vpr_normalize_version(chip)
-
-
 ##################################################
 if __name__ == "__main__":
     chip = make_docs()

siliconcompiler/tools/openroad/_apr.py

@@ -646,6 +646,10 @@ def define_gpl_params(chip):
                       default_value='true',
                       schelp='true/false, when enabled a global placement is performed without '
                              'considering the impact of the pin placements')
+    set_tool_task_var(chip, param_key='gpl_enable_skip_initial_place',
+                      default_value='false',
+                      schelp='true/false, when enabled a global placement skips the initial '
+                             'placement, before the main global placement pass.')
 
 
 def define_dpo_params(chip):
@@ -654,7 +658,7 @@ def define_dpo_params(chip):
                       schelp='true/false, when true the detailed placement optimization '
                              'will be performed')
     set_tool_task_var(chip, param_key='dpo_max_displacement',
-                      default_value='0',
+                      default_value='5',
                       schelp='maximum cell movement in detailed placement optimization in microns, '
                              '0 will result in the tool default maximum displacement')
 

siliconcompiler/tools/openroad/antenna_repair.py

@@ -68,7 +68,7 @@ def pre_process(chip):
             chip.get('tool', tool, 'task', task, 'var', 'ant_check',
                      step=step, index=index)[0] == 'false':
         chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
-        chip.logger.warning(f'{step}{index} will be skipped since antenna repair is disabled.')
+        chip.logger.warning(f'{step}/{index} will be skipped since antenna repair is disabled.')
         return
 
     define_ord_files(chip)

siliconcompiler/tools/openroad/macro_placement.py

@@ -62,7 +62,7 @@ def pre_process(chip):
             for in_step, in_index in input_nodes
             ]):
         chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
-        chip.logger.warning(f'{step}{index} will be skipped since are no macros to place.')
+        chip.logger.warning(f'{step}/{index} will be skipped since are no macros to place.')
         return
 
     build_pex_corners(chip)

siliconcompiler/tools/openroad/power_grid.py

@@ -60,7 +60,7 @@ def pre_process(chip):
             (chip.get('tool', tool, 'task', task, 'var', 'pdn_enable',
                       step=step, index=index)[0] == 'false' or len(pdncfg) == 0):
         chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
-        chip.logger.warning(f'{step}{index} will be skipped since power grid is disabled.')
+        chip.logger.warning(f'{step}/{index} will be skipped since power grid is disabled.')
         return
 
     define_ord_files(chip)

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -68,6 +68,8 @@ proc sc_global_placement { args } {
     set gpl_routability_driven [lindex [sc_cfg_tool_task_get var gpl_routability_driven] 0]
     set gpl_timing_driven [lindex [sc_cfg_tool_task_get var gpl_timing_driven] 0]
     set gpl_padding [lindex [sc_cfg_tool_task_get var pad_global_place] 0]
+    set gpl_enable_skip_initial_place [lindex \
+        [sc_cfg_tool_task_get var gpl_enable_skip_initial_place] 0]
 
     set gpl_args []
     if {
@@ -79,6 +81,9 @@ proc sc_global_placement { args } {
     if { $gpl_timing_driven == "true" } {
         lappend gpl_args "-timing_driven"
     }
+    if { $gpl_enable_skip_initial_place == "true" } {
+        lappend gpl_args "-skip_initial_place"
+    }
 
     if { [info exists flags(-skip_io)] } {
         lappend gpl_args "-skip_io"
@@ -634,36 +639,38 @@ proc sc_setup_sta { } {
         set_timing_derate -late $sta_late_timing_derate
     }
 
-    # Create path groups
-    if {
-        [lindex [sc_cfg_tool_task_get var sta_define_path_groups] 0] == "true" &&
-        [llength [sta::path_group_names]] == 0
-    } {
-        sc_path_group -name in2out -from [all_inputs -no_clocks] -to [all_outputs]
-
+    if { [sc_check_version 19370] } {
+        # Create path groups
         if {
-            [llength [all_clocks]] == 1 ||
-            [lindex [sc_cfg_tool_task_get var sta_unique_path_groups_per_clock] 0] == "false"
+            [lindex [sc_cfg_tool_task_get var sta_define_path_groups] 0] == "true" &&
+            [llength [sta::path_group_names]] == 0
         } {
-            sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
-            sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
-            sc_path_group -name reg2out -from [all_registers] -to [all_outputs]
-        } else {
-            foreach clock [all_clocks] {
-                set clk_name [get_property $clock name]
-                sc_path_group -name in2reg.${clk_name} \
-                    -from [all_inputs -no_clocks] \
-                    -to [all_registers -clock $clock]
-                sc_path_group -name reg2reg.${clk_name} \
-                    -from [all_registers -clock $clock] \
-                    -to [all_registers -clock $clock]
-                sc_path_group -name reg2out.${clk_name} \
-                    -from [all_registers -clock $clock] \
-                    -to [all_outputs]
+            sc_path_group -name in2out -from [all_inputs -no_clocks] -to [all_outputs]
+
+            if {
+                [llength [all_clocks]] == 1 ||
+                [lindex [sc_cfg_tool_task_get var sta_unique_path_groups_per_clock] 0] == "false"
+            } {
+                sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
+                sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
+                sc_path_group -name reg2out -from [all_registers] -to [all_outputs]
+            } else {
+                foreach clock [all_clocks] {
+                    set clk_name [get_property $clock name]
+                    sc_path_group -name in2reg.${clk_name} \
+                        -from [all_inputs -no_clocks] \
+                        -to [all_registers -clock $clock]
+                    sc_path_group -name reg2reg.${clk_name} \
+                        -from [all_registers -clock $clock] \
+                        -to [all_registers -clock $clock]
+                    sc_path_group -name reg2out.${clk_name} \
+                        -from [all_registers -clock $clock] \
+                        -to [all_outputs]
+                }
             }
         }
+        utl::info FLW 1 "Timing path groups: [sta::path_group_names]"
     }
-    utl::info FLW 1 "Timing path groups: [sta::path_group_names]"
 
     # Check timing setup
     if { [sc_cfg_tool_task_check_in_list check_setup var reports] } {

siliconcompiler/tools/opensta/timing.py

@@ -1,6 +1,7 @@
 import os
 import re
 from siliconcompiler import utils
+from siliconcompiler import NodeStatus
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler.tools.opensta import setup as tool_setup
 from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
@@ -28,14 +29,14 @@ def setup(chip):
 
     design = chip.top()
     if f'{design}.vg' in input_provides(chip, step, index):
-        chip.set('tool', tool, 'task', task, 'input', f'{design}.vg',
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.vg',
                  step=step, index=index)
     else:
-        chip.set('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
+        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
                  step=step, index=index)
 
     if f'{design}.sdc' in input_provides(chip, step, index):
-        chip.set('tool', tool, 'task', task, 'input', f'{design}.sdc',
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.sdc',
                  step=step, index=index)
     elif chip.valid('input', 'constraint', 'sdc') and \
             chip.get('input', 'constraint', 'sdc', step=step, index=index):
@@ -84,6 +85,28 @@ def setup(chip):
     add_common_file(chip, 'opensta_generic_sdc', 'sdc/sc_constraints.sdc')
 
 
+def pre_process(chip):
+    '''
+    Tool specific function to run before step execution
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    # If a verilog and sdc file are both provided as input to this tool, but they
+    # are both empty, skip this tool step.
+    design = chip.top()
+    if (f'{design}.vg' in input_provides(chip, step, index)) and \
+            (f'{design}.sdc' in input_provides(chip, step, index)):
+        if os.path.getsize(f'inputs/{design}.vg') == 0 and \
+                os.path.getsize(f'inputs/{design}.sdc') == 0:
+            chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
+            chip.logger.warning(f'{step}/{index} will be skipped since no timing '
+                                'analysis files were provided.')
+            return
+
+
 def __report_map(chip, metric, basefile):
     corners = chip.getkeys('constraint', 'timing')
     mapping = {

siliconcompiler/tools/slang/__init__.py

@@ -212,5 +212,5 @@ def _diagnostics(chip, driver, compilation):
     for diag in compilation.getAllDiagnostics():
         diags.issue(diag)
 
-    record_metric(chip, step, index, 'errors', diags.numErrors, [f'sc_{step}{index}.log'])
-    record_metric(chip, step, index, 'warnings', diags.numWarnings, [f'sc_{step}{index}.log'])
+    record_metric(chip, step, index, 'errors', diags.numErrors, [f'sc_{step}_{index}.log'])
+    record_metric(chip, step, index, 'warnings', diags.numWarnings, [f'sc_{step}_{index}.log'])

siliconcompiler/tools/surfer/show.py

@@ -0,0 +1,53 @@
+import os
+from siliconcompiler.tools._common import add_require_input, get_tool_task, input_provides
+
+
+def setup(chip):
+    '''
+    Show a VCD file.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    # Standard setup
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=0.3.0', clobber=False)
+
+    # Require VCD file
+    if f'{chip.top()}.vcd' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', f'{chip.top()}.vcd',
+                 step=step, index=index)
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'show_filepath']),
+                 step=step, index=index)
+    else:
+        add_require_input(chip, 'input', 'waveform', 'vcd')
+
+    # Don't exit on show
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit', False,
+             step=step, index=index, clobber=False)
+
+
+def runtime_options(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    options = []
+
+    # Get VCD file
+    if os.path.exists(f'inputs/{chip.top()}.vcd'):
+        dump = f'inputs/{chip.top()}.vcd'
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        dump = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',
+                        step=step, index=index)[0]
+    else:
+        dump = chip.find_files('input', 'waveform', 'vcd', step=step, index=index)[0]
+    options.append(dump)
+
+    return options

siliconcompiler/tools/surfer/surfer.py

@@ -0,0 +1,30 @@
+'''
+Surfer is a waveform viewer with a focus on a snappy usable
+interface and extensibility.
+
+Documentation: https://gitlab.com/surfer-project/surfer/-/wikis/home
+
+Sources: https://gitlab.com/surfer-project/surfer
+
+Installation: https://gitlab.com/surfer-project/surfer#installation
+'''
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    from siliconcompiler.tools.surfer import show
+    show.setup(chip)
+    return chip
+
+
+def parse_version(stdout):
+    # surfer 0.3.0
+    return stdout.strip().split()[1]
+
+
+####################################################################
+if __name__ == "__main__":
+    chip = make_docs()
+    chip.write_manifest("surfer.json")

siliconcompiler/tools/vpr/route.py

@@ -44,6 +44,48 @@ def setup(chip, clobber=True):
     chip.add('tool', tool, 'task', task, 'output', design + '.net', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.place', step=step, index=index)
 
+    # Add a parameter for generating a post-implementation netlist for external
+    # static timing analysis.
+    if vpr.use_timing_analysis(chip):
+        chip.set('tool', tool, 'task', task, 'var', 'gen_post_implementation_netlist',
+                 True, step=step, index=index, clobber=False)
+    else:
+        chip.set('tool', tool, 'task', task, 'var', 'gen_post_implementation_netlist',
+                 False, step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'gen_post_implementation_netlist',
+             'set to true to have VPR generate a post-implementation netlist',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'gen_post_implementation_netlist']),
+             step=step, index=index)
+
+    # Add a parameter to control the timing corner used when generating SDF files.
+    chip.set('tool', tool, 'task', task, 'var', 'timing_corner', 'typical',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'timing_corner',
+             'set the timing corner for files generated by the post-implementation netlist',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'timing_corner']),
+             step=step, index=index)
+
+    # Add the post-implementation timing netlist outputs for the timing step.
+    # These files must always be generated so nodes that are connected after this
+    # step that are expecting these files do not complain if they are not generated.
+    timing_corner = chip.get('tool', tool, 'task', task, 'var', 'timing_corner',
+                             step=step, index=index)[0]
+
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.sdc',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.{timing_corner}.sdf',
+             step=step, index=index)
+
 
 def runtime_options(chip):
     '''Command line options to vpr for the route step
@@ -104,6 +146,21 @@ def runtime_options(chip):
         options.append("--graphics_commands")
         options.append(graphics_command_str)
 
+    # Generate a post-implementation netlist for use in external timing analysis
+    # if requested.
+    gen_post_implementation_netlist = chip.get('tool', tool, 'task', task, 'var',
+                                               'gen_post_implementation_netlist',
+                                               step=step, index=index)[0]
+    if gen_post_implementation_netlist == 'true':
+        # Generate the netlist.
+        options.extend(["--gen_post_synthesis_netlist", "on"])
+        # Generate the SDC file.
+        options.extend(["--gen_post_implementation_sdc", "on"])
+        # Create undriven nets for unconnected inputs.
+        options.extend(["--post_synth_netlist_unconn_inputs", "nets"])
+        # Turn off module parameters.
+        options.extend(["--post_synth_netlist_module_parameters", "off"])
+
     return options
 
 
@@ -122,3 +179,28 @@ def post_process(chip):
     shutil.copy2(f'inputs/{design}.blif', 'outputs')
     shutil.copy2(f'inputs/{design}.net', 'outputs')
     shutil.copy2(f'inputs/{design}.place', 'outputs')
+
+    # Copy and rename the post-implementation netlist results into the output
+    # directory to be used in external timing analysis.
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    gen_post_implementation_netlist = chip.get('tool', tool, 'task', task, 'var',
+                                               'gen_post_implementation_netlist',
+                                               step=step, index=index)[0]
+    timing_corner = chip.get('tool', tool, 'task', task, 'var', 'timing_corner',
+                             step=step, index=index)[0]
+
+    if vpr.use_timing_analysis(chip) and gen_post_implementation_netlist == 'true':
+        # These files will only exist if timing analysis is on and VPR was told
+        # to generate them.
+        shutil.move(f'{design}_post_synthesis.v', f'outputs/{design}.vg')
+        shutil.move(f'{design}_post_synthesis.sdc', f'outputs/{design}.sdc')
+        shutil.move(f'{design}_post_synthesis.sdf', f'outputs/{design}.{timing_corner}.sdf')
+    else:
+        # If timing analysis is on or we are not generating a post-implementation
+        # netlist, just produce blank files. These will trigger any future nodes
+        # that use them to skip.
+        open(f'outputs/{design}.vg', 'a')
+        open(f'outputs/{design}.sdc', 'a')
+        open(f'outputs/{design}.{timing_corner}.sdf', 'a')