siliconcompiler 0.32.3__py3-none-any.whl → 0.33.1__py3-none-any.whl

siliconcompiler/tools/yosys/sc_synth_asic.tcl

@@ -32,18 +32,85 @@ set sc_pdk [sc_cfg_get option pdk]
 
 source "$sc_refdir/procs.tcl"
 
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
+if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
+    set sc_macro_libraries \
+        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
+} else {
+    set sc_macro_libraries []
+}
+set sc_mainlib [lindex $sc_logiclibs 0]
+
+set sc_abc_constraints \
+    [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
+
+set sc_blackboxes []
+foreach lib $sc_macrolibs {
+    if { [sc_cfg_exists library $lib output blackbox verilog] } {
+        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
+            lappend sc_blackboxes $lib_f
+        }
+    }
+}
+
+set sc_memory_libmap_files ""
+if { [sc_cfg_tool_task_exists file memory_libmap] } {
+    set sc_memory_libmap_files [sc_cfg_tool_task_get file memory_libmap]
+}
+
+set sc_memory_techmap_files ""
+if { [sc_cfg_tool_task_exists file memory_techmap] } {
+    set sc_memory_techmap_files [sc_cfg_tool_task_get file memory_techmap]
+}
+
+########################################################
+# Read Libraries
+########################################################
+
+foreach lib_file "$sc_libraries $sc_macro_libraries" {
+    yosys read_liberty -overwrite -setattr liberty_cell -lib $lib_file
+    yosys read_liberty -overwrite -setattr liberty_cell \
+        -unit_delay -wb -ignore_miss_func -ignore_buses $lib_file
+}
+foreach bb_file $sc_blackboxes {
+    yosys log "Reading blackbox model file: $bb_file"
+    yosys read_verilog -setattr blackbox -sv $bb_file
+}
+
+# Before working on the design, we mask out any module supplied via
+# `blackbox_modules`. This allows synthesis of parts of the design without having
+# to modify the input RTL.
+if { [sc_cfg_tool_task_exists var blackbox_modules] } {
+    foreach bb [sc_cfg_tool_task_get var blackbox_modules] {
+        foreach module [get_modules $bb] {
+            yosys log "Blackboxing module: $module"
+            yosys blackbox $module
+        }
+    }
+}
+
 ########################################################
 # Design Inputs
 ########################################################
 
 set input_verilog "inputs/$sc_design.v"
 if { ![file exists $input_verilog] } {
-    set input_verilog []
-    if { [sc_cfg_exists input rtl systemverilog] } {
-        lappend input_verilog {*}[sc_cfg_get input rtl systemverilog]
-    }
-    if { [sc_cfg_exists input rtl verilog] } {
-        lappend input_verilog {*}[sc_cfg_get input rtl verilog]
+    set input_verilog "inputs/$sc_design.sv"
+    if { ![file exists $input_verilog] } {
+        set input_verilog []
+        if { [sc_cfg_exists input rtl systemverilog] } {
+            lappend input_verilog {*}[sc_cfg_get input rtl systemverilog]
+        }
+        if { [sc_cfg_exists input rtl verilog] } {
+            lappend input_verilog {*}[sc_cfg_get input rtl verilog]
+        }
     }
 }
 
@@ -63,9 +130,12 @@ if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugi
     yosys read_slang \
         -D SYNTHESIS \
         --keep-hierarchy \
+        --ignore-assertions \
+        --allow-use-before-declare \
         --top $sc_design \
         {*}$slang_params \
         {*}$input_verilog
+    yosys setattr -unset init
 } else {
     # Use -noblackbox to correctly interpret empty modules as empty,
     # actual black boxes are read in later
@@ -119,42 +189,43 @@ proc get_modules { { find "*" } } {
     return [lsort $modules]
 }
 
-####################
-# DESIGNER's CHOICE
-####################
-
-set sc_logiclibs [sc_get_asic_libraries logic]
-set sc_macrolibs [sc_get_asic_libraries macro]
-
-set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
-if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
-    set sc_macro_libraries \
-        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
-} else {
-    set sc_macro_libraries []
-}
-set sc_mainlib [lindex $sc_logiclibs 0]
-
-set sc_abc_constraints \
-    [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
-
-set sc_blackboxes []
-foreach lib $sc_macrolibs {
-    if { [sc_cfg_exists library $lib output blackbox verilog] } {
-        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
-            lappend sc_blackboxes $lib_f
+proc sc_annotate_gate_cost_equivalent { } {
+    yosys cellmatch -derive_luts =A:liberty_cell
+    # find a reference nand2 gate
+    set found_cell ""
+    set found_cell_area ""
+    # iterate over all cells with a nand2 signature
+    yosys echo off
+    set nand2_cells [yosys tee -q -s result.string select -list-mod =*/a:lut=4'b0111 %m]
+    yosys echo on
+    foreach cell $nand2_cells {
+        if { ![rtlil::has_attr -mod $cell area] } {
+            puts "WARNING: Cell $cell missing area information"
+            continue
+        }
+        set area [rtlil::get_attr -string -mod $cell area]
+        if { $found_cell == "" || $area < $found_cell_area } {
+            set found_cell $cell
+            set found_cell_area $area
         }
     }
-}
-
-set sc_memory_libmap_files ""
-if { [sc_cfg_tool_task_exists file memory_libmap] } {
-    set sc_memory_libmap_files [sc_cfg_tool_task_get file memory_libmap]
-}
+    if { $found_cell == "" } {
+        set found_cell_area 1
+        puts "WARNING: reference nand2 cell not found, using $found_cell_area as area"
+    } else {
+        puts "Using nand2 reference cell ($found_cell) with area: $found_cell_area"
+    }
 
-set sc_memory_techmap_files ""
-if { [sc_cfg_tool_task_exists file memory_techmap] } {
-    set sc_memory_techmap_files [sc_cfg_tool_task_get file memory_techmap]
+    # convert the area on all Liberty cells to a gate number equivalent
+    yosys echo off
+    set cells [yosys tee -q -s result.string select -list-mod =A:area =A:liberty_cell %i]
+    yosys echo on
+    foreach cell $cells {
+        set area [rtlil::get_attr -mod -string $cell area]
+        set gate_eq [expr { int(max(1, ceil($area / $found_cell_area))) }]
+        puts "Setting gate_cost_equivalent for $cell as $gate_eq"
+        rtlil::set_attr -mod -uint $cell gate_cost_equivalent $gate_eq
+    }
 }
 
 #########################
@@ -209,34 +280,10 @@ proc get_buffer_cell { } {
     return "$cell $in $out"
 }
 
-########################################################
-# Read Libraries
-########################################################
-
-foreach lib_file "$sc_libraries $sc_macro_libraries" {
-    yosys read_liberty -setattr liberty_cell -lib $lib_file
-}
-foreach bb_file $sc_blackboxes {
-    yosys log "Reading blackbox model file: $bb_file"
-    yosys read_verilog -setattr blackbox -sv $bb_file
-}
-
 ########################################################
 # Synthesis
 ########################################################
 
-# Before working on the design, we mask out any module supplied via
-# `blackbox_modules`. This allows synthesis of parts of the design without having
-# to modify the input RTL.
-if { [sc_cfg_tool_task_exists var blackbox_modules] } {
-    foreach bb [sc_cfg_tool_task_get var blackbox_modules] {
-        foreach module [get_modules $bb] {
-            yosys log "Blackboxing module: $module"
-            yosys blackbox $module
-        }
-    }
-}
-
 # Although the `synth` command also runs `hierarchy`, we run it here without the
 # `-check` flag first in order to resolve parameters before looking for missing
 # modules. This works around the fact that Surelog doesn't pickle modules that
@@ -290,6 +337,7 @@ if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "
     set sc_hier_threshold \
         [lindex [sc_cfg_tool_task_get var hier_threshold] 0]
 
+    sc_annotate_gate_cost_equivalent
     yosys keep_hierarchy -min_cost $sc_hier_threshold
 
     yosys synth -flatten {*}$synth_args -top $sc_design -run coarse:fine

siliconcompiler/tools/yosys/screenshot.py

@@ -75,7 +75,7 @@ def prepare_asic_libraries(chip):
                     lib_file_name = f'{lib_file_name_base}_{unique_ident}'
                     unique_ident += 1
 
-                lib_content[lib_file_name] = prepareLib.processLibertyFile(
+                lib_content[lib_file_name] = prepareLib.process_liberty_file(
                         lib_file,
                         logger=None if chip.get('option', 'quiet',
                                                 step=step, index=index) else chip.logger)

siliconcompiler/tools/yosys/syn_asic.py

@@ -2,7 +2,7 @@ from siliconcompiler.tools.yosys import synth_post_process, setup as tool_setup
 import os
 import json
 import re
-from siliconcompiler.tools.yosys.prepareLib import processLibertyFile
+from siliconcompiler.tools.yosys.prepareLib import process_liberty_file
 from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
@@ -36,6 +36,8 @@ def setup(chip):
     # Input/output requirements.
     if f'{design}.v' in input_provides(chip, step, index):
         chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    elif f'{design}.sv' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.sv', step=step, index=index)
     else:
         added = False
         added |= add_require_input(chip, 'input', 'rtl', 'systemverilog',
@@ -320,7 +322,7 @@ def prepare_synthesis_libraries(chip):
                     lib_file_name = f'{lib_file_name_base}_{unique_ident}'
                     unique_ident += 1
 
-                lib_content[lib_file_name] = processLibertyFile(
+                lib_content[lib_file_name] = process_liberty_file(
                     lib_file,
                     logger=logger
                 )
@@ -565,8 +567,6 @@ def _generate_cell_area_report(chip):
             area = info["area"]
 
         for cell, inst_count in info["num_cells_by_type"].items():
-            # print(module, cell, inst_count)
-
             cell_area, cell_count = get_area_count(cell)
 
             count += cell_count * inst_count
@@ -583,7 +583,7 @@ def _generate_cell_area_report(chip):
             cell_type = level_info["cells"][cell]["type"]
             if cell_type in modules:
                 area, count = get_area_count(cell_type)
-                cellarea_report.addCell(
+                cellarea_report.add_cell(
                     name=f"{prefix}{cell}",
                     module=cell_type,
                     cellcount=count,
@@ -594,7 +594,7 @@ def _generate_cell_area_report(chip):
     area = 0.0
     if "area" in stat["design"]:
         area = stat["design"]["area"]
-    cellarea_report.addCell(
+    cellarea_report.add_cell(
         name=design,
         module=design,
         cellarea=area,
@@ -604,4 +604,4 @@ def _generate_cell_area_report(chip):
     handle_heir(netlist["modules"][design], "")
 
     if cellarea_report.size() > 0:
-        cellarea_report.writeReport("reports/hierarchical_cell_area.json")
+        cellarea_report.write_report("reports/hierarchical_cell_area.json")

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "e78e29127134a0b95ebcd5661895c6dc4651e641",
+    "git-commit": "b0107893ea0693f3cf09bbf95450a38c1b26b950",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "109bc9ab5e35b830db9569f741db09e468704e6b",
+    "git-commit": "71bdfb99049f33a010bb23527c5c921c925378a0",
     "auto-update": true
   },
   "netgen": {
@@ -41,7 +41,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.30.0",
+    "version": "0.30.1",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -50,7 +50,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "d30c7e7f4e9018b9d4a565207ff752460c81eeb4",
+    "git-commit": "380c2b978a54e459ac216c9e6b7f1a4e31573a0e",
     "auto-update": true
   },
   "verilator": {
@@ -71,7 +71,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
+    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
     "auto-update": false
   },
   "icepack": {
@@ -96,13 +96,15 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.52",
+    "git-commit": "v0.53",
     "version-prefix": "",
     "auto-update": true
   },
   "xyce": {
-    "version": "7.8",
-    "auto-update": false
+    "git-url": "https://github.com/Xyce/Xyce.git",
+    "git-commit": "Release-7.9.0",
+    "version-prefix": "Release-",
+    "auto-update": true
   },
   "xdm": {
     "git-url": "https://github.com/Xyce/XDM.git",
@@ -144,7 +146,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "a95ef24f0307230ae25ea6f2216d2fe8b8ece0be",
+    "git-commit": "34753c07b7bd285b784b3a2c756cfac56e1a26ab",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -156,7 +158,7 @@
   },
   "yosys-parmys": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
+    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
     "docker-depends": [
       "yosys",
       "vpr"

siliconcompiler/toolscripts/rhel8/install-chisel.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum install -y wget
 
 mkdir -p deps
@@ -19,7 +26,7 @@ if [ ! -z ${PREFIX} ]; then
     args="-C $PREFIX --strip-components 1"
 fi
 
-tar xvf sbt.tgz $args
+$SUDO_INSTALL tar xvf sbt.tgz $args
 
 cd -
 

siliconcompiler/toolscripts/rhel8/install-icarus.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum group install -y "Development Tools"
 sudo yum install -y wget git
 
@@ -21,7 +28,7 @@ tar xvf gperf-3.1.tar.gz
 cd gperf-3.1
 ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install
 cd ..
 
 if [ ! -z ${PREFIX} ]; then
@@ -36,6 +43,6 @@ git checkout $(python3 ${src_path}/_tools.py --tool icarus --field git-commit)
 sh autoconf.sh
 ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel8/install-klayout.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum install -y wget
 
 mkdir -p deps

siliconcompiler/toolscripts/rhel8/install-magic.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum group install -y "Development Tools"
 sudo yum install -y tcl-devel tk-devel tcsh csh git
 
@@ -22,4 +29,4 @@ fi
 
 LD_FLAGS=-shared ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel8/install-montage.sh

@@ -1,5 +1,5 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 sudo yum install -y ImageMagick

siliconcompiler/toolscripts/rhel8/install-netgen.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum group install -y "Development Tools"
 sudo yum install -y tcl-devel tk-devel git
 
@@ -22,4 +29,4 @@ fi
 
 ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel8/install-slang.sh

@@ -1,6 +1,6 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
@@ -15,6 +15,13 @@ python3 -m venv .slang --clear
 python3 -m pip install --upgrade pip
 python3 -m pip install cmake
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL="sudo -E PATH=$PATH"
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum install -y gcc-toolset-12
 
 git clone $(python3 ${src_path}/_tools.py --tool slang --field git-url) slang
@@ -23,11 +30,11 @@ git checkout $(python3 ${src_path}/_tools.py --tool slang --field git-commit)
 
 cfg_args=""
 if [ ! -z ${PREFIX} ]; then
-    cfg_args="--prefix=$PREFIX"
+    cfg_args="-D CMAKE_INSTALL_PREFIX=$PREFIX"
 fi
 
-scl run gcc-toolset-12 "cmake -B build"
+scl run gcc-toolset-12 "cmake -B build $cfg_args"
 scl run gcc-toolset-12 "cmake --build build -j$(nproc)"
-scl run gcc-toolset-12 "cmake --install build --strip $cfg_args"
+scl run gcc-toolset-12 "$SUDO_INSTALL make -C build install"
 
 cd -

siliconcompiler/toolscripts/rhel8/install-surelog.sh

@@ -1,6 +1,6 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
@@ -29,6 +29,13 @@ git submodule update --init --recursive
 
 scl run gcc-toolset-12 "LDFLAGS=\"-lrt\" make -j$(nproc)"
 
-sudo -E PATH="$PATH" make install
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL="sudo -E PATH=$PATH"
+else
+    SUDO_INSTALL=""
+fi
+
+$SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel8/install-sv2v.sh

@@ -1,6 +1,6 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
@@ -18,7 +18,14 @@ if [ ! -z ${PREFIX} ]; then
     export PATH="$PREFIX:$PATH"
 fi
 
-curl -sSL https://get.haskellstack.org/ | sh -s - -f $haskell_args
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL="sudo -E PATH=$PATH"
+else
+    SUDO_INSTALL=""
+fi
+
+curl -sSL https://get.haskellstack.org/ | $SUDO_INSTALL sh -s - -f $haskell_args
 
 git clone $(python3 ${src_path}/_tools.py --tool sv2v --field git-url) sv2v
 cd sv2v
@@ -27,8 +34,8 @@ git checkout $(python3 ${src_path}/_tools.py --tool sv2v --field git-commit)
 make -j$(nproc)
 
 if [ ! -z ${PREFIX} ]; then
-    sudo mkdir -p ${PREFIX}/bin/
-    sudo cp bin/* ${PREFIX}/bin/
+    $SUDO_INSTALL mkdir -p ${PREFIX}/bin/
+    $SUDO_INSTALL cp bin/* ${PREFIX}/bin/
 fi
 
 cd -

siliconcompiler/toolscripts/rhel8/install-verible.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum install -y wget
 
 mkdir -p deps
@@ -19,8 +26,9 @@ tar xzf $filename
 
 if [ -z ${PREFIX} ]; then
     PREFIX=/opt/verible
-    sudo mkdir -p $PREFIX
+    SUDO_INSTALL=sudo
+    $SUDO_INSTALL mkdir -p $PREFIX
     echo "Please add \"export PATH="/opt/verible/bin:\$PATH"\" to your .bashrc"
 fi
 
-sudo mv verible-$version/* $PREFIX
+$SUDO_INSTALL mv verible-$version/* $PREFIX

siliconcompiler/toolscripts/rhel8/install-verilator.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum group install -y "Development Tools"
 sudo yum install -y git wget
 
@@ -22,7 +29,7 @@ cd help2man-1.43.3
 
 ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install
 
 cd ..
 
@@ -36,6 +43,6 @@ autoconf
 
 ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install
 
 cd -