siliconcompiler 0.32.3__py3-none-any.whl → 0.33.1__py3-none-any.whl

siliconcompiler/tools/opensta/timing.py

@@ -70,6 +70,17 @@ def setup(chip):
             chip.add('tool', tool, 'task', task, 'require', f'constraint,timing,{scenario},file',
                      step=step, index=index)
 
+    # Add the SPEF or SDF files as inputs if provided.
+    spef_files = [f for f in input_provides(chip, step, index) if f.endswith(".spef")]
+    sdf_files = [f for f in input_provides(chip, step, index) if f.endswith(".sdf")]
+    if spef_files and sdf_files:
+        # If both SPEF and SDF files are provided, only use the SPEF files.
+        chip.add('tool', tool, 'task', task, 'input', spef_files, step=step, index=index)
+    elif spef_files:
+        chip.add('tool', tool, 'task', task, 'input', spef_files, step=step, index=index)
+    elif sdf_files:
+        chip.add('tool', tool, 'task', task, 'input', sdf_files, step=step, index=index)
+
     add_common_file(chip, 'opensta_generic_sdc', 'sdc/sc_constraints.sdc')
 
 

siliconcompiler/tools/slang/__init__.py

@@ -70,38 +70,38 @@ def common_runtime_options(chip):
                                  'param'])
 
     if opts['libext']:
-        options.append(f'--libext {",".join(opts["libext"])}')
+        options.extend(['--libext', f'{",".join(opts["libext"])}'])
 
     #####################
     # Library directories
     #####################
     if opts['ydir']:
-        options.append(f'-y {",".join(opts["ydir"])}')
+        options.extend(['-y', f'{",".join(opts["ydir"])}'])
 
     #####################
     # Library files
     #####################
     if opts['vlib']:
-        options.append(f'-libfile {",".join(opts["vlib"])}')
+        options.extend(['-libfile', f'{",".join(opts["vlib"])}'])
 
     #####################
     # Include paths
     #####################
     if opts['idir']:
-        options.append(f'--include-directory {",".join(opts["idir"])}')
+        options.extend(['--include-directory', f'{",".join(opts["idir"])}'])
 
     #######################
     # Variable Definitions
     #######################
     for value in opts['define']:
-        options.append('-D ' + value)
+        options.extend(['-D', value])
 
     #######################
     # Command files
     #######################
     cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
     if cmdfiles:
-        options.append(f'-F {",".join(cmdfiles)}')
+        options.extend(['-F', f'{",".join(cmdfiles)}'])
 
     #######################
     # Sources
@@ -114,7 +114,7 @@ def common_runtime_options(chip):
     #######################
     # Top Module
     #######################
-    options.append('--top ' + chip.top(step, index))
+    options.extend(['--top', chip.top(step, index)])
 
     ###############################
     # Parameters (top module only)
@@ -122,7 +122,7 @@ def common_runtime_options(chip):
     # Set up user-provided parameters to ensure we elaborate the correct modules
     for param, value in opts['param']:
         value = value.replace('"', '\\"')
-        options.append(f'-G {param}={value}')
+        options.extend(['-G', f'{param}={value}'])
 
     return options
 
@@ -133,11 +133,11 @@ def _get_driver(chip, options_func, ignored_diagnotics=None):
 
     options = options_func(chip)
 
-    parseOpts = pyslang.CommandLineOptions()
-    parseOpts.ignoreProgramName = True
+    parse_options = pyslang.CommandLineOptions()
+    parse_options.ignoreProgramName = True
     opts = " ".join(options)
     code = 0
-    if not driver.parseCommandLine(opts, parseOpts):
+    if not driver.parseCommandLine(opts, parse_options):
         code = 1
 
     if code == 0 and not driver.processOptions():
@@ -211,5 +211,5 @@ def _diagnostics(chip, driver, compilation):
     for diag in compilation.getAllDiagnostics():
         diags.issue(diag)
 
-    record_metric(chip, step, index, 'errors', diags.numErrors, [])
-    record_metric(chip, step, index, 'warnings', diags.numWarnings, [])
+    record_metric(chip, step, index, 'errors', diags.numErrors, [f'sc_{step}{index}.log'])
+    record_metric(chip, step, index, 'warnings', diags.numWarnings, [f'sc_{step}{index}.log'])

siliconcompiler/tools/slang/elaborate.py

@@ -50,16 +50,16 @@ def __get_files(manager, tree):
     nodes = Queue(maxsize=0)
     nodes.put(tree.root)
 
-    def procRange(range):
+    def proc_range(range):
         files.add(manager.getFileName(range.start))
         files.add(manager.getFileName(range.end))
 
     while not nodes.empty():
         node = nodes.get()
-        procRange(node.sourceRange)
+        proc_range(node.sourceRange)
         for token in node:
             if isinstance(token, pyslang.Token):
-                procRange(token.range)
+                proc_range(token.range)
             else:
                 nodes.put(token)
 
@@ -103,7 +103,7 @@ def run(chip):
     add_source = chip.get('tool', tool, 'task', task, 'var', 'include_source_paths',
                           step=step, index=index)[0] == 'true'
 
-    def printFiles(out, files):
+    def print_files(out, files):
         for src_file in files:
             out.write(f'//   File: {src_file}\n')
 
@@ -126,12 +126,12 @@ def run(chip):
 
             out.write("////////////////////////////////////////////////////////////////\n")
             out.write("// Start:\n")
-            printFiles(out, files)
+            print_files(out, files)
 
             out.write(writer.print(tree).str() + '\n')
 
             out.write("// End:\n")
-            printFiles(out, files)
+            print_files(out, files)
             out.write("////////////////////////////////////////////////////////////////\n")
 
     if ok:

siliconcompiler/tools/slang/lint.py

@@ -37,9 +37,7 @@ def run(chip):
 def runtime_options(chip):
     options = slang.common_runtime_options(chip)
     options.extend([
-        "--lint-only",
-        "-Weverything",
-        "-Werror"
+        "-Weverything"
     ])
 
     return options

siliconcompiler/tools/surelog/parse.py

@@ -83,13 +83,13 @@ def runtime_options(chip):
     # Library directories
     #####################
     for value in opts['ydir']:
-        cmdlist.append('-y ' + value)
+        cmdlist.extend(['-y', value])
 
     #####################
     # Library files
     #####################
     for value in opts['vlib']:
-        cmdlist.append('-v ' + value)
+        cmdlist.extend(['-v', value])
 
     #####################
     # Include paths
@@ -107,7 +107,7 @@ def runtime_options(chip):
     # Command files
     #######################
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
-        cmdlist.append('-f ' + value)
+        cmdlist.extend(['-f', + value])
 
     #######################
     # Sources
@@ -120,7 +120,7 @@ def runtime_options(chip):
     #######################
     # Top Module
     #######################
-    cmdlist.append(f'-top {chip.top(step, index)}')
+    cmdlist.extend(['-top', chip.top(step, index)])
 
     ###############################
     # Parameters (top module only)

siliconcompiler/tools/sv2v/convert.py

@@ -23,6 +23,26 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '--numeric-version')
     chip.set('tool', tool, 'version', '>=0.0.9', clobber=False)
 
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'skip_convert']), step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'var', 'skip_convert',
+             'true/false, if true will skip converting system verilog to verilog', field='help')
+    skip = chip.get('tool', tool, 'task', task, 'var', 'skip_convert', step=step, index=index)
+    if skip:
+        skip = skip[0] == "true"
+    else:
+        skip = False
+    chip.set('tool', tool, 'task', task, 'var', 'skip_convert', skip,
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.sv', step=step, index=index)
+
+    if skip:
+        chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.sv', step=step, index=index)
+        return "passing system verilog along"
+
+    chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.v', step=step, index=index)
+
     chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
@@ -41,6 +61,3 @@ def setup(chip):
              step=step, index=index)
     chip.add('tool', tool, 'task', task, 'option', "--write=outputs/" + topmodule + ".v",
              step=step, index=index)
-
-    chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.sv', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.v', step=step, index=index)

siliconcompiler/tools/verilator/compile.py

@@ -161,12 +161,12 @@ def runtime_options(chip):
 
     if c_flags:
         cflags_str = ' '.join(c_flags)
-        cmdlist.extend(['-CFLAGS', f'"{cflags_str}"'])
+        cmdlist.extend(['-CFLAGS', cflags_str])
 
     ld_flags = chip.get('tool', tool, 'task', task, 'var', 'ldflags', step=step, index=index)
     if ld_flags:
         ldflags_str = ' '.join(ld_flags)
-        cmdlist.extend(['-LDFLAGS', f'"{ldflags_str}"'])
+        cmdlist.extend(['-LDFLAGS', ldflags_str])
 
     for value in get_input_files(chip, 'input', 'hll', 'c'):
         cmdlist.append(value)

siliconcompiler/tools/verilator/verilator.py

@@ -144,9 +144,9 @@ def runtime_options(chip):
         cmdlist.append(f'inputs/{design}.v')
     else:
         for value in frontend_opts['ydir']:
-            cmdlist.append(f'-y {value}')
+            cmdlist.extend(['-y', value])
         for value in frontend_opts['vlib']:
-            cmdlist.append(f'-v {value}')
+            cmdlist.extend(['-v', value])
         for value in frontend_opts['idir']:
             cmdlist.append(f'-I{value}')
         for value in frontend_opts['define']:
@@ -160,7 +160,7 @@ def runtime_options(chip):
             cmdlist.append(value)
 
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
-        cmdlist.append(f'-f {value}')
+        cmdlist.extend(['-f', value])
 
     return cmdlist
 

siliconcompiler/tools/vpr/_xml_constraint.py

@@ -1,4 +1,4 @@
-import xml.etree.ElementTree as ET
+from xml.etree import ElementTree
 import xml.dom.minidom
 
 
@@ -10,7 +10,7 @@ def generate_vpr_constraints_xml_file(pin_map, filename):
 
 def generate_vpr_constraints_xml(pin_map):
 
-    constraints_xml = ET.Element("vpr_constraints")
+    constraints_xml = ElementTree.Element("vpr_constraints")
 
     # Generate partition list section
     partition_list = generate_partition_list_xml(pin_map)
@@ -22,7 +22,7 @@ def generate_vpr_constraints_xml(pin_map):
 
 def generate_partition_list_xml(pin_map):
 
-    partition_list = ET.Element("partition_list")
+    partition_list = ElementTree.Element("partition_list")
 
     # ***ASSUMPTION:  pin map is a dictionary of block names
     #                 and tuples, where the tuples specify the
@@ -38,7 +38,7 @@ def generate_partition_list_xml(pin_map):
 
 def generate_partition_xml(pin, pin_region):
 
-    partition = ET.Element("partition")
+    partition = ElementTree.Element("partition")
 
     partition_name = generate_partition_name(pin)
     partition.set("name", partition_name)
@@ -80,7 +80,7 @@ def generate_partition_name(pin):
 
 def generate_add_atom_xml(pin_name):
 
-    atom_xml = ET.Element("add_atom")
+    atom_xml = ElementTree.Element("add_atom")
 
     atom_xml.set("name_pattern", str(pin_name))
 
@@ -89,7 +89,7 @@ def generate_add_atom_xml(pin_name):
 
 def generate_add_region_xml(x_low, x_high, y_low, y_high, subtile):
 
-    region_xml = ET.Element("add_region")
+    region_xml = ElementTree.Element("add_region")
 
     region_xml.set("x_low", str(x_low))
     region_xml.set("y_low", str(y_low))
@@ -100,9 +100,9 @@ def generate_add_region_xml(x_low, x_high, y_low, y_high, subtile):
     return region_xml
 
 
-def write_vpr_constraints_xml_file(constraints: ET.Element, filename: str):
+def write_vpr_constraints_xml_file(constraints: ElementTree.Element, filename: str):
 
-    dom = xml.dom.minidom.parseString(ET.tostring(constraints))
+    dom = xml.dom.minidom.parseString(ElementTree.tostring(constraints))
     xml_string = dom.toprettyxml()
 
     with open(filename, 'w') as xfile:

siliconcompiler/tools/vpr/place.py

@@ -62,7 +62,7 @@ def runtime_options(chip):
         graphics_command_str = " ".join(graphics_commands)
 
         options.append("--graphics_commands")
-        options.append(f"\"{graphics_command_str}\"")
+        options.append(graphics_command_str)
 
     return options
 

siliconcompiler/tools/vpr/route.py

@@ -62,8 +62,8 @@ def runtime_options(chip):
 
     options.append('--route')
     # To run only the routing step we need to pass in the placement files
-    options.append(f'--net_file inputs/{design}.net')
-    options.append(f'--place_file inputs/{design}.place')
+    options.extend(['--net_file', f'inputs/{design}.net'])
+    options.extend(['--place_file', f'inputs/{design}.place'])
 
     enable_images = chip.get('tool', tool, 'task', task, 'var', 'enable_images',
                              step=step, index=index)[0]
@@ -72,7 +72,7 @@ def runtime_options(chip):
                                 step=step, index=index)
 
     if (len(route_iterations) > 0):
-        options.append(f'--max_router_iterations {route_iterations[0]}')
+        options.extend(['--max_router_iterations', route_iterations[0]])
 
     if enable_images == 'true':
         design = chip.top()
@@ -102,7 +102,7 @@ def runtime_options(chip):
         graphics_command_str = " ".join(graphics_commands)
 
         options.append("--graphics_commands")
-        options.append(f"\"{graphics_command_str}\"")
+        options.append(graphics_command_str)
 
     return options
 

siliconcompiler/tools/vpr/screenshot.py

@@ -49,6 +49,6 @@ def runtime_options(chip):
         raise SiliconCompilerError(f"Incorrect file type {show_type}", chip=chip)
 
     options.append("--graphics_commands")
-    options.append(f"\"{screenshot_command_str}\"")
+    options.append(screenshot_command_str)
 
     return options

siliconcompiler/tools/vpr/show.py

@@ -64,14 +64,14 @@ def generic_show_options(chip):
         raise SiliconCompilerError("Blif file does not exist", chip=chip)
 
     if os.path.exists(net_file):
-        options.append(f'--net_file {net_file}')
+        options.extend(['--net_file', net_file])
     else:
         raise SiliconCompilerError("Net file does not exist", chip=chip)
 
     if os.path.exists(route_file) and os.path.exists(place_file):
         options.append('--analysis')
-        options.append(f'--place_file {place_file}')
-        options.append(f'--route_file {route_file}')
+        options.extend(['--place_file', place_file])
+        options.extend(['--route_file', route_file])
     elif os.path.exists(place_file):
         # NOTE: This is a workaround to display the VPR GUI on the output of the place step.
         # VPR GUI can be invoked during the place, route or analysis steps - not after they are run.
@@ -81,8 +81,8 @@ def generic_show_options(chip):
         # the placed design. Setting max_router_iterations to 0 avoids running routing iterations
         # and provides a fast way to invoke VPR GUI on the placed design.
         options.append('--route')
-        options.append('--max_router_iterations 0')
-        options.append(f'--place_file {place_file}')
+        options.extend(['--max_router_iterations', 0])
+        options.extend(['--place_file', place_file])
     else:
         raise SiliconCompilerError("Place file does not exist", chip=chip)
 

siliconcompiler/tools/vpr/vpr.py

@@ -103,15 +103,15 @@ def runtime_options(chip):
 
     device_code = chip.get('fpga', part_name, 'var', 'vpr_device_code')
 
-    options.append(f"--device {device_code[0]}")
+    options.extend(["--device", device_code[0]])
 
     # Medium-term solution:  VPR performs hash digest checks that
     # fail if file paths are changed between steps.  We wish to
     # disable the digest checks to work around this
-    options.append("--verify_file_digests off")
+    options.extend(["--verify_file_digests", "off"])
 
-    options.append(f"--write_block_usage {__block_file}")
-    options.append("--outfile_prefix outputs/")
+    options.extend(["--write_block_usage", __block_file])
+    options.extend(["--outfile_prefix", "outputs/"])
 
     if chip.valid('fpga', part_name, 'file', 'archfile') and \
        chip.get('fpga', part_name, 'file', 'archfile'):
@@ -133,25 +133,25 @@ def runtime_options(chip):
             "Only one architecture XML file can be passed to VPR", chip=chip)
 
     threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
-    options.append(f"--num_workers {threads}")
+    options.extend(["--num_workers", threads])
 
     # For most architectures, constant nets need to be routed
     # like regular nets to be functionally correct (however inefficient
     # that might be...); these two options help control that
-    options.append('--constant_net_method route')
-    options.append('--const_gen_inference none')
+    options.extend(['--constant_net_method', 'route'])
+    options.extend(['--const_gen_inference', 'none'])
 
     # If we allow VPR to sweep dangling primary I/Os and logic blocks
     # it can interfere with circuit debugging; so disable that
-    options.append('--sweep_dangling_primary_ios off')
+    options.extend(['--sweep_dangling_primary_ios', 'off'])
     # If you don't sweep dangling primary I/Os, but sweeping nets
     # VPR can crash:
-    options.append('--sweep_dangling_nets off')
+    options.extend(['--sweep_dangling_nets', 'off'])
     # If you don't sweep dangling nets then the timing engine requires
     # you to set an option allowing dangling nodes
-    options.append('--allow_dangling_combinational_nodes on')
-    options.append('--sweep_constant_primary_outputs off')
-    options.append('--sweep_dangling_blocks off')
+    options.extend(['--allow_dangling_combinational_nodes', 'on'])
+    options.extend(['--sweep_constant_primary_outputs', 'off'])
+    options.extend(['--sweep_dangling_blocks', 'off'])
 
     # Explicitly specify the clock modeling type in the part driver
     # to avoid ambiguity and future-proof against new VPR clock models
@@ -163,11 +163,11 @@ def runtime_options(chip):
         # When dedicated networks are used, tell VPR to use the two-stage router,
         # otherwise not.
         if (selected_clock_model == 'ideal'):
-            options.append(f'--clock_modeling {selected_clock_model}')
+            options.extend(['--clock_modeling', selected_clock_model])
         elif (selected_clock_model == 'route'):
-            options.append(f'--clock_modeling {selected_clock_model}')
+            options.extend(['--clock_modeling', selected_clock_model])
         elif (selected_clock_model == 'dedicated_network'):
-            options.append(f'--clock_modeling {selected_clock_model}')
+            options.extend(['--clock_modeling', selected_clock_model])
             options.append('--two_stage_clock_routing')
         else:
             raise SiliconCompilerError(
@@ -181,24 +181,24 @@ def runtime_options(chip):
                                     file_not_found_msg="SDC file not found")
 
     if sdc_file:
-        sdc_arg = f"--sdc_file {sdc_file}"
-        options.append(sdc_arg)
+        options.append("--sdc_file")
+        options.append(sdc_file)
 
         report_type = chip.get('tool', tool, 'task', task, 'var', 'timing_report_type',
                                step=step, index=index)[0]
-        options.append(f'--timing_report_detail {report_type}')
+        options.extend(['--timing_report_detail', report_type])
         report_paths = chip.get('tool', tool, 'task', task, 'var', 'timing_paths',
                                 step=step, index=index)[0]
-        options.append(f'--timing_report_npaths {report_paths}')
+        options.extend(['--timing_report_npaths', report_paths])
     else:
-        options.append("--timing_analysis off")
+        options.extend(["--timing_analysis", "off"])
 
     # Per the scheme implemented in the placement pre-process step,
     # if a constraints file exists it will always be in the auto_constraints()
     # location:
     if (os.path.isfile(auto_constraints())):
-        pin_constraint_arg = f"--read_vpr_constraints {auto_constraints()}"
-        options.append(pin_constraint_arg)
+        options.append("--read_vpr_constraints")
+        options.append(auto_constraints())
 
     # Routing graph XML:
     rr_graph = find_single_file(chip, 'fpga', part_name, 'file', 'graphfile',
@@ -208,7 +208,7 @@ def runtime_options(chip):
         chip.logger.info("No VPR RR graph file specified")
         chip.logger.info("Routing architecture will come from architecture XML file")
     else:
-        options.append("--read_rr_graph " + rr_graph)
+        options.extend(["--read_rr_graph", rr_graph])
 
     # ***NOTE: For real FPGA chips you need to specify the routing channel
     #          width explicitly.  VPR requires an explicit routing channel
@@ -222,7 +222,7 @@ def runtime_options(chip):
     if (len(num_routing_channels) == 0):
         raise SiliconCompilerError("Number of routing channels not specified", chip=chip)
     elif (len(num_routing_channels) == 1):
-        options.append("--route_chan_width " + num_routing_channels[0])
+        options.extend(["--route_chan_width", num_routing_channels[0]])
     elif (len(num_routing_channels) > 1):
         raise SiliconCompilerError(
             "Only one routing channel width argument can be passed to VPR", chip=chip)

siliconcompiler/tools/xdm/convert.py

@@ -24,9 +24,9 @@ def setup(chip):
 
     chip.add('tool', tool, 'task', task, 'option', '--auto',
              step=step, index=index)
-    chip.add('tool', tool, 'task', task, 'option', '--source_file_format hspice',
+    chip.add('tool', tool, 'task', task, 'option', ['--source_file_format', 'hspice'],
              step=step, index=index)
-    chip.add('tool', tool, 'task', task, 'option', f'--dir_out outputs/{design}.xyce',
+    chip.add('tool', tool, 'task', task, 'option', ['--dir_out', f'outputs/{design}.xyce'],
              step=step, index=index)
 
     chip.set('tool', 'xdm', 'task', 'convert', 'var', 'rename', 'true',

siliconcompiler/tools/xyce/simulate.py

@@ -48,7 +48,7 @@ def setup(chip):
                 step=step, index=index) == ['true']:
         chip.add('tool', tool, 'task', task, 'output', f'{design}.raw',
                  step=step, index=index)
-        chip.add('tool', tool, 'task', task, 'option', f'-r outputs/{design}.raw',
+        chip.add('tool', tool, 'task', task, 'option', ['-r', f'outputs/{design}.raw'],
                  step=step, index=index)
 
 

siliconcompiler/tools/yosys/prepareLib.py

@@ -6,7 +6,7 @@ import gzip
 import argparse  # argument parsing
 
 
-def processLibertyFile(input_file, logger=None):
+def process_liberty_file(input_file, logger=None):
     # Read input file
     if logger:
         logger.info(f"Opening file for replace: {input_file}")
@@ -56,4 +56,4 @@ if __name__ == "__main__":
                         help='Output File')
     args = parser.parse_args()
 
-    processLibertyFile(args.inputFile, args.outputFile, args.patterns)
+    process_liberty_file(args.inputFile, args.outputFile, args.patterns)