siliconcompiler 0.32.3__py3-none-any.whl → 0.33.1__py3-none-any.whl

siliconcompiler/tools/_common/__init__.py

@@ -465,16 +465,12 @@ def record_metric(chip, step, index, metric, value, source, source_unit=None):
         Records the metric cell area under 'floorplan0' and notes the source as
         'reports/metrics.json'
     '''
-    from siliconcompiler import units
-
-    metric_unit = None
-    if chip.schema.has_field('metric', metric, 'unit'):
-        metric_unit = chip.get('metric', metric, field='unit')
-
-    if metric_unit:
-        value = units.convert(value, from_unit=source_unit, to_unit=metric_unit)
-
-    chip.set('metric', metric, value, step=step, index=index)
+    chip.get("metric", field="schema").record(
+        step, index,
+        metric,
+        value,
+        unit=source_unit
+    )
 
     if source:
         flow = chip.get('option', 'flow')

siliconcompiler/tools/_common/asic.py

@@ -257,10 +257,10 @@ class CellArea:
     def __init__(self):
         self.__areas = {}
 
-    def addCell(self, name=None, module=None,
-                cellarea=None, cellcount=None,
-                macroarea=None, macrocount=None,
-                stdcellarea=None, stdcellcount=None):
+    def add_cell(self, name=None, module=None,
+                 cellarea=None, cellcount=None,
+                 macroarea=None, macrocount=None,
+                 stdcellarea=None, stdcellcount=None):
         if not name and not module:
             return
 
@@ -294,6 +294,6 @@ class CellArea:
     def size(self):
         return len(self.__areas)
 
-    def writeReport(self, path):
+    def write_report(self, path):
         with open(path, 'w') as f:
             json.dump(self.__areas, f, indent=4)

siliconcompiler/tools/_common/sdc/sc_constraints.sdc

@@ -1,6 +1,6 @@
 # Default constraints file that sets up clocks based on definitions in schema.
 
-source sc_manifest.tcl > /dev/null
+source sc_manifest.tcl
 
 ### Create clocks
 if { [sc_cfg_exists datasheet pin] } {

siliconcompiler/tools/bluespec/convert.py

@@ -70,24 +70,24 @@ def runtime_options(chip):
     opts = get_frontend_options(chip, ['idir', 'ydir', 'define'])
 
     cmdlist.append('-verilog')
-    cmdlist.append(f'-vdir {VLOG_DIR}')
-    cmdlist.append(f'-bdir {BSC_DIR}')
-    cmdlist.append('-info-dir reports')
+    cmdlist.extend(['-vdir', VLOG_DIR])
+    cmdlist.extend(['-bdir', BSC_DIR])
+    cmdlist.extend(['-info-dir', 'reports'])
     cmdlist.append('-u')
     cmdlist.append('-v')
 
     cmdlist.append('-show-module-use')
     cmdlist.append('-sched-dot')
 
-    cmdlist.append(f'-g {chip.top(step, index)}')
+    cmdlist.extend(['-g', chip.top(step, index)])
 
     bsc_path = ':'.join(opts['ydir'] + ['%/Libraries'])
-    cmdlist.append('-p ' + bsc_path)
+    cmdlist.extend(['-p', bsc_path])
 
     for value in opts['idir']:
-        cmdlist.append('-I ' + value)
+        cmdlist.extend(['-I', value])
     for value in opts['define']:
-        cmdlist.append('-D ' + value)
+        cmdlist.extend(['-D', value])
 
     sources = get_input_files(chip, 'input', 'hll', 'bsv', add_library_files=False)
     if len(sources) != 1:
@@ -125,7 +125,8 @@ def post_process(chip):
                 if os.path.exists(mod_path):
                     extra_modules.add(mod_path)
                 else:
-                    chip.logger.warn(f"Unable to find module {module} source files at: {BSC_LIB}")
+                    chip.logger.warning(f"Unable to find module {module} source "
+                                        f"files at: {BSC_LIB}")
 
     # bsc outputs each compiled module to its own Verilog file, so we
     # concatenate them all to create a pickled output we can pass along.

siliconcompiler/tools/builtin/_common.py

@@ -3,7 +3,7 @@ from siliconcompiler import NodeStatus, SiliconCompilerError
 from siliconcompiler import utils
 import shutil
 from siliconcompiler.tools._common import get_tool_task
-from siliconcompiler.flowgraph import _get_pruned_node_inputs
+from siliconcompiler.flowgraph import RuntimeFlowgraph
 
 
 ###########################################################################
@@ -152,4 +152,11 @@ def _select_inputs(chip, step, index):
     chip.logger.info(f"Running builtin task '{task}'")
 
     flow = chip.get('option', 'flow')
-    return _get_pruned_node_inputs(chip, flow, (step, index))
+
+    flow_schema = chip.schema.get("flowgraph", flow, field="schema")
+    runtime = RuntimeFlowgraph(
+        flow_schema,
+        from_steps=set([step for step, _ in flow_schema.get_entry_nodes()]),
+        prune_nodes=chip.get('option', 'prune'))
+
+    return runtime.get_node_inputs(step, index, record=chip.schema.get("record", field="schema"))

siliconcompiler/tools/builtin/concatenate.py

@@ -3,7 +3,6 @@ import os
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
-from siliconcompiler import flowgraph
 from siliconcompiler import scheduler
 
 
@@ -12,7 +11,7 @@ def make_docs(chip):
     _make_docs(chip)
     chip.set('option', 'flow', 'asicflow')
 
-    for step, index in flowgraph._get_flowgraph_entry_nodes(chip, 'asicflow'):
+    for step, index in chip.schema.get("flowgraph", "asicflow", field="schema").get_entry_nodes():
         scheduler._setup_node(chip, step, index)
 
     chip.set('arg', 'step', 'import.combine')
@@ -63,7 +62,12 @@ def _gather_outputs(chip, step, index):
     flow = chip.get('option', 'flow')
 
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
-    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+    in_task_outputs = []
+    for in_step, in_index in in_nodes:
+        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, field="schema")
+        task_class.set_runtime(chip, step=in_step, index=in_index)
+        in_task_outputs.append(task_class.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].union(*in_task_outputs[1:])

siliconcompiler/tools/builtin/minimum.py

@@ -1,6 +1,6 @@
 from siliconcompiler.tools.builtin import _common
-from siliconcompiler import flowgraph
 from siliconcompiler.tools.builtin.builtin import set_io_files
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
@@ -41,7 +41,12 @@ def _gather_outputs(chip, step, index):
     flow = chip.get('option', 'flow')
 
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
-    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+    in_task_outputs = []
+    for in_step, in_index in in_nodes:
+        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, field="schema")
+        task_class.set_runtime(chip, step=in_step, index=in_index)
+        in_task_outputs.append(task_class.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].intersection(*in_task_outputs[1:])

siliconcompiler/tools/builtin/mux.py

@@ -1,7 +1,8 @@
 from siliconcompiler.tools.builtin import _common
 import re
 from siliconcompiler.tools.builtin.builtin import set_io_files
-from siliconcompiler import flowgraph, SiliconCompilerError
+from siliconcompiler import SiliconCompilerError
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
@@ -54,7 +55,12 @@ def _gather_outputs(chip, step, index):
     flow = chip.get('option', 'flow')
 
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
-    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+    in_task_outputs = []
+    for in_step, in_index in in_nodes:
+        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, field="schema")
+        task_class.set_runtime(chip, step=in_step, index=in_index)
+        in_task_outputs.append(task_class.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].intersection(*in_task_outputs[1:])

siliconcompiler/tools/builtin/nop.py

@@ -1,6 +1,6 @@
 from siliconcompiler.tools.builtin import _common
 from siliconcompiler.tools.builtin.builtin import set_io_files
-from siliconcompiler import flowgraph
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
@@ -22,7 +22,12 @@ def _gather_outputs(chip, step, index):
     flow = chip.get('option', 'flow')
 
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
-    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+    in_task_outputs = []
+    for in_step, in_index in in_nodes:
+        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, field="schema")
+        task_class.set_runtime(chip, step=in_step, index=in_index)
+        in_task_outputs.append(task_class.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].union(*in_task_outputs[1:])

siliconcompiler/tools/builtin/verify.py

@@ -1,8 +1,9 @@
 from siliconcompiler.tools.builtin import _common
-from siliconcompiler.schema import Schema
+from siliconcompiler.schema.parametertype import NodeType
 from siliconcompiler.scheduler import _haltstep
 from siliconcompiler.tools.builtin.builtin import set_io_files
-from siliconcompiler import utils, flowgraph, SiliconCompilerError
+from siliconcompiler import utils, SiliconCompilerError
+from siliconcompiler.tools._common import get_tool_task
 
 import re
 
@@ -52,8 +53,8 @@ def _select_inputs(chip, step, index):
             raise SiliconCompilerError(
                 f"Missing metric for {metric} in {inputs[0]}{inputs[1]}", chip=chip)
 
-        metric_type = chip.get('metric', metric, field='type')
-        goal = Schema._normalize_value(goal, metric_type, "", None)
+        metric_type = chip.get('metric', metric, field=None)
+        goal = NodeType.normalize(goal, metric_type.get(field='type'))
         if not utils.safecompare(chip, value, op, goal):
             chip.error(f"{step}{index} fails '{metric}' metric: {value}{op}{goal}")
 
@@ -67,7 +68,12 @@ def _gather_outputs(chip, step, index):
     flow = chip.get('option', 'flow')
 
     in_nodes = chip.get('flowgraph', flow, step, index, 'input')
-    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+    in_task_outputs = []
+    for in_step, in_index in in_nodes:
+        in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
+        task_class = chip.get("tool", in_tool, field="schema")
+        task_class.set_runtime(chip, step=in_step, index=in_index)
+        in_task_outputs.append(task_class.get_output_files())
 
     if len(in_task_outputs) > 0:
         return in_task_outputs[0].intersection(*in_task_outputs[1:])

siliconcompiler/tools/chisel/convert.py

@@ -103,7 +103,7 @@ def runtime_options(chip):
 
     design = chip.top()
 
-    runMain = ["runMain"]
+    run_main = ["runMain"]
     if chip.valid('input', 'config', 'chisel') and \
        chip.get('input', 'config', 'chisel', step=step, index=index):
         app = design
@@ -112,23 +112,23 @@ def runtime_options(chip):
             app = chip.get('tool', tool, 'task', task, 'var', 'application',
                            step=step, index=index)[0]
 
-        runMain.append(f"{app}")
+        run_main.append(f"{app}")
 
         if chip.valid('tool', tool, 'task', task, 'var', 'argument') and \
            chip.get('tool', tool, 'task', task, 'var', 'argument', step=step, index=index):
-            runMain.extend(chip.get('tool', tool, 'task', task, 'var', 'argument',
-                                    step=step, index=index))
-        runMain.append("--")
+            run_main.extend(chip.get('tool', tool, 'task', task, 'var', 'argument',
+                                     step=step, index=index))
+        run_main.append("--")
 
-        runMain.append("--target-dir chisel-output")
+        run_main.extend(["--target-dir", "chisel-output"])
     else:
         # Use built in driver
-        runMain.append("SCDriver")
-        runMain.append(f"--module {chip.top(step=step, index=index)}")
+        run_main.append("SCDriver")
+        run_main.extend(["--module", chip.top(step=step, index=index)])
 
-        runMain.append(f"--output-file ../outputs/{design}.v")
+        run_main.extend(["--output-file", f"../outputs/{design}.v"])
 
-    return [f'"{" ".join(runMain)}"']
+    return [" ".join(run_main)]
 
 
 def post_process(chip):

siliconcompiler/tools/genfasm/bitstream.py

@@ -41,9 +41,9 @@ def runtime_options(chip):
     blif = f"inputs/{design}.blif"
     options.append(blif)
 
-    options.append(f'--net_file inputs/{design}.net')
-    options.append(f'--place_file inputs/{design}.place')
-    options.append(f'--route_file inputs/{design}.route')
+    options.extend(['--net_file', f'inputs/{design}.net'])
+    options.extend(['--place_file', f'inputs/{design}.place'])
+    options.extend(['--route_file', f'inputs/{design}.route'])
 
     return options
 

siliconcompiler/tools/ghdl/convert.py

@@ -25,7 +25,7 @@ def setup(chip):
 
     chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
-    chip.set('tool', tool, 'task', task, 'option', '',
+    chip.set('tool', tool, 'task', task, 'option', [],
              step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'output',
              step=step, index=index)

siliconcompiler/tools/icarus/compile.py

@@ -68,19 +68,19 @@ def runtime_options(chip):
 
     # source files
     for value in opts['ydir']:
-        cmdlist.append('-y ' + value)
+        cmdlist.extend(['-y', value])
     for value in opts['vlib']:
-        cmdlist.append('-v ' + value)
+        cmdlist.extend(['-v', value])
     for value in opts['idir']:
         cmdlist.append('-I' + value)
     for value in opts['define']:
         cmdlist.append('-D' + value)
 
     # add siliconcompiler specific defines
-    cmdlist.append(f"-DSILICONCOMPILER_TRACE_FILE=\\\"reports/{design}.vcd\\\"")
+    cmdlist.append(f"-DSILICONCOMPILER_TRACE_FILE=\"reports/{design}.vcd\"")
 
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
-        cmdlist.append('-f ' + value)
+        cmdlist.extend(['-f', value])
     for value in get_input_files(chip, 'input', 'rtl', 'netlist'):
         cmdlist.append(value)
     for value in get_input_files(chip, 'input', 'rtl', 'verilog'):

siliconcompiler/tools/icepack/bitstream.py

@@ -1,4 +1,5 @@
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.icepack.icepack import runtime_options as tool_runtime_options
 
 
 def setup(chip):
@@ -15,6 +16,10 @@ def setup(chip):
 
     chip.set('tool', tool, 'exe', tool)
 
-    chip.set('tool', tool, 'task', task, 'option', "", step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', [], step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'input', f'{design}.asc', step=step, index=index)
     chip.set('tool', tool, 'task', task, 'output', f'{design}.bit', step=step, index=index)
+
+
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/klayout/convert_drc_db.py

@@ -1,6 +1,7 @@
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
 
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools.klayout.klayout import runtime_options as tool_runtime_options
 
 
 def make_docs(chip):
@@ -58,3 +59,7 @@ def setup(chip):
 
     chip.set('tool', tool, 'task', task, 'output', f'{design}.json',
              step=step, index=index)
+
+
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/klayout/drc.py

@@ -6,7 +6,7 @@ from siliconcompiler.tools._common import input_provides, has_input_files, \
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_tool_task_var
 
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
-import xml.etree.ElementTree as ET
+from xml.etree import ElementTree
 from siliconcompiler import utils
 
 
@@ -144,7 +144,7 @@ def post_process(chip):
     drc_report = None
     if os.path.isfile(drc_db):
         with open(drc_db, "r") as f:
-            drc_report = ET.fromstring(f.read())
+            drc_report = ElementTree.fromstring(f.read())
     if drc_report is None:
         drc_db = []
 

siliconcompiler/tools/klayout/klayout_export.py

@@ -121,7 +121,6 @@ def main():
     # SC_ROOT provided by CLI
     sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
     sys.path.append(SC_TOOLS_ROOT)  # noqa: F821
-    print(sys.path)
 
     from klayout_utils import (
         technology,

siliconcompiler/tools/klayout/klayout_show.py

@@ -17,18 +17,18 @@ def show(schema, tech, input_path, output_path, screenshot=False, report=None):
         sc_hide_layers = []
 
     # Load KLayout technology file
-    layoutOptions = tech.load_layout_options
+    layout_options = tech.load_layout_options
 
     # These may be disabled in our KLayout tech file for reasons relating to GDS
     # export, but for the purposes of viewing we'll hardcode them to True.
-    layoutOptions.lefdef_config.produce_blockages = True
-    layoutOptions.lefdef_config.produce_cell_outlines = True
-    layoutOptions.lefdef_config.produce_obstructions = True
+    layout_options.lefdef_config.produce_blockages = True
+    layout_options.lefdef_config.produce_cell_outlines = True
+    layout_options.lefdef_config.produce_obstructions = True
 
     # Always use LEF geometry even when LEF file contains FOREIGN statement.
-    layoutOptions.lefdef_config.macro_resolution_mode = 1
+    layout_options.lefdef_config.macro_resolution_mode = 1
 
-    tech.load_layout_options = layoutOptions
+    tech.load_layout_options = layout_options
 
     app = pya.Application.instance()
     main_window = pya.MainWindow.instance()

siliconcompiler/tools/klayout/klayout_utils.py

@@ -1,5 +1,4 @@
 import pya
-import importlib.util as importlib_util
 import json
 import os
 import shutil
@@ -85,12 +84,12 @@ def technology(design, schema):
         lefs.extend(schema.get('library', lib, 'output', sc_stackup, 'lef',
                                step=sc_step, index=sc_index))
 
-    layoutOptions = tech.load_layout_options
+    layout_options = tech.load_layout_options
 
-    layoutOptions.lefdef_config.macro_resolution_mode = 1
-    layoutOptions.lefdef_config.via_cellname_prefix = "VIA_"
+    layout_options.lefdef_config.macro_resolution_mode = 1
+    layout_options.lefdef_config.via_cellname_prefix = "VIA_"
     pathed_files = set()
-    for lef_file in layoutOptions.lefdef_config.lef_files:
+    for lef_file in layout_options.lefdef_config.lef_files:
         if foundry_lef and not os.path.isabs(lef_file):
             lef_file = os.path.join(os.path.dirname(foundry_lef), lef_file)
         lef_file = os.path.abspath(lef_file)
@@ -100,13 +99,13 @@ def technology(design, schema):
     for lef in lefs:
         pathed_files.add(os.path.abspath(lef))
 
-    layoutOptions.lefdef_config.lef_files = list(pathed_files)
-    layoutOptions.lefdef_config.read_lef_with_def = False
-    layoutOptions.lefdef_config.dbu = tech.dbu
+    layout_options.lefdef_config.lef_files = list(pathed_files)
+    layout_options.lefdef_config.read_lef_with_def = False
+    layout_options.lefdef_config.dbu = tech.dbu
 
-    layoutOptions.lefdef_config.produce_fills = True
+    layout_options.lefdef_config.produce_fills = True
 
-    for lef_file in layoutOptions.lefdef_config.lef_files:
+    for lef_file in layout_options.lefdef_config.lef_files:
         print(f"[INFO] LEF file: {lef_file}")
 
     # Set layer properties
@@ -128,7 +127,7 @@ def technology(design, schema):
         print(f"[INFO] Layer properties: {layer_properties}")
 
     # Set layer map
-    map_file = layoutOptions.lefdef_config.map_file
+    map_file = layout_options.lefdef_config.map_file
     if map_file:
         map_file = map_file[0]
         if not os.path.isabs(map_file):
@@ -142,10 +141,10 @@ def technology(design, schema):
                 break
 
     if map_file and os.path.exists(map_file):
-        layoutOptions.lefdef_config.map_file = map_file
+        layout_options.lefdef_config.map_file = map_file
         print(f"[INFO] Layer map: {map_file}")
 
-    tech.load_layout_options = layoutOptions
+    tech.load_layout_options = layout_options
 
     return tech
 
@@ -172,15 +171,9 @@ def get_write_options(filename, timestamps):
 
 
 def get_schema(manifest):
-    scroot = os.path.join(os.path.dirname(__file__), '..', '..')
-    module_name = 'schema'
-    schema_base = os.path.join(scroot, module_name, '__init__.py')
-    spec = importlib_util.spec_from_file_location(module_name, schema_base)
-    module = importlib_util.module_from_spec(spec)
-    sys.modules[module_name] = module
-    spec.loader.exec_module(module)
-    # Return schema
-    return module.Schema(manifest=manifest)
+    sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..'))
+    from schema.safeschema import SafeSchema
+    return SafeSchema.from_manifest(filepath=manifest)
 
 
 def generate_metrics():

siliconcompiler/tools/netgen/count_lvs.py

@@ -34,7 +34,7 @@ import argparse
 from siliconcompiler import sc_open
 
 
-def count_LVS_failures(filename):
+def count_lvs_failures(filename):
     with sc_open(filename) as cfile:
         lvsdata = json.load(cfile)
 
@@ -114,7 +114,7 @@ if __name__ == '__main__':
     parser = argparse.ArgumentParser(description='Parses netgen lvs')
     parser.add_argument('--file', '-f', required=True)
     args = parser.parse_args()
-    failures = count_LVS_failures(args.file)
+    failures = count_lvs_failures(args.file)
     total = failures[0]
     if total > 0:
         failed = True

siliconcompiler/tools/netgen/lvs.py

@@ -79,7 +79,7 @@ def post_process(chip):
         chip.logger.warning('No LVS report generated. Netgen may have encountered errors.')
         return
 
-    lvs_failures = count_lvs.count_LVS_failures(lvs_report)
+    lvs_failures = count_lvs.count_lvs_failures(lvs_report)
 
     # We don't count top-level pin mismatches as errors b/c we seem to get
     # false positives for disconnected pins. Report them as warnings

siliconcompiler/tools/nextpnr/apr.py

@@ -1,4 +1,5 @@
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.nextpnr.nextpnr import runtime_options as tool_runtime_options
 
 
 def setup(chip):
@@ -18,7 +19,11 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '--version')
     chip.set('tool', tool, 'version', '>=0.2', clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'option', "", step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', [], step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.netlist.json',
              step=step, index=index)
     chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.asc', step=step, index=index)
+
+
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/nextpnr/nextpnr.py

@@ -33,14 +33,14 @@ def runtime_options(chip):
 
     options = []
 
-    options.append('--json inputs/' + topmodule + '.netlist.json')
-    options.append('--asc outputs/' + topmodule + '.asc')
+    options.extend(['--json', 'inputs/' + topmodule + '.netlist.json'])
+    options.extend(['--asc', 'outputs/' + topmodule + '.asc'])
 
     if partname == 'ice40up5k-sg48':
-        options.append('--up5k --package sg48')
+        options.extend(['--up5k', '--package', 'sg48'])
 
     for constraint_file in chip.find_files('input', 'constraint', 'pcf', step=step, index=index):
-        options.append('--pcf ' + constraint_file)
+        options.extend(['--pcf', constraint_file])
 
     return options
 

siliconcompiler/tools/openroad/_apr.py

@@ -402,7 +402,7 @@ def _generate_cell_area_report(design, ord_metrics):
         if stdcell_info_area:
             stdcellarea = sum(stdcell_info_area)
 
-        cellarea_report.addCell(
+        cellarea_report.add_cell(
             name=cell_name,
             module=cell_type,
             cellarea=cellarea,
@@ -420,7 +420,7 @@ def _generate_cell_area_report(design, ord_metrics):
         process_cell(module)
 
     if cellarea_report.size() > 0:
-        cellarea_report.writeReport("reports/hierarchical_cell_area.json")
+        cellarea_report.write_report("reports/hierarchical_cell_area.json")
 
 
 def define_tapcell_params(chip):
@@ -801,6 +801,14 @@ def define_sta_params(chip):
     set_tool_task_var(chip, param_key='sta_top_n_paths',
                       default_value='10',
                       schelp='number of paths to report timing for')
+    set_tool_task_var(chip, param_key='sta_define_path_groups',
+                      default_value=True,
+                      skip=['pdk', 'lib'],
+                      schelp='true/false, if true will generate path groups for timing reporting')
+    set_tool_task_var(chip, param_key='sta_unique_path_groups_per_clock',
+                      default_value=False,
+                      skip=['pdk', 'lib'],
+                      schelp='true/false, if true will generate separate path groups per clock')
 
     chip.set('tool', tool, 'task', task, 'var', 'power_corner', get_power_corner(chip),
              step=step, index=index, clobber=False)
@@ -1044,6 +1052,8 @@ def set_pnr_inputs(chip):
 
     design = chip.top()
 
+    # clear
+    chip.set('tool', tool, 'task', task, 'input', [], step=step, index=index)
     if f'{design}.sdc' in input_provides(chip, step, index):
         chip.add('tool', tool, 'task', task, 'input', design + '.sdc',
                  step=step, index=index)
@@ -1071,6 +1081,9 @@ def set_pnr_outputs(chip):
 
     design = chip.top()
 
+    # clear
+    chip.set('tool', tool, 'task', task, 'output', [], step=step, index=index)
+
     chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)