siliconcompiler 0.32.3__py3-none-any.whl → 0.33.0__py3-none-any.whl

siliconcompiler/tools/vpr/vpr.py

@@ -103,15 +103,15 @@ def runtime_options(chip):
 
     device_code = chip.get('fpga', part_name, 'var', 'vpr_device_code')
 
-    options.append(f"--device {device_code[0]}")
+    options.extend(["--device", device_code[0]])
 
     # Medium-term solution:  VPR performs hash digest checks that
     # fail if file paths are changed between steps.  We wish to
     # disable the digest checks to work around this
-    options.append("--verify_file_digests off")
+    options.extend(["--verify_file_digests", "off"])
 
-    options.append(f"--write_block_usage {__block_file}")
-    options.append("--outfile_prefix outputs/")
+    options.extend(["--write_block_usage", __block_file])
+    options.extend(["--outfile_prefix", "outputs/"])
 
     if chip.valid('fpga', part_name, 'file', 'archfile') and \
        chip.get('fpga', part_name, 'file', 'archfile'):
@@ -133,25 +133,25 @@ def runtime_options(chip):
             "Only one architecture XML file can be passed to VPR", chip=chip)
 
     threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
-    options.append(f"--num_workers {threads}")
+    options.extend(["--num_workers", threads])
 
     # For most architectures, constant nets need to be routed
     # like regular nets to be functionally correct (however inefficient
     # that might be...); these two options help control that
-    options.append('--constant_net_method route')
-    options.append('--const_gen_inference none')
+    options.extend(['--constant_net_method', 'route'])
+    options.extend(['--const_gen_inference', 'none'])
 
     # If we allow VPR to sweep dangling primary I/Os and logic blocks
     # it can interfere with circuit debugging; so disable that
-    options.append('--sweep_dangling_primary_ios off')
+    options.extend(['--sweep_dangling_primary_ios', 'off'])
     # If you don't sweep dangling primary I/Os, but sweeping nets
     # VPR can crash:
-    options.append('--sweep_dangling_nets off')
+    options.extend(['--sweep_dangling_nets', 'off'])
     # If you don't sweep dangling nets then the timing engine requires
     # you to set an option allowing dangling nodes
-    options.append('--allow_dangling_combinational_nodes on')
-    options.append('--sweep_constant_primary_outputs off')
-    options.append('--sweep_dangling_blocks off')
+    options.extend(['--allow_dangling_combinational_nodes', 'on'])
+    options.extend(['--sweep_constant_primary_outputs', 'off'])
+    options.extend(['--sweep_dangling_blocks', 'off'])
 
     # Explicitly specify the clock modeling type in the part driver
     # to avoid ambiguity and future-proof against new VPR clock models
@@ -163,11 +163,11 @@ def runtime_options(chip):
         # When dedicated networks are used, tell VPR to use the two-stage router,
         # otherwise not.
         if (selected_clock_model == 'ideal'):
-            options.append(f'--clock_modeling {selected_clock_model}')
+            options.extend(['--clock_modeling', selected_clock_model])
         elif (selected_clock_model == 'route'):
-            options.append(f'--clock_modeling {selected_clock_model}')
+            options.extend(['--clock_modeling', selected_clock_model])
         elif (selected_clock_model == 'dedicated_network'):
-            options.append(f'--clock_modeling {selected_clock_model}')
+            options.extend(['--clock_modeling', selected_clock_model])
             options.append('--two_stage_clock_routing')
         else:
             raise SiliconCompilerError(
@@ -181,24 +181,24 @@ def runtime_options(chip):
                                     file_not_found_msg="SDC file not found")
 
     if sdc_file:
-        sdc_arg = f"--sdc_file {sdc_file}"
-        options.append(sdc_arg)
+        options.append("--sdc_file")
+        options.append(sdc_file)
 
         report_type = chip.get('tool', tool, 'task', task, 'var', 'timing_report_type',
                                step=step, index=index)[0]
-        options.append(f'--timing_report_detail {report_type}')
+        options.extend(['--timing_report_detail', report_type])
         report_paths = chip.get('tool', tool, 'task', task, 'var', 'timing_paths',
                                 step=step, index=index)[0]
-        options.append(f'--timing_report_npaths {report_paths}')
+        options.extend(['--timing_report_npaths', report_paths])
     else:
-        options.append("--timing_analysis off")
+        options.extend(["--timing_analysis", "off"])
 
     # Per the scheme implemented in the placement pre-process step,
     # if a constraints file exists it will always be in the auto_constraints()
     # location:
     if (os.path.isfile(auto_constraints())):
-        pin_constraint_arg = f"--read_vpr_constraints {auto_constraints()}"
-        options.append(pin_constraint_arg)
+        options.append("--read_vpr_constraints")
+        options.append(auto_constraints())
 
     # Routing graph XML:
     rr_graph = find_single_file(chip, 'fpga', part_name, 'file', 'graphfile',
@@ -208,7 +208,7 @@ def runtime_options(chip):
         chip.logger.info("No VPR RR graph file specified")
         chip.logger.info("Routing architecture will come from architecture XML file")
     else:
-        options.append("--read_rr_graph " + rr_graph)
+        options.extend(["--read_rr_graph", rr_graph])
 
     # ***NOTE: For real FPGA chips you need to specify the routing channel
     #          width explicitly.  VPR requires an explicit routing channel
@@ -222,7 +222,7 @@ def runtime_options(chip):
     if (len(num_routing_channels) == 0):
         raise SiliconCompilerError("Number of routing channels not specified", chip=chip)
     elif (len(num_routing_channels) == 1):
-        options.append("--route_chan_width " + num_routing_channels[0])
+        options.extend(["--route_chan_width", num_routing_channels[0]])
     elif (len(num_routing_channels) > 1):
         raise SiliconCompilerError(
             "Only one routing channel width argument can be passed to VPR", chip=chip)

siliconcompiler/tools/xdm/convert.py

@@ -24,9 +24,9 @@ def setup(chip):
 
     chip.add('tool', tool, 'task', task, 'option', '--auto',
              step=step, index=index)
-    chip.add('tool', tool, 'task', task, 'option', '--source_file_format hspice',
+    chip.add('tool', tool, 'task', task, 'option', ['--source_file_format', 'hspice'],
              step=step, index=index)
-    chip.add('tool', tool, 'task', task, 'option', f'--dir_out outputs/{design}.xyce',
+    chip.add('tool', tool, 'task', task, 'option', ['--dir_out', f'outputs/{design}.xyce'],
              step=step, index=index)
 
     chip.set('tool', 'xdm', 'task', 'convert', 'var', 'rename', 'true',

siliconcompiler/tools/xyce/simulate.py

@@ -48,7 +48,7 @@ def setup(chip):
                 step=step, index=index) == ['true']:
         chip.add('tool', tool, 'task', task, 'output', f'{design}.raw',
                  step=step, index=index)
-        chip.add('tool', tool, 'task', task, 'option', f'-r outputs/{design}.raw',
+        chip.add('tool', tool, 'task', task, 'option', ['-r', f'outputs/{design}.raw'],
                  step=step, index=index)
 
 

siliconcompiler/tools/yosys/sc_synth_asic.tcl

@@ -32,18 +32,83 @@ set sc_pdk [sc_cfg_get option pdk]
 
 source "$sc_refdir/procs.tcl"
 
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
+if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
+    set sc_macro_libraries \
+        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
+} else {
+    set sc_macro_libraries []
+}
+set sc_mainlib [lindex $sc_logiclibs 0]
+
+set sc_abc_constraints \
+    [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
+
+set sc_blackboxes []
+foreach lib $sc_macrolibs {
+    if { [sc_cfg_exists library $lib output blackbox verilog] } {
+        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
+            lappend sc_blackboxes $lib_f
+        }
+    }
+}
+
+set sc_memory_libmap_files ""
+if { [sc_cfg_tool_task_exists file memory_libmap] } {
+    set sc_memory_libmap_files [sc_cfg_tool_task_get file memory_libmap]
+}
+
+set sc_memory_techmap_files ""
+if { [sc_cfg_tool_task_exists file memory_techmap] } {
+    set sc_memory_techmap_files [sc_cfg_tool_task_get file memory_techmap]
+}
+
+########################################################
+# Read Libraries
+########################################################
+
+foreach lib_file "$sc_libraries $sc_macro_libraries" {
+    yosys read_liberty -setattr liberty_cell -lib $lib_file
+}
+foreach bb_file $sc_blackboxes {
+    yosys log "Reading blackbox model file: $bb_file"
+    yosys read_verilog -setattr blackbox -sv $bb_file
+}
+
+# Before working on the design, we mask out any module supplied via
+# `blackbox_modules`. This allows synthesis of parts of the design without having
+# to modify the input RTL.
+if { [sc_cfg_tool_task_exists var blackbox_modules] } {
+    foreach bb [sc_cfg_tool_task_get var blackbox_modules] {
+        foreach module [get_modules $bb] {
+            yosys log "Blackboxing module: $module"
+            yosys blackbox $module
+        }
+    }
+}
+
 ########################################################
 # Design Inputs
 ########################################################
 
 set input_verilog "inputs/$sc_design.v"
 if { ![file exists $input_verilog] } {
-    set input_verilog []
-    if { [sc_cfg_exists input rtl systemverilog] } {
-        lappend input_verilog {*}[sc_cfg_get input rtl systemverilog]
-    }
-    if { [sc_cfg_exists input rtl verilog] } {
-        lappend input_verilog {*}[sc_cfg_get input rtl verilog]
+    set input_verilog "inputs/$sc_design.sv"
+    if { ![file exists $input_verilog] } {
+        set input_verilog []
+        if { [sc_cfg_exists input rtl systemverilog] } {
+            lappend input_verilog {*}[sc_cfg_get input rtl systemverilog]
+        }
+        if { [sc_cfg_exists input rtl verilog] } {
+            lappend input_verilog {*}[sc_cfg_get input rtl verilog]
+        }
     }
 }
 
@@ -63,9 +128,12 @@ if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugi
     yosys read_slang \
         -D SYNTHESIS \
         --keep-hierarchy \
+        --ignore-assertions \
+        --allow-use-before-declare \
         --top $sc_design \
         {*}$slang_params \
         {*}$input_verilog
+    yosys setattr -unset init
 } else {
     # Use -noblackbox to correctly interpret empty modules as empty,
     # actual black boxes are read in later
@@ -119,44 +187,6 @@ proc get_modules { { find "*" } } {
     return [lsort $modules]
 }
 
-####################
-# DESIGNER's CHOICE
-####################
-
-set sc_logiclibs [sc_get_asic_libraries logic]
-set sc_macrolibs [sc_get_asic_libraries macro]
-
-set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
-if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
-    set sc_macro_libraries \
-        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
-} else {
-    set sc_macro_libraries []
-}
-set sc_mainlib [lindex $sc_logiclibs 0]
-
-set sc_abc_constraints \
-    [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
-
-set sc_blackboxes []
-foreach lib $sc_macrolibs {
-    if { [sc_cfg_exists library $lib output blackbox verilog] } {
-        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
-            lappend sc_blackboxes $lib_f
-        }
-    }
-}
-
-set sc_memory_libmap_files ""
-if { [sc_cfg_tool_task_exists file memory_libmap] } {
-    set sc_memory_libmap_files [sc_cfg_tool_task_get file memory_libmap]
-}
-
-set sc_memory_techmap_files ""
-if { [sc_cfg_tool_task_exists file memory_techmap] } {
-    set sc_memory_techmap_files [sc_cfg_tool_task_get file memory_techmap]
-}
-
 #########################
 # Schema helper functions
 #########################
@@ -209,34 +239,10 @@ proc get_buffer_cell { } {
     return "$cell $in $out"
 }
 
-########################################################
-# Read Libraries
-########################################################
-
-foreach lib_file "$sc_libraries $sc_macro_libraries" {
-    yosys read_liberty -setattr liberty_cell -lib $lib_file
-}
-foreach bb_file $sc_blackboxes {
-    yosys log "Reading blackbox model file: $bb_file"
-    yosys read_verilog -setattr blackbox -sv $bb_file
-}
-
 ########################################################
 # Synthesis
 ########################################################
 
-# Before working on the design, we mask out any module supplied via
-# `blackbox_modules`. This allows synthesis of parts of the design without having
-# to modify the input RTL.
-if { [sc_cfg_tool_task_exists var blackbox_modules] } {
-    foreach bb [sc_cfg_tool_task_get var blackbox_modules] {
-        foreach module [get_modules $bb] {
-            yosys log "Blackboxing module: $module"
-            yosys blackbox $module
-        }
-    }
-}
-
 # Although the `synth` command also runs `hierarchy`, we run it here without the
 # `-check` flag first in order to resolve parameters before looking for missing
 # modules. This works around the fact that Surelog doesn't pickle modules that

siliconcompiler/tools/yosys/syn_asic.py

@@ -36,6 +36,8 @@ def setup(chip):
     # Input/output requirements.
     if f'{design}.v' in input_provides(chip, step, index):
         chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    elif f'{design}.sv' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.sv', step=step, index=index)
     else:
         added = False
         added |= add_require_input(chip, 'input', 'rtl', 'systemverilog',
@@ -565,8 +567,6 @@ def _generate_cell_area_report(chip):
             area = info["area"]
 
         for cell, inst_count in info["num_cells_by_type"].items():
-            # print(module, cell, inst_count)
-
             cell_area, cell_count = get_area_count(cell)
 
             count += cell_count * inst_count

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "e78e29127134a0b95ebcd5661895c6dc4651e641",
+    "git-commit": "ce617810e4dc11b3cdb5a267ef3454788f81aaf0",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "109bc9ab5e35b830db9569f741db09e468704e6b",
+    "git-commit": "b32eed9a849381172a5d3208cc7798a8a11c4c9b",
     "auto-update": true
   },
   "netgen": {
@@ -41,7 +41,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.30.0",
+    "version": "0.30.1",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -71,7 +71,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
+    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
     "auto-update": false
   },
   "icepack": {
@@ -96,7 +96,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.52",
+    "git-commit": "v0.53",
     "version-prefix": "",
     "auto-update": true
   },
@@ -144,7 +144,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "a95ef24f0307230ae25ea6f2216d2fe8b8ece0be",
+    "git-commit": "7d4959430442ac1d7e3bf7b3e55d648293a5ac7b",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -156,7 +156,7 @@
   },
   "yosys-parmys": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
+    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
     "docker-depends": [
       "yosys",
       "vpr"

siliconcompiler/toolscripts/ubuntu22/install-vpr.sh

@@ -17,8 +17,6 @@ git submodule update --init --recursive
 
 ./install_apt_packages.sh
 
-sudo apt-get install -y libtbb-dev
-
 args=
 if [ ! -z ${PREFIX} ]; then
     args="-DCMAKE_INSTALL_PREFIX=$PREFIX"

siliconcompiler/toolscripts/ubuntu24/install-vpr.sh

@@ -17,8 +17,6 @@ git submodule update --init --recursive
 
 ./install_apt_packages.sh
 
-sudo apt-get install -y libtbb-dev
-
 args=
 if [ ! -z ${PREFIX} ]; then
     args="-DCMAKE_INSTALL_PREFIX=$PREFIX"

siliconcompiler/utils/__init__.py

@@ -1,11 +1,11 @@
 import contextlib
-import hashlib
 import os
 import re
 import psutil
 import shutil
-from pathlib import Path, PurePosixPath
+from pathlib import Path
 from jinja2 import Environment, FileSystemLoader
+from siliconcompiler.schema.parametervalue import PathNodeValue
 
 import sys
 if sys.version_info < (3, 10):
@@ -231,7 +231,9 @@ def sc_open(path, *args, **kwargs):
 def get_file_template(path,
                       root=os.path.join(
                           os.path.dirname(
-                              os.path.dirname(os.path.abspath(__file__))), 'templates')):
+                              os.path.dirname(os.path.abspath(__file__))),
+                          'data',
+                          'templates')):
     if os.path.isabs(path):
         root = os.path.dirname(path)
         path = os.path.basename(path)
@@ -325,31 +327,6 @@ def grep(chip, args, line):
         return line
 
 
-#######################################
-def _resolve_env_vars(chip, filepath, step, index):
-    if not filepath:
-        return None
-
-    env_save = os.environ.copy()
-
-    os.environ.update(get_env_vars(chip, step, index))
-    resolved_path = os.path.expandvars(filepath)
-
-    os.environ.clear()
-    os.environ.update(env_save)
-
-    resolved_path = os.path.expanduser(resolved_path)
-
-    # variables that don't exist in environment get ignored by `expandvars`,
-    # but we can do our own error checking to ensure this doesn't result in
-    # silent bugs
-    envvars = re.findall(r'\$\{?(\w+)\}?', resolved_path)
-    for var in envvars:
-        chip.logger.warning(f'Variable {var} in {filepath} not defined in environment')
-
-    return resolved_path
-
-
 #######################################
 def get_env_vars(chip, step, index):
     '''
@@ -373,69 +350,6 @@ def get_env_vars(chip, step, index):
     return schema_env
 
 
-###########################################################################
-def find_sc_file(chip, filename, missing_ok=False, search_paths=None, step=None, index=None):
-    """
-    Returns the absolute path for the filename provided.
-
-    Searches the for the filename provided and returns the absolute path.
-    If no valid absolute path is found during the search, None is returned.
-
-    Shell variables ('$' followed by strings consisting of numbers,
-    underscores, and digits) are replaced with the variable value.
-
-    Args:
-        filename (str): Relative or absolute filename.
-        missing_ok (bool): If False, error out if no valid absolute path
-            found, rather than returning None.
-        search_paths (list): List of directories to search under instead of
-            the defaults.
-        step (str): Step name
-        index (str): Index
-
-    Returns:
-        Returns absolute path of 'filename' if found, otherwise returns
-        None.
-
-    Examples:
-        >>> chip._find_sc_file('flows/asicflow.py')
-        Returns the absolute path based on the sc installation directory.
-
-    """
-
-    if not filename:
-        return None
-
-    # Replacing environment variables
-    filename = _resolve_env_vars(chip, filename, step, index)
-
-    # If we have an absolute path, pass-through here
-    if os.path.isabs(filename) and os.path.exists(filename):
-        return filename
-
-    # Otherwise, search relative to search_paths
-    if search_paths is None:
-        search_paths = [chip.cwd]
-
-    searchdirs = ', '.join([str(p) for p in search_paths])
-    chip.logger.debug(f"Searching for file {filename} in {searchdirs}")
-
-    result = None
-    for searchdir in search_paths:
-        if not os.path.isabs(searchdir):
-            searchdir = os.path.join(chip.cwd, searchdir)
-
-        abspath = os.path.abspath(os.path.join(searchdir, filename))
-        if os.path.exists(abspath):
-            result = abspath
-            break
-
-    if result is None and not missing_ok:
-        chip.error(f"File {filename} was not found")
-
-    return result
-
-
 def get_plugins(system, name=None):
     '''
     Search for python modules with a specific function
@@ -470,32 +384,14 @@ def truncate_text(text, width):
     return text
 
 
-def get_hashed_filename(path, package=None, hash=hashlib.sha1):
+def get_hashed_filename(path, package=None):
     '''
     Utility to map collected file to an unambiguous name based on its path.
 
     The mapping looks like:
-    path/to/file.ext => file_<hash('path/to/file')>.ext
+    path/to/file.ext => file_<hash('path/to')>.ext
     '''
-    path = PurePosixPath(path)
-    ext = ''.join(path.suffixes)
-
-    # strip off all file suffixes to get just the bare name
-    barepath = path
-    while barepath.suffix:
-        barepath = PurePosixPath(barepath.stem)
-    filename = str(barepath.parts[-1])
-
-    if not package:
-        package = ''
-    else:
-        package = f'{package}:'
-
-    path_to_hash = f'{package}{str(path)}'
-
-    pathhash = hash(path_to_hash.encode('utf-8')).hexdigest()
-
-    return f'{filename}_{pathhash}{ext}'
+    return PathNodeValue.generate_hashed_path(path, package)
 
 
 def get_cores(chip, physical=False):