siliconcompiler 0.32.3__py3-none-any.whl → 0.33.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -9,7 +9,7 @@ source ./sc_manifest.tcl
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Error checking
@@ -122,4 +122,4 @@ if { [llength $pdn_blockages] > 0 } {
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -9,7 +9,7 @@ source ./sc_manifest.tcl
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Buffer ports
@@ -70,4 +70,4 @@ estimate_parasitics -placement
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -9,7 +9,7 @@ source ./sc_manifest.tcl
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Timing Repair
@@ -159,4 +159,4 @@ estimate_parasitics $parasitics_stage
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl

@@ -9,7 +9,7 @@ source ./sc_manifest.tcl
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Generate LEF
@@ -122,4 +122,4 @@ foreach net [sc_psm_check_nets] {
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -411,12 +411,18 @@ proc sc_psm_check_nets { } {
 # Save an image
 ###########################
 
-proc sc_save_image { title path { pixels 1000 } } {
+proc sc_save_image { title path { gif false } { pixels 1000 } } {
     utl::info FLW 1 "Saving \"$title\" to $path"
 
     save_image -resolution [sc_image_resolution $pixels] \
         -area [sc_image_area] \
         $path
+
+    if { $gif } {
+        save_animated_gif -add \
+            -resolution [sc_image_resolution $pixels] \
+            -area [sc_image_area]
+    }
 }
 
 ###########################
@@ -480,6 +486,9 @@ proc sc_image_setup_default { } {
     gui::set_display_controls "Misc/Scale bar" visible true
     gui::set_display_controls "Misc/Highlight selected" visible true
     gui::set_display_controls "Misc/Detailed view" visible true
+    if { [sc_check_version 21574] } {
+        gui::set_display_controls "Misc/Labels" visible true
+    }
 }
 
 ###########################
@@ -597,6 +606,22 @@ proc sc_has_input_files { type key } {
     return [expr { [sc_get_input_files $type $key] != [] }]
 }
 
+proc sc_path_group { args } {
+    sta::parse_key_args "sc_path_group" args \
+        keys {-name -to -from} \
+        flags {}
+
+    sta::check_argc_eq0 "sc_path_group" $args
+
+    if { [llength $keys(-from)] == 0 } {
+        return
+    }
+    if { [llength $keys(-to)] == 0 } {
+        return
+    }
+    group_path -name $keys(-name) -from $keys(-from) -to $keys(-to)
+}
+
 proc sc_setup_sta { } {
     set sta_early_timing_derate [lindex [sc_cfg_tool_task_get var sta_early_timing_derate] 0]
     set sta_late_timing_derate [lindex [sc_cfg_tool_task_get var sta_late_timing_derate] 0]
@@ -609,6 +634,37 @@ proc sc_setup_sta { } {
         set_timing_derate -late $sta_late_timing_derate
     }
 
+    # Create path groups
+    if {
+        [lindex [sc_cfg_tool_task_get var sta_define_path_groups] 0] == "true" &&
+        [llength [sta::path_group_names]] == 0
+    } {
+        sc_path_group -name in2out -from [all_inputs -no_clocks] -to [all_outputs]
+
+        if {
+            [llength [all_clocks]] == 1 ||
+            [lindex [sc_cfg_tool_task_get var sta_unique_path_groups_per_clock] 0] == "false"
+        } {
+            sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
+            sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
+            sc_path_group -name reg2out -from [all_registers] -to [all_outputs]
+        } else {
+            foreach clock [all_clocks] {
+                set clk_name [get_property $clock name]
+                sc_path_group -name in2reg.${clk_name} \
+                    -from [all_inputs -no_clocks] \
+                    -to [all_registers -clock $clock]
+                sc_path_group -name reg2reg.${clk_name} \
+                    -from [all_registers -clock $clock] \
+                    -to [all_registers -clock $clock]
+                sc_path_group -name reg2out.${clk_name} \
+                    -from [all_registers -clock $clock] \
+                    -to [all_outputs]
+            }
+        }
+    }
+    utl::info FLW 1 "Timing path groups: [sta::path_group_names]"
+
     # Check timing setup
     if { [sc_cfg_tool_task_check_in_list check_setup var reports] } {
         tee -file "reports/check_timing_setup.rpt" {check_setup -verbose}

siliconcompiler/tools/openroad/scripts/common/screenshot.tcl

@@ -5,7 +5,7 @@ set sc_resolution \
 
 sc_image_setup_default
 
-sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution
+sc_save_image "screenshot" "outputs/${sc_design}.png" false $sc_resolution
 
 gui::restore_display_controls
 
@@ -14,5 +14,5 @@ if {
     [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
     == "true"
 } {
-    source -echo "${sc_refdir}/sc_write_images.tcl"
+    source "${sc_refdir}/sc_write_images.tcl"
 }

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -1,6 +1,6 @@
 # Adopted from https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3f9740e6b3643835e918d78ae1d377d65af0f0fb/flow/scripts/save_images.tcl
 
-proc sc_image_heatmap { name ident image_name title { allow_bin_adjust 1 } } {
+proc sc_image_heatmap { name ident image_name title { gif false } { allow_bin_adjust 1 } } {
     set ord_heatmap_bins_x [lindex [sc_cfg_tool_task_get var ord_heatmap_bins_x] 0]
     set ord_heatmap_bins_y [lindex [sc_cfg_tool_task_get var ord_heatmap_bins_y] 0]
 
@@ -49,7 +49,7 @@ proc sc_image_heatmap { name ident image_name title { allow_bin_adjust 1 } } {
 
     gui::set_display_controls "Heat Maps/${name}" visible true
 
-    sc_save_image "$title heatmap" reports/images/heatmap/${image_name}
+    sc_save_image "$title heatmap" reports/images/heatmap/${image_name} $gif
 
     gui::set_display_controls "Heat Maps/${name}" visible false
 }
@@ -125,6 +125,13 @@ proc sc_image_irdrop { net corner } {
         return
     }
 
+    set gif false
+    if { [sc_check_version 21574] } {
+        set gif true
+    }
+    if { $gif } {
+        save_animated_gif -start "reports/images/heatmap/irdrop/${net}.${corner}.gif"
+    }
     foreach layer [[ord::get_db_tech] getLayers] {
         if { [$layer getRoutingLevel] == 0 } {
             continue
@@ -136,10 +143,26 @@ proc sc_image_irdrop { net corner } {
         gui::set_heatmap IRDrop Layer $layer_name
         gui::set_heatmap IRDrop rebuild
 
+        set label ""
+        if { [sc_check_version 21574] } {
+            set box [[ord::get_db_block] getDieArea]
+            set x [ord::dbu_to_microns [$box xMax]]
+            set y [ord::dbu_to_microns [$box yMin]]
+            set label [add_label -position "$x $y" -anchor "bottom right" -color white $layer_name]
+        }
+
         sc_image_heatmap "IR Drop" \
             "IRDrop" \
             "irdrop/${net}.${corner}.${layer_name}.png" \
-            "IR drop for $net on $layer_name for $corner"
+            "IR drop for $net on $layer_name for $corner" \
+            $gif
+
+        if { $label != "" } {
+            gui::delete_label $label
+        }
+    }
+    if { $gif } {
+        save_animated_gif -end
     }
 }
 
@@ -154,6 +177,7 @@ proc sc_image_routing_congestion { } {
         "Routing" \
         "routing_congestion.png" \
         "routing congestion" \
+        0 \
         0
 }
 
@@ -170,6 +194,7 @@ proc sc_image_estimated_routing_congestion { } {
             "RUDY" \
             "estimated_routing_congestion.png" \
             "estimated routing congestion" \
+            0 \
             0
     } err
     unsuppress_message GRT 10

siliconcompiler/tools/openroad/scripts/sc_rcx.tcl

@@ -48,5 +48,5 @@ read_lef $sc_techlef
 set_thread_count [sc_cfg_tool_task_get threads]
 
 utl::set_metrics_stage "sc__step__{}"
-source -echo "${sc_refdir}/rcx/sc_${sc_task}.tcl"
+source "${sc_refdir}/rcx/sc_${sc_task}.tcl"
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -39,7 +39,7 @@ set sc_macrolibs [sc_get_asic_libraries macro]
 # Setup debugging
 ###############################
 
-source -echo "$sc_refdir/common/debugging.tcl"
+source "$sc_refdir/common/debugging.tcl"
 
 ###############################
 # Source helper functions
@@ -85,7 +85,7 @@ utl::push_metrics_stage "sc__prestep__{}"
 if { [sc_cfg_tool_task_exists prescript] } {
     foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
         puts "Sourcing pre script: ${sc_pre_script}"
-        source -echo $sc_pre_script
+        source $sc_pre_script
     }
 }
 utl::pop_metrics_stage
@@ -160,7 +160,7 @@ utl::push_metrics_stage "sc__poststep__{}"
 if { [sc_cfg_tool_task_exists postscript] } {
     foreach sc_post_script [sc_cfg_tool_task_get postscript] {
         puts "Sourcing post script: ${sc_post_script}"
-        source -echo $sc_post_script
+        source $sc_post_script
     }
 }
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/sc_show.tcl

@@ -20,7 +20,7 @@ set sc_refdir [sc_cfg_tool_task_get refdir]
 # Setup debugging
 ###############################
 
-source -echo "$sc_refdir/common/debugging.tcl"
+source "$sc_refdir/common/debugging.tcl"
 
 ###############################
 # Setup helper functions
@@ -58,11 +58,11 @@ set_thread_count [sc_cfg_tool_task_get threads]
 # Read Files
 ###############################
 
-source -echo "$sc_refdir/common/read_liberty.tcl"
+source "$sc_refdir/common/read_liberty.tcl"
 
-source -echo "$sc_refdir/common/read_input_files.tcl"
+source "$sc_refdir/common/read_input_files.tcl"
 
-source -echo "$sc_refdir/common/read_timing_constraints.tcl"
+source "$sc_refdir/common/read_timing_constraints.tcl"
 
 ###############################
 # Common Setup
@@ -84,7 +84,7 @@ utl::push_metrics_stage "sc__prestep__{}"
 if { [sc_cfg_tool_task_exists prescript] } {
     foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
         puts "Sourcing pre script: ${sc_pre_script}"
-        source -echo $sc_pre_script
+        source $sc_pre_script
     }
 }
 utl::pop_metrics_stage
@@ -102,7 +102,7 @@ if { [llength $openroad_dont_touch] > 0 } {
 }
 
 if { $sc_task == "screenshot" } {
-    source -echo "$sc_refdir/common/screenshot.tcl"
+    source "$sc_refdir/common/screenshot.tcl"
 }
 
 if { [lindex [sc_cfg_tool_task_get {var} show_exit] 0] == "true" } {

siliconcompiler/tools/slang/__init__.py

@@ -70,38 +70,38 @@ def common_runtime_options(chip):
                                  'param'])
 
     if opts['libext']:
-        options.append(f'--libext {",".join(opts["libext"])}')
+        options.extend(['--libext', f'{",".join(opts["libext"])}'])
 
     #####################
     # Library directories
     #####################
     if opts['ydir']:
-        options.append(f'-y {",".join(opts["ydir"])}')
+        options.extend(['-y', f'{",".join(opts["ydir"])}'])
 
     #####################
     # Library files
     #####################
     if opts['vlib']:
-        options.append(f'-libfile {",".join(opts["vlib"])}')
+        options.extend(['-libfile', f'{",".join(opts["vlib"])}'])
 
     #####################
     # Include paths
     #####################
     if opts['idir']:
-        options.append(f'--include-directory {",".join(opts["idir"])}')
+        options.extend(['--include-directory', f'{",".join(opts["idir"])}'])
 
     #######################
     # Variable Definitions
     #######################
     for value in opts['define']:
-        options.append('-D ' + value)
+        options.extend(['-D', value])
 
     #######################
     # Command files
     #######################
     cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
     if cmdfiles:
-        options.append(f'-F {",".join(cmdfiles)}')
+        options.extend(['-F', f'{",".join(cmdfiles)}'])
 
     #######################
     # Sources
@@ -114,7 +114,7 @@ def common_runtime_options(chip):
     #######################
     # Top Module
     #######################
-    options.append('--top ' + chip.top(step, index))
+    options.extend(['--top', chip.top(step, index)])
 
     ###############################
     # Parameters (top module only)
@@ -122,7 +122,7 @@ def common_runtime_options(chip):
     # Set up user-provided parameters to ensure we elaborate the correct modules
     for param, value in opts['param']:
         value = value.replace('"', '\\"')
-        options.append(f'-G {param}={value}')
+        options.extend(['-G', f'{param}={value}'])
 
     return options
 
@@ -211,5 +211,5 @@ def _diagnostics(chip, driver, compilation):
     for diag in compilation.getAllDiagnostics():
         diags.issue(diag)
 
-    record_metric(chip, step, index, 'errors', diags.numErrors, [])
-    record_metric(chip, step, index, 'warnings', diags.numWarnings, [])
+    record_metric(chip, step, index, 'errors', diags.numErrors, [f'sc_{step}{index}.log'])
+    record_metric(chip, step, index, 'warnings', diags.numWarnings, [f'sc_{step}{index}.log'])

siliconcompiler/tools/surelog/parse.py

@@ -83,13 +83,13 @@ def runtime_options(chip):
     # Library directories
     #####################
     for value in opts['ydir']:
-        cmdlist.append('-y ' + value)
+        cmdlist.extend(['-y', value])
 
     #####################
     # Library files
     #####################
     for value in opts['vlib']:
-        cmdlist.append('-v ' + value)
+        cmdlist.extend(['-v', value])
 
     #####################
     # Include paths
@@ -107,7 +107,7 @@ def runtime_options(chip):
     # Command files
     #######################
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
-        cmdlist.append('-f ' + value)
+        cmdlist.extend(['-f', + value])
 
     #######################
     # Sources
@@ -120,7 +120,7 @@ def runtime_options(chip):
     #######################
     # Top Module
     #######################
-    cmdlist.append(f'-top {chip.top(step, index)}')
+    cmdlist.extend(['-top', chip.top(step, index)])
 
     ###############################
     # Parameters (top module only)

siliconcompiler/tools/sv2v/convert.py

@@ -23,6 +23,26 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '--numeric-version')
     chip.set('tool', tool, 'version', '>=0.0.9', clobber=False)
 
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'skip_convert']), step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'var', 'skip_convert',
+             'true/false, if true will skip converting system verilog to verilog', field='help')
+    skip = chip.get('tool', tool, 'task', task, 'var', 'skip_convert', step=step, index=index)
+    if skip:
+        skip = skip[0] == "true"
+    else:
+        skip = False
+    chip.set('tool', tool, 'task', task, 'var', 'skip_convert', skip,
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.sv', step=step, index=index)
+
+    if skip:
+        chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.sv', step=step, index=index)
+        return "passing system verilog along"
+
+    chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.v', step=step, index=index)
+
     chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
@@ -41,6 +61,3 @@ def setup(chip):
              step=step, index=index)
     chip.add('tool', tool, 'task', task, 'option', "--write=outputs/" + topmodule + ".v",
              step=step, index=index)
-
-    chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.sv', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.v', step=step, index=index)

siliconcompiler/tools/verilator/compile.py

@@ -161,12 +161,12 @@ def runtime_options(chip):
 
     if c_flags:
         cflags_str = ' '.join(c_flags)
-        cmdlist.extend(['-CFLAGS', f'"{cflags_str}"'])
+        cmdlist.extend(['-CFLAGS', cflags_str])
 
     ld_flags = chip.get('tool', tool, 'task', task, 'var', 'ldflags', step=step, index=index)
     if ld_flags:
         ldflags_str = ' '.join(ld_flags)
-        cmdlist.extend(['-LDFLAGS', f'"{ldflags_str}"'])
+        cmdlist.extend(['-LDFLAGS', ldflags_str])
 
     for value in get_input_files(chip, 'input', 'hll', 'c'):
         cmdlist.append(value)

siliconcompiler/tools/verilator/verilator.py

@@ -144,9 +144,9 @@ def runtime_options(chip):
         cmdlist.append(f'inputs/{design}.v')
     else:
         for value in frontend_opts['ydir']:
-            cmdlist.append(f'-y {value}')
+            cmdlist.extend(['-y', value])
         for value in frontend_opts['vlib']:
-            cmdlist.append(f'-v {value}')
+            cmdlist.extend(['-v', value])
         for value in frontend_opts['idir']:
             cmdlist.append(f'-I{value}')
         for value in frontend_opts['define']:
@@ -160,7 +160,7 @@ def runtime_options(chip):
             cmdlist.append(value)
 
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
-        cmdlist.append(f'-f {value}')
+        cmdlist.extend(['-f', value])
 
     return cmdlist
 

siliconcompiler/tools/vpr/place.py

@@ -62,7 +62,7 @@ def runtime_options(chip):
         graphics_command_str = " ".join(graphics_commands)
 
         options.append("--graphics_commands")
-        options.append(f"\"{graphics_command_str}\"")
+        options.append(graphics_command_str)
 
     return options
 

siliconcompiler/tools/vpr/route.py

@@ -62,8 +62,8 @@ def runtime_options(chip):
 
     options.append('--route')
     # To run only the routing step we need to pass in the placement files
-    options.append(f'--net_file inputs/{design}.net')
-    options.append(f'--place_file inputs/{design}.place')
+    options.extend(['--net_file', f'inputs/{design}.net'])
+    options.extend(['--place_file', f'inputs/{design}.place'])
 
     enable_images = chip.get('tool', tool, 'task', task, 'var', 'enable_images',
                              step=step, index=index)[0]
@@ -72,7 +72,7 @@ def runtime_options(chip):
                                 step=step, index=index)
 
     if (len(route_iterations) > 0):
-        options.append(f'--max_router_iterations {route_iterations[0]}')
+        options.extend(['--max_router_iterations', route_iterations[0]])
 
     if enable_images == 'true':
         design = chip.top()
@@ -102,7 +102,7 @@ def runtime_options(chip):
         graphics_command_str = " ".join(graphics_commands)
 
         options.append("--graphics_commands")
-        options.append(f"\"{graphics_command_str}\"")
+        options.append(graphics_command_str)
 
     return options
 

siliconcompiler/tools/vpr/screenshot.py

@@ -49,6 +49,6 @@ def runtime_options(chip):
         raise SiliconCompilerError(f"Incorrect file type {show_type}", chip=chip)
 
     options.append("--graphics_commands")
-    options.append(f"\"{screenshot_command_str}\"")
+    options.append(screenshot_command_str)
 
     return options

siliconcompiler/tools/vpr/show.py

@@ -64,14 +64,14 @@ def generic_show_options(chip):
         raise SiliconCompilerError("Blif file does not exist", chip=chip)
 
     if os.path.exists(net_file):
-        options.append(f'--net_file {net_file}')
+        options.extend(['--net_file', net_file])
     else:
         raise SiliconCompilerError("Net file does not exist", chip=chip)
 
     if os.path.exists(route_file) and os.path.exists(place_file):
         options.append('--analysis')
-        options.append(f'--place_file {place_file}')
-        options.append(f'--route_file {route_file}')
+        options.extend(['--place_file', place_file])
+        options.extend(['--route_file', route_file])
     elif os.path.exists(place_file):
         # NOTE: This is a workaround to display the VPR GUI on the output of the place step.
         # VPR GUI can be invoked during the place, route or analysis steps - not after they are run.
@@ -81,8 +81,8 @@ def generic_show_options(chip):
         # the placed design. Setting max_router_iterations to 0 avoids running routing iterations
         # and provides a fast way to invoke VPR GUI on the placed design.
         options.append('--route')
-        options.append('--max_router_iterations 0')
-        options.append(f'--place_file {place_file}')
+        options.extend(['--max_router_iterations', 0])
+        options.extend(['--place_file', place_file])
     else:
         raise SiliconCompilerError("Place file does not exist", chip=chip)