qiskit 1.4.1__cp39-abi3-win_amd64.whl → 2.0.0rc1__cp39-abi3-win_amd64.whl

qiskit/transpiler/passes/scheduling/alignments/align_measures.py

@@ -1,255 +0,0 @@
-# This code is part of Qiskit.
-#
-# (C) Copyright IBM 2021.
-#
-# This code is licensed under the Apache License, Version 2.0. You may
-# obtain a copy of this license in the LICENSE.txt file in the root directory
-# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
-#
-# Any modifications or derivative works of this code must retain this
-# copyright notice, and modified files need to carry a notice indicating
-# that they have been altered from the originals.
-
-"""Align measurement instructions."""
-from __future__ import annotations
-import itertools
-import warnings
-from collections import defaultdict
-from collections.abc import Iterable
-from typing import Type
-
-from qiskit.circuit.quantumcircuit import ClbitSpecifier, QubitSpecifier
-
-from qiskit.circuit.delay import Delay
-from qiskit.circuit.measure import Measure
-from qiskit.circuit.parameterexpression import ParameterExpression
-from qiskit.dagcircuit import DAGCircuit
-from qiskit.transpiler.basepasses import TransformationPass
-from qiskit.transpiler.exceptions import TranspilerError
-from qiskit.utils.deprecation import deprecate_func
-
-
-class AlignMeasures(TransformationPass):
-    """Measurement alignment.
-
-    This is a control electronics aware optimization pass.
-
-    In many quantum computing architectures gates (instructions) are implemented with
-    shaped analog stimulus signals. These signals are digitally stored in the
-    waveform memory of the control electronics and converted into analog voltage signals
-    by electronic components called digital to analog converters (DAC).
-
-    In a typical hardware implementation of superconducting quantum processors,
-    a single qubit instruction is implemented by a
-    microwave signal with the duration of around several tens of ns with a per-sample
-    time resolution of ~0.1-10ns, as reported by ``backend.configuration().dt``.
-    In such systems requiring higher DAC bandwidth, control electronics often
-    defines a `pulse granularity`, in other words a data chunk, to allow the DAC to
-    perform the signal conversion in parallel to gain the bandwidth.
-
-    Measurement alignment is required if a backend only allows triggering ``measure``
-    instructions at a certain multiple value of this pulse granularity.
-    This value is usually provided by ``backend.configuration().timing_constraints``.
-
-    In Qiskit SDK, the duration of delay can take arbitrary value in units of ``dt``,
-    thus circuits involving delays may violate the above alignment constraint (i.e. misalignment).
-    This pass shifts measurement instructions to a new time position to fix the misalignment,
-    by inserting extra delay right before the measure instructions.
-    The input of this pass should be scheduled :class:`~qiskit.dagcircuit.DAGCircuit`,
-    thus one should select one of the scheduling passes
-    (:class:`~qiskit.transpiler.passes.ALAPSchedule` or
-    :class:`~qiskit.trasnpiler.passes.ASAPSchedule`) before calling this.
-
-    Examples:
-        We assume executing the following circuit on a backend with ``alignment=16``.
-
-        .. code-block:: text
-
-                 ┌───┐┌────────────────┐┌─┐
-            q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├
-                 └───┘└────────────────┘└╥┘
-            c: 1/════════════════════════╩═
-                                         0
-
-        Note that delay of 100 dt induces a misalignment of 4 dt at the measurement.
-        This pass appends an extra 12 dt time shift to the input circuit.
-
-        .. code-block:: text
-
-                 ┌───┐┌────────────────┐┌─┐
-            q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├
-                 └───┘└────────────────┘└╥┘
-            c: 1/════════════════════════╩═
-                                         0
-
-        This pass always inserts a positive delay before measurements
-        rather than reducing other delays.
-
-    Notes:
-        The Backend may allow users to execute circuits violating the alignment constraint.
-        However, it may return meaningless measurement data mainly due to the phase error.
-    """
-
-    @deprecate_func(
-        additional_msg=(
-            "Instead, use :class:`~.ConstrainedReschedule`, which performs the same function "
-            "but also supports aligning to additional timing constraints."
-        ),
-        since="1.1.0",
-    )
-    def __init__(self, alignment: int = 1):
-        """Create new pass.
-
-        Args:
-            alignment: Integer number representing the minimum time resolution to
-                trigger measure instruction in units of ``dt``. This value depends on
-                the control electronics of your quantum processor.
-        """
-        super().__init__()
-        self.alignment = alignment
-
-    def run(self, dag: DAGCircuit):
-        """Run the measurement alignment pass on `dag`.
-
-        Args:
-            dag (DAGCircuit): DAG to be checked.
-
-        Returns:
-            DAGCircuit: DAG with consistent timing and op nodes annotated with duration.
-
-        Raises:
-            TranspilerError: If circuit is not scheduled.
-        """
-        time_unit = self.property_set["time_unit"]
-
-        if not _check_alignment_required(dag, self.alignment, Measure):
-            # return input as-is to avoid unnecessary scheduling.
-            # because following procedure regenerate new DAGCircuit,
-            # we should avoid continuing if not necessary from performance viewpoint.
-            return dag
-
-        # if circuit is not yet scheduled, schedule with ALAP method
-        if dag.duration is None:
-            raise TranspilerError(
-                f"This circuit {dag.name} may involve a delay instruction violating the "
-                "pulse controller alignment. To adjust instructions to "
-                "right timing, you should call one of scheduling passes first. "
-                "This is usually done by calling transpiler with scheduling_method='alap'."
-            )
-
-        # the following lines are basically copied from ASAPSchedule pass
-        #
-        # * some validations for non-scheduled nodes are dropped, since we assume scheduled input
-        # * pad_with_delay is called only with non-delay node to avoid consecutive delay
-        new_dag = dag.copy_empty_like()
-
-        qubit_time_available: dict[QubitSpecifier, int] = defaultdict(int)  # to track op start time
-        qubit_stop_times: dict[QubitSpecifier, int] = defaultdict(
-            int
-        )  # to track delay start time for padding
-        clbit_readable: dict[ClbitSpecifier, int] = defaultdict(int)
-        clbit_writeable: dict[ClbitSpecifier, int] = defaultdict(int)
-
-        def pad_with_delays(qubits: Iterable[QubitSpecifier], until, unit) -> None:
-            """Pad idle time-slots in ``qubits`` with delays in ``unit`` until ``until``."""
-            for q in qubits:
-                if qubit_stop_times[q] < until:
-                    idle_duration = until - qubit_stop_times[q]
-                    new_dag.apply_operation_back(Delay(idle_duration, unit), (q,), check=False)
-
-        for node in dag.topological_op_nodes():
-            # choose appropriate clbit available time depending on op
-            clbit_time_available = (
-                clbit_writeable if isinstance(node.op, Measure) else clbit_readable
-            )
-            # correction to change clbit start time to qubit start time
-            delta = node.op.duration if isinstance(node.op, Measure) else 0
-            start_time = max(
-                itertools.chain(
-                    (qubit_time_available[q] for q in node.qargs),
-                    (
-                        clbit_time_available[c] - delta
-                        for c in node.cargs + tuple(node.op.condition_bits)
-                    ),
-                )
-            )
-
-            if isinstance(node.op, Measure):
-                if start_time % self.alignment != 0:
-                    start_time = ((start_time // self.alignment) + 1) * self.alignment
-
-            if not isinstance(node.op, Delay):  # exclude delays for combining consecutive delays
-                pad_with_delays(node.qargs, until=start_time, unit=time_unit)
-                new_dag.apply_operation_back(node.op, node.qargs, node.cargs, check=False)
-
-            stop_time = start_time + node.op.duration
-            # update time table
-            for q in node.qargs:
-                qubit_time_available[q] = stop_time
-                if not isinstance(node.op, Delay):
-                    qubit_stop_times[q] = stop_time
-            for c in node.cargs:  # measure
-                clbit_writeable[c] = clbit_readable[c] = stop_time
-            for c in node.op.condition_bits:  # conditional op
-                clbit_writeable[c] = max(start_time, clbit_writeable[c])
-
-        working_qubits = qubit_time_available.keys()
-        circuit_duration = max(qubit_time_available[q] for q in working_qubits)
-        pad_with_delays(new_dag.qubits, until=circuit_duration, unit=time_unit)
-
-        new_dag.name = dag.name
-        new_dag.metadata = dag.metadata
-
-        # set circuit duration and unit to indicate it is scheduled
-        new_dag.duration = circuit_duration
-        new_dag.unit = time_unit
-
-        return new_dag
-
-
-def _check_alignment_required(
-    dag: DAGCircuit,
-    alignment: int,
-    instructions: Type | list[Type],
-) -> bool:
-    """Check DAG nodes and return a boolean representing if instruction scheduling is necessary.
-
-    Args:
-        dag: DAG circuit to check.
-        alignment: Instruction alignment condition.
-        instructions: Target instructions.
-
-    Returns:
-        If instruction scheduling is necessary.
-    """
-    if not isinstance(instructions, list):
-        instructions = [instructions]
-
-    if alignment == 1:
-        # disable alignment if arbitrary t0 value can be used
-        return False
-
-    if all(len(dag.op_nodes(inst)) == 0 for inst in instructions):
-        # disable alignment if target instruction is not involved
-        return False
-
-    # check delay durations
-    for delay_node in dag.op_nodes(Delay):
-        duration = delay_node.op.duration
-        if isinstance(duration, ParameterExpression):
-            # duration is parametrized:
-            # raise user warning if backend alignment is not 1.
-            warnings.warn(
-                f"Parametrized delay with {repr(duration)} is found in circuit {dag.name}. "
-                f"This backend requires alignment={alignment}. "
-                "Please make sure all assigned values are multiple values of the alignment.",
-                UserWarning,
-            )
-        else:
-            # duration is bound:
-            # check duration and trigger alignment if it violates constraint
-            if duration % alignment != 0:
-                return True
-
-    # disable alignment if all delays are multiple values of the alignment
-    return False

qiskit/transpiler/passes/scheduling/alignments/pulse_gate_validation.py

@@ -1,107 +0,0 @@
-# This code is part of Qiskit.
-#
-# (C) Copyright IBM 2021.
-#
-# This code is licensed under the Apache License, Version 2.0. You may
-# obtain a copy of this license in the LICENSE.txt file in the root directory
-# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
-#
-# Any modifications or derivative works of this code must retain this
-# copyright notice, and modified files need to carry a notice indicating
-# that they have been altered from the originals.
-
-"""Analysis passes for hardware alignment constraints."""
-
-from qiskit.dagcircuit import DAGCircuit
-from qiskit.pulse import Play
-from qiskit.transpiler.basepasses import AnalysisPass
-from qiskit.transpiler.exceptions import TranspilerError
-from qiskit.transpiler.target import Target
-from qiskit.utils.deprecate_pulse import deprecate_pulse_dependency
-
-
-class ValidatePulseGates(AnalysisPass):
-    """Check custom gate length.
-
-    This is a control electronics aware analysis pass.
-
-    Quantum gates (instructions) are often implemented with shaped analog stimulus signals.
-    These signals may be digitally stored in the waveform memory of the control electronics
-    and converted into analog voltage signals by electronic components known as
-    digital to analog converters (DAC).
-
-    In Qiskit SDK, we can define the pulse-level implementation of custom quantum gate
-    instructions, as a `pulse gate
-    <https://docs.quantum.ibm.com/guides/pulse>`__,
-    thus user gates should satisfy all waveform memory constraints imposed by the backend.
-
-    This pass validates all attached calibration entries and raises ``TranspilerError`` to
-    kill the transpilation process if any invalid calibration entry is found.
-    This pass saves users from waiting until job execution time to get an invalid pulse error from
-    the backend control electronics.
-    """
-
-    @deprecate_pulse_dependency
-    def __init__(
-        self,
-        granularity: int = 1,
-        min_length: int = 1,
-        target: Target = None,
-    ):
-        """Create new pass.
-
-        Args:
-            granularity: Integer number representing the minimum time resolution to
-                define the pulse gate length in units of ``dt``. This value depends on
-                the control electronics of your quantum processor.
-            min_length: Integer number representing the minimum data point length to
-                define the pulse gate in units of ``dt``. This value depends on
-                the control electronics of your quantum processor.
-            target: The :class:`~.Target` representing the target backend, if
-                ``target`` is specified then this argument will take
-                precedence and ``granularity`` and ``min_length`` will be ignored.
-        """
-        super().__init__()
-        self.granularity = granularity
-        self.min_length = min_length
-        if target is not None:
-            self.granularity = target.granularity
-            self.min_length = target.min_length
-
-    def run(self, dag: DAGCircuit):
-        """Run the pulse gate validation attached to ``dag``.
-
-        Args:
-            dag: DAG to be validated.
-
-        Returns:
-            DAGCircuit: DAG with consistent timing and op nodes annotated with duration.
-
-        Raises:
-            TranspilerError: When pulse gate violate pulse controller constraints.
-        """
-        if self.granularity == 1 and self.min_length == 1:
-            # we can define arbitrary length pulse with dt resolution
-            return
-
-        for gate, insts in dag.calibrations.items():
-            for qubit_param_pair, schedule in insts.items():
-                for _, inst in schedule.instructions:
-                    if isinstance(inst, Play):
-                        pulse = inst.pulse
-                        if pulse.duration % self.granularity != 0:
-                            raise TranspilerError(
-                                f"Pulse duration is not multiple of {self.granularity}. "
-                                "This pulse cannot be played on the specified backend. "
-                                f"Please modify the duration of the custom gate pulse {pulse.name} "
-                                f"which is associated with the gate {gate} of "
-                                f"qubit {qubit_param_pair[0]}."
-                            )
-                        if pulse.duration < self.min_length:
-                            raise TranspilerError(
-                                f"Pulse gate duration is less than {self.min_length}. "
-                                "This pulse cannot be played on the specified backend. "
-                                f"Please modify the duration of the custom gate pulse {pulse.name} "
-                                f"which is associated with the gate {gate} of "
-                                "qubit {qubit_param_pair[0]}."
-                            )

qiskit/transpiler/passes/scheduling/asap.py

@@ -1,175 +0,0 @@
-# This code is part of Qiskit.
-#
-# (C) Copyright IBM 2020.
-#
-# This code is licensed under the Apache License, Version 2.0. You may
-# obtain a copy of this license in the LICENSE.txt file in the root directory
-# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
-#
-# Any modifications or derivative works of this code must retain this
-# copyright notice, and modified files need to carry a notice indicating
-# that they have been altered from the originals.
-
-"""ASAP Scheduling."""
-
-from qiskit.circuit import Delay, Qubit, Measure
-from qiskit.dagcircuit import DAGCircuit
-from qiskit.transpiler.exceptions import TranspilerError
-from qiskit.transpiler.passes.scheduling.base_scheduler import BaseSchedulerTransform
-from qiskit.utils.deprecation import deprecate_func
-
-
-class ASAPSchedule(BaseSchedulerTransform):
-    """ASAP Scheduling pass, which schedules the start time of instructions as early as possible..
-
-    See :class:`~qiskit.transpiler.passes.scheduling.base_scheduler.BaseSchedulerTransform` for the
-    detailed behavior of the control flow operation, i.e. ``c_if``.
-
-    .. note::
-
-        This base class has been superseded by :class:`~.ASAPScheduleAnalysis` and
-        the new scheduling workflow. It will be deprecated and subsequently
-        removed in a future release.
-    """
-
-    @deprecate_func(
-        additional_msg=(
-            "Instead, use :class:`~.ASAPScheduleAnalysis`, which is an "
-            "analysis pass that requires a padding pass to later modify the circuit."
-        ),
-        since="1.1.0",
-    )
-    def __init__(self, *args, **kwargs):
-        super().__init__(*args, **kwargs)
-
-    def run(self, dag):
-        """Run the ASAPSchedule pass on `dag`.
-
-        Args:
-            dag (DAGCircuit): DAG to schedule.
-
-        Returns:
-            DAGCircuit: A scheduled DAG.
-
-        Raises:
-            TranspilerError: if the circuit is not mapped on physical qubits.
-            TranspilerError: if conditional bit is added to non-supported instruction.
-        """
-        if len(dag.qregs) != 1 or dag.qregs.get("q", None) is None:
-            raise TranspilerError("ASAP schedule runs on physical circuits only")
-
-        time_unit = self.property_set["time_unit"]
-
-        new_dag = DAGCircuit()
-        for qreg in dag.qregs.values():
-            new_dag.add_qreg(qreg)
-        for creg in dag.cregs.values():
-            new_dag.add_creg(creg)
-
-        idle_after = {q: 0 for q in dag.qubits + dag.clbits}
-        for node in dag.topological_op_nodes():
-            op_duration = self._get_node_duration(node, dag)
-
-            # compute t0, t1: instruction interval, note that
-            # t0: start time of instruction
-            # t1: end time of instruction
-            if isinstance(node.op, self.CONDITIONAL_SUPPORTED):
-                t0q = max(idle_after[q] for q in node.qargs)
-                if node.op.condition_bits:
-                    # conditional is bit tricky due to conditional_latency
-                    t0c = max(idle_after[bit] for bit in node.op.condition_bits)
-                    if t0q > t0c:
-                        # This is situation something like below
-                        #
-                        #           |t0q
-                        # Q ▒▒▒▒▒▒▒▒▒░░
-                        # C ▒▒▒░░░░░░░░
-                        #     |t0c
-                        #
-                        # In this case, you can insert readout access before tq0
-                        #
-                        #           |t0q
-                        # Q ▒▒▒▒▒▒▒▒▒▒▒
-                        # C ▒▒▒░░░▒▒░░░
-                        #         |t0q - conditional_latency
-                        #
-                        t0c = max(t0q - self.conditional_latency, t0c)
-                    t1c = t0c + self.conditional_latency
-                    for bit in node.op.condition_bits:
-                        # Lock clbit until state is read
-                        idle_after[bit] = t1c
-                    # It starts after register read access
-                    t0 = max(t0q, t1c)
-                else:
-                    t0 = t0q
-                t1 = t0 + op_duration
-            else:
-                if node.op.condition_bits:
-                    raise TranspilerError(
-                        f"Conditional instruction {node.op.name} is not supported in ASAP scheduler."
-                    )
-
-                if isinstance(node.op, Measure):
-                    # measure instruction handling is bit tricky due to clbit_write_latency
-                    t0q = max(idle_after[q] for q in node.qargs)
-                    t0c = max(idle_after[c] for c in node.cargs)
-                    # Assume following case (t0c > t0q)
-                    #
-                    #       |t0q
-                    # Q ▒▒▒▒░░░░░░░░░░░░
-                    # C ▒▒▒▒▒▒▒▒░░░░░░░░
-                    #           |t0c
-                    #
-                    # In this case, there is no actual clbit access until clbit_write_latency.
-                    # The node t0 can be push backward by this amount.
-                    #
-                    #         |t0q' = t0c - clbit_write_latency
-                    # Q ▒▒▒▒░░▒▒▒▒▒▒▒▒▒▒
-                    # C ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒
-                    #           |t0c' = t0c
-                    #
-                    # rather than naively doing
-                    #
-                    #           |t0q' = t0c
-                    # Q ▒▒▒▒░░░░▒▒▒▒▒▒▒▒
-                    # C ▒▒▒▒▒▒▒▒░░░▒▒▒▒▒
-                    #              |t0c' = t0c + clbit_write_latency
-                    #
-                    t0 = max(t0q, t0c - self.clbit_write_latency)
-                    t1 = t0 + op_duration
-                    for clbit in node.cargs:
-                        idle_after[clbit] = t1
-                else:
-                    # It happens to be directives such as barrier
-                    t0 = max(idle_after[bit] for bit in node.qargs + node.cargs)
-                    t1 = t0 + op_duration
-
-            # Add delay to qubit wire
-            for bit in node.qargs:
-                delta = t0 - idle_after[bit]
-                if (
-                    delta > 0
-                    and isinstance(bit, Qubit)
-                    and self._delay_supported(dag.find_bit(bit).index)
-                ):
-                    new_dag.apply_operation_back(Delay(delta, time_unit), [bit], [])
-                idle_after[bit] = t1
-
-            new_dag.apply_operation_back(node.op, node.qargs, node.cargs)
-
-        circuit_duration = max(idle_after.values())
-        for bit, after in idle_after.items():
-            delta = circuit_duration - after
-            if not (delta > 0 and isinstance(bit, Qubit)):
-                continue
-            if self._delay_supported(dag.find_bit(bit).index):
-                new_dag.apply_operation_back(Delay(delta, time_unit), [bit], [])
-
-        new_dag.name = dag.name
-        new_dag.metadata = dag.metadata
-        new_dag._calibrations_prop = dag._calibrations_prop
-
-        # set circuit duration and unit to indicate it is scheduled
-        new_dag.duration = circuit_duration
-        new_dag.unit = time_unit
-        return new_dag