qiskit 1.4.1__cp39-abi3-win_amd64.whl → 2.0.0rc1__cp39-abi3-win_amd64.whl

qiskit/synthesis/one_qubit/one_qubit_decompose.py

@@ -19,7 +19,7 @@ import numpy as np
 
 from qiskit._accelerate import euler_one_qubit_decomposer
 from qiskit.circuit.quantumcircuit import QuantumCircuit
-from qiskit.circuit.quantumregister import Qubit
+from qiskit.circuit import Qubit
 from qiskit.circuit.library.standard_gates import (
     UGate,
     PhaseGate,

qiskit/synthesis/two_qubit/__init__.py

@@ -16,4 +16,5 @@ from .two_qubit_decompose import (
     TwoQubitBasisDecomposer,
     two_qubit_cnot_decompose,
     TwoQubitWeylDecomposition,
+    TwoQubitControlledUDecomposer,
 )

qiskit/synthesis/two_qubit/two_qubit_decompose.py

@@ -51,7 +51,6 @@ from qiskit.circuit.library.standard_gates import (
 from qiskit.exceptions import QiskitError
 from qiskit.quantum_info.operators import Operator
 from qiskit.synthesis.one_qubit.one_qubit_decompose import (
-    OneQubitEulerDecomposer,
     DEFAULT_ATOL,
 )
 from qiskit.utils.deprecation import deprecate_func
@@ -271,168 +270,51 @@ class TwoQubitControlledUDecomposer:
     :math:`U \sim U_d(\alpha, 0, 0) \sim \text{Ctrl-U}`
     gate that is locally equivalent to an :class:`.RXXGate`."""
 
-    def __init__(self, rxx_equivalent_gate: Type[Gate]):
+    def __init__(self, rxx_equivalent_gate: Type[Gate], euler_basis: str = "ZXZ"):
         r"""Initialize the KAK decomposition.
 
         Args:
             rxx_equivalent_gate: Gate that is locally equivalent to an :class:`.RXXGate`:
-            :math:`U \sim U_d(\alpha, 0, 0) \sim \text{Ctrl-U}` gate.
+                :math:`U \sim U_d(\alpha, 0, 0) \sim \text{Ctrl-U}` gate.
+                Valid options are [:class:`.RZZGate`, :class:`.RXXGate`, :class:`.RYYGate`,
+                :class:`.RZXGate`, :class:`.CPhaseGate`, :class:`.CRXGate`, :class:`.CRYGate`,
+                :class:`.CRZGate`].
+            euler_basis: Basis string to be provided to :class:`.OneQubitEulerDecomposer`
+                for 1Q synthesis.
+                Valid options are [``'ZXZ'``, ``'ZYZ'``, ``'XYX'``, ``'XZX'``, ``'U'``, ``'U3'``,
+                ``'U321'``, ``'U1X'``, ``'PSX'``, ``'ZSX'``, ``'ZSXX'``, ``'RR'``].
+
         Raises:
             QiskitError: If the gate is not locally equivalent to an :class:`.RXXGate`.
         """
-        atol = DEFAULT_ATOL
-
-        scales, test_angles, scale = [], [0.2, 0.3, np.pi / 2], None
-
-        for test_angle in test_angles:
-            # Check that gate takes a single angle parameter
-            try:
-                rxx_equivalent_gate(test_angle, label="foo")
-            except TypeError as _:
-                raise QiskitError("Equivalent gate needs to take exactly 1 angle parameter.") from _
-            decomp = TwoQubitWeylDecomposition(rxx_equivalent_gate(test_angle))
-
-            circ = QuantumCircuit(2)
-            circ.rxx(test_angle, 0, 1)
-            decomposer_rxx = TwoQubitWeylDecomposition(
-                Operator(circ).data,
-                fidelity=None,
-                _specialization=two_qubit_decompose.Specialization.ControlledEquiv,
-            )
-
-            circ = QuantumCircuit(2)
-            circ.append(rxx_equivalent_gate(test_angle), qargs=[0, 1])
-            decomposer_equiv = TwoQubitWeylDecomposition(
-                Operator(circ).data,
-                fidelity=None,
-                _specialization=two_qubit_decompose.Specialization.ControlledEquiv,
+        if rxx_equivalent_gate._standard_gate is not None:
+            self._inner_decomposer = two_qubit_decompose.TwoQubitControlledUDecomposer(
+                rxx_equivalent_gate._standard_gate, euler_basis
             )
-
-            scale = decomposer_rxx.a / decomposer_equiv.a
-
-            if abs(decomp.a * 2 - test_angle / scale) > atol:
-                raise QiskitError(
-                    f"{rxx_equivalent_gate.__name__} is not equivalent to an RXXGate."
-                )
-
-            scales.append(scale)
-
-        # Check that all three tested angles give the same scale
-        if not np.allclose(scales, [scale] * len(test_angles)):
-            raise QiskitError(
-                f"Cannot initialize {self.__class__.__name__}: with gate {rxx_equivalent_gate}. "
-                "Inconsistent scaling parameters in checks."
+            self.gate_name = rxx_equivalent_gate._standard_gate.name
+        else:
+            self._inner_decomposer = two_qubit_decompose.TwoQubitControlledUDecomposer(
+                rxx_equivalent_gate, euler_basis
             )
-
-        self.scale = scales[0]
-
         self.rxx_equivalent_gate = rxx_equivalent_gate
+        self.scale = self._inner_decomposer.scale
+        self.euler_basis = euler_basis
 
-    def __call__(self, unitary, *, atol=DEFAULT_ATOL) -> QuantumCircuit:
+    def __call__(
+        self, unitary: Operator | np.ndarray, approximate=False, use_dag=False, *, atol=DEFAULT_ATOL
+    ) -> QuantumCircuit:
         """Returns the Weyl decomposition in circuit form.
 
-        Note: atol ist passed to OneQubitEulerDecomposer.
-        """
-
-        # pylint: disable=attribute-defined-outside-init
-        self.decomposer = TwoQubitWeylDecomposition(unitary)
-
-        oneq_decompose = OneQubitEulerDecomposer("ZYZ")
-        c1l, c1r, c2l, c2r = (
-            oneq_decompose(k, atol=atol)
-            for k in (
-                self.decomposer.K1l,
-                self.decomposer.K1r,
-                self.decomposer.K2l,
-                self.decomposer.K2r,
-            )
-        )
-        circ = QuantumCircuit(2, global_phase=self.decomposer.global_phase)
-        circ.compose(c2r, [0], inplace=True)
-        circ.compose(c2l, [1], inplace=True)
-        self._weyl_gate(circ)
-        circ.compose(c1r, [0], inplace=True)
-        circ.compose(c1l, [1], inplace=True)
-        return circ
-
-    def _to_rxx_gate(self, angle: float) -> QuantumCircuit:
-        """
-        Takes an angle and returns the circuit equivalent to an RXXGate with the
-        RXX equivalent gate as the two-qubit unitary.
-
         Args:
-            angle: Rotation angle (in this case one of the Weyl parameters a, b, or c)
+            unitary (Operator or ndarray): :math:`4 \times 4` unitary to synthesize.
 
         Returns:
-            Circuit: Circuit equivalent to an RXXGate.
+            QuantumCircuit: Synthesized quantum circuit.
 
-        Raises:
-            QiskitError: If the circuit is not equivalent to an RXXGate.
+        Note: atol is passed to OneQubitEulerDecomposer.
         """
-
-        # The user-provided RXXGate equivalent gate may be locally equivalent to the RXXGate
-        # but with some scaling in the rotation angle. For example, RXXGate(angle) has Weyl
-        # parameters (angle, 0, 0) for angle in [0, pi/2] but the user provided gate, i.e.
-        # :code:`self.rxx_equivalent_gate(angle)` might produce the Weyl parameters
-        # (scale * angle, 0, 0) where scale != 1. This is the case for the CPhaseGate.
-
-        circ = QuantumCircuit(2)
-        circ.append(self.rxx_equivalent_gate(self.scale * angle), qargs=[0, 1])
-        decomposer_inv = TwoQubitWeylDecomposition(Operator(circ).data)
-
-        oneq_decompose = OneQubitEulerDecomposer("ZYZ")
-
-        # Express the RXXGate in terms of the user-provided RXXGate equivalent gate.
-        rxx_circ = QuantumCircuit(2, global_phase=-decomposer_inv.global_phase)
-        rxx_circ.compose(oneq_decompose(decomposer_inv.K2r).inverse(), inplace=True, qubits=[0])
-        rxx_circ.compose(oneq_decompose(decomposer_inv.K2l).inverse(), inplace=True, qubits=[1])
-        rxx_circ.compose(circ, inplace=True)
-        rxx_circ.compose(oneq_decompose(decomposer_inv.K1r).inverse(), inplace=True, qubits=[0])
-        rxx_circ.compose(oneq_decompose(decomposer_inv.K1l).inverse(), inplace=True, qubits=[1])
-
-        return rxx_circ
-
-    def _weyl_gate(self, circ: QuantumCircuit, atol=1.0e-13):
-        """Appends U_d(a, b, c) to the circuit."""
-
-        circ_rxx = self._to_rxx_gate(-2 * self.decomposer.a)
-        circ.compose(circ_rxx, inplace=True)
-
-        # translate the RYYGate(b) into a circuit based on the desired Ctrl-U gate.
-        if abs(self.decomposer.b) > atol:
-            circ_ryy = QuantumCircuit(2)
-            circ_ryy.sdg(0)
-            circ_ryy.sdg(1)
-            circ_ryy.compose(self._to_rxx_gate(-2 * self.decomposer.b), inplace=True)
-            circ_ryy.s(0)
-            circ_ryy.s(1)
-            circ.compose(circ_ryy, inplace=True)
-
-        # translate the RZZGate(c) into a circuit based on the desired Ctrl-U gate.
-        if abs(self.decomposer.c) > atol:
-            # Since the Weyl chamber is here defined as a > b > |c| we may have
-            # negative c. This will cause issues in _to_rxx_gate
-            # as TwoQubitWeylControlledEquiv will map (c, 0, 0) to (|c|, 0, 0).
-            # We therefore produce RZZGate(|c|) and append its inverse to the
-            # circuit if c < 0.
-            gamma, invert = -2 * self.decomposer.c, False
-            if gamma > 0:
-                gamma *= -1
-                invert = True
-
-            circ_rzz = QuantumCircuit(2)
-            circ_rzz.h(0)
-            circ_rzz.h(1)
-            circ_rzz.compose(self._to_rxx_gate(gamma), inplace=True)
-            circ_rzz.h(0)
-            circ_rzz.h(1)
-
-            if invert:
-                circ.compose(circ_rzz.inverse(), inplace=True)
-            else:
-                circ.compose(circ_rzz, inplace=True)
-
-        return circ
+        circ_data = self._inner_decomposer(np.asarray(unitary, dtype=complex), atol)
+        return QuantumCircuit._from_circuit_data(circ_data, add_regs=True)
 
 
 class TwoQubitBasisDecomposer:
@@ -472,6 +354,7 @@ class TwoQubitBasisDecomposer:
             gate_name = "cx"
         else:
             gate_name = "USER_GATE"
+        self.gate_name = gate_name
 
         self._inner_decomposer = two_qubit_decompose.TwoQubitBasisDecomposer(
             gate_name,

qiskit/transpiler/__init__.py

@@ -187,7 +187,9 @@ For example, if you wanted to run a custom scheduling stage using dynamical deco
 :class:`~.PadDynamicalDecoupling` pass) and also add initial logical optimization prior to routing,
 you would do something like the following (building off the previous example):
 
-.. code-block:: python
+.. plot::
+   :include-source:
+   :nofigs:
 
     import numpy as np
     from qiskit.providers.fake_provider import GenericBackendV2
@@ -195,7 +197,6 @@ you would do something like the following (building off the previous example):
     from qiskit.transpiler import PassManager, generate_preset_pass_manager
     from qiskit.transpiler.passes import (
         ALAPScheduleAnalysis,
-        CXCancellation,
         InverseCancellation,
         PadDynamicalDecoupling,
     )
@@ -504,6 +505,9 @@ is ``qiskit.transpiler.routing``.  The built-in plugins are:
     * - Method
       - Summary
 
+    * - :ref:`default <transpiler-preset-stage-routing-default>`
+      - Use a Qiskit-chosen default routing method.
+
     * - :ref:`sabre <transpiler-preset-stage-routing-sabre>`
       - Default.  Uses `Qiskit's modified Sabre routing algorithm <sabre-lightsabre-paper_>`_ to
         swap map.
@@ -514,13 +518,19 @@ is ``qiskit.transpiler.routing``.  The built-in plugins are:
     * - :ref:`basic <transpiler-preset-stage-routing-basic>`
       - Greedy swap insertion to route a single operation at a time.
 
-    * - :ref:`stochastic <transpiler-preset-stage-routing-stochastic>`
-      - Consider operations layer-by-layer, using a stochastic algorithm to find swap networks that
-        implement a suitable permutation to make the layer executable.
-
     * - :ref:`lookahead <transpiler-preset-stage-routing-lookahead>`
       - Breadth-first search with heuristic pruning to find swaps that make gates executable.
 
+.. _transpiler-preset-stage-routing-default:
+
+Built-in ``default`` plugin
+...........................
+
+Use a Qiskit-chosen default method for routing.  As of Qiskit 2.0, the chosen algorithm is the same
+as :ref:`transpiler-preset-stage-routing-sabre`, though in practice, usually the :ref:`built-in
+default layout-stage plugin <transpiler-preset-stage-layout-default>` will run the Sabre-based
+routing algorithm, and the routing stage will only be used to run :class:`.VF2PostLayout`.
+
 .. _transpiler-preset-stage-routing-none:
 
 Built-in ``none`` plugin
@@ -543,25 +553,6 @@ attempt to improve the initial layout after routing.
 
 This method typically has poor output quality.
 
-.. _transpiler-preset-stage-routing-stochastic:
-
-Built-in ``stochastic`` plugin
-..............................
-
-.. deprecated:: 1.3
-    Use :ref:`transpiler-preset-stage-routing-sabre` instead.
-
-Uses the :class:`.StochasticSwap` algorithm to route.  In short, this stratifies the circuit into
-layers, then uses a stochastic algorithm to find a permutation that will allow the layer to execute,
-and a series of swaps that will implement that permutation in a hardware-valid way.
-
-The optimization level affects the number of stochastic trials used for each layer, and the amount
-of work spent in :class:`.VF2PostLayout` to optimize the initial layout.
-
-This was Qiskit's primary routing algorithm for several years, until approximately 2021.  Now, it
-is reliably beaten in runtime and output quality by :ref:`Qiskit's custom Sabre-based routing
-algorithm <transpiler-preset-stage-routing-sabre>`.
-
 .. _transpiler-preset-stage-routing-lookahead:
 
 Built-in ``lookahead`` plugin
@@ -614,15 +605,6 @@ supported by the target ISA.  For example, if a ``cx`` is requested on hardware
 the ISA only contains a ``cz`` operation on those qubits, the translation stage must find a way of
 representing the ``cx`` gate using the ``cz`` and available one-qubit gates.
 
-.. note::
-
-    In Qiskit 1.x, translation plugins need not output gates with the correct
-    directionality, provided the gate exists with opposite directionality on the given qubit pair.
-    For example, if ``cx(0, 1)`` is ISA-supported, the translation stage can output
-    ``cx(1, 0)``.
-
-    This is likely to change in later versions of Qiskit.
-
 The translation stage is called before entering the optimization stage. Optimization plugins
 (including Qiskit's built-in plugins) may also use the translation stage as a "fixup" stage after
 the optimization loop, if the optimization loop returns a circuit that includes non-ISA gates.  This
@@ -642,6 +624,9 @@ When writing :ref:`stage plugins <transpiler-preset-stage-plugins>`, the entry p
     * - Method
       - Summary
 
+    * - :ref:`default <transpiler-preset-stage-translation-translator>`
+      - Use a Qiskit-chosen default translation method.
+
     * - :ref:`translator <transpiler-preset-stage-translation-translator>`
       - Symbolic translation of gates to the target basis using known equivalences.
 
@@ -649,6 +634,15 @@ When writing :ref:`stage plugins <transpiler-preset-stage-plugins>`, the entry p
       - Collect each run of one- and two-qubit gates into a matrix representation, and resynthesize
         from there.
 
+.. _transpiler-preset-stage-translation-default:
+
+Built-in ``default`` plugin
+...........................
+
+Use a Qiskit-chosen default method for translation.  As of Qiskit 2.0, this is the same as
+:ref:`transpiler-preset-stage-translation-translator`, but the chosen algorithm might change during
+the 2.x series, either for all targets, or only for certain classes of target.
+
 .. _transpiler-preset-stage-translation-synthesis:
 
 Built-in ``synthesis`` plugin
@@ -873,7 +867,9 @@ The specific information needed by the transpiler is described by the
 For example, to construct a simple :class:`~.Target` object, one can iteratively add
 descriptions of the instructions it supports:
 
-.. code-block::
+.. plot::
+   :include-source:
+   :nofigs:
 
     from qiskit.circuit import Parameter, Measure
     from qiskit.transpiler import Target, InstructionProperties
@@ -1238,7 +1234,7 @@ also look at it with the :func:`.timeline.draw` function:
 
    circ = transpile(ghz, backend, scheduling_method="asap")
 
-   timeline_draw(circ)
+   timeline_draw(circ, target=backend.target)
 
 The scheduling of a circuit involves two parts: analysis and constraint mapping, followed by a
 padding pass. The first part requires running a scheduling analysis pass such as
@@ -1254,202 +1250,6 @@ the scheduling and adjustments/rescheduling are finished, a padding pass,
 such as :class:`~.PadDelay` or :class:`~.PadDynamicalDecoupling` is run
 to insert the instructions into the circuit, which completes the scheduling.
 
-Scheduling analysis with control-flow instructions
---------------------------------------------------
-
-When running scheduling analysis passes on a circuit, you must keep in mind that there
-are additional constraints on classical conditions and control flow instructions. This section
-covers the details of these additional
-constraints that any scheduling pass will need to account for.
-
-Topological node ordering in scheduling
-.......................................
-
-The DAG representation of ``QuantumCircuit`` respects the node ordering in the
-classical register wires, though theoretically two conditional instructions
-conditioned on the same register could commute, i.e. read-access to the
-classical register doesn't change its state.
-
-.. code-block:: text
-
-    qc = QuantumCircuit(2, 1)
-    qc.delay(100, 0)
-    qc.x(0).c_if(0, True)
-    qc.x(1).c_if(0, True)
-
-The scheduler SHOULD comply with the above topological ordering policy of the
-DAG circuit.
-Accordingly, the `asap`-scheduled circuit will become
-
-.. code-block:: text
-
-         ┌────────────────┐   ┌───┐
-    q_0: ┤ Delay(100[dt]) ├───┤ X ├──────────────
-         ├────────────────┤   └─╥─┘      ┌───┐
-    q_1: ┤ Delay(100[dt]) ├─────╫────────┤ X ├───
-         └────────────────┘     ║        └─╥─┘
-                           ┌────╨────┐┌────╨────┐
-    c: 1/══════════════════╡ c_0=0x1 ╞╡ c_0=0x1 ╞
-                           └─────────┘└─────────┘
-
-Note that this scheduling might be inefficient in some cases,
-because the second conditional operation could start without waiting
-for the 100 dt delay.
-However, any additional optimization should be done in a different pass,
-not to break the topological ordering of the original circuit.
-
-Realistic control flow scheduling (respecting microarchitecture)
-................................................................
-
-In the dispersive QND readout scheme, the qubit (Q) is measured by sending
-a microwave stimulus, followed by a resonator ring-down (depopulation). This
-microwave signal is recorded in the buffer memory (B) with the hardware kernel,
-then a discriminated (D) binary value is moved to the classical register (C).
-A sequence from t0 to t1 of the measure instruction interval could be
-modeled as follows:
-
-.. code-block:: text
-
-    Q ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-    B ░░▒▒▒▒▒▒▒▒░░░░░░░░░
-    D ░░░░░░░░░░▒▒▒▒▒▒░░░
-    C ░░░░░░░░░░░░░░░░▒▒░
-
-However, the :class:`.QuantumCircuit` representation is not accurate enough to represent
-this model. In the circuit representation, the corresponding :class:`.circuit.Qubit` is occupied
-by the stimulus microwave signal during the first half of the interval,
-and the :class:`.Clbit` is only occupied at the very end of the interval.
-
-The lack of precision representing the physical model may induce
-edge cases in the scheduling:
-
-.. code-block:: text
-
-            ┌───┐
-    q_0: ───┤ X ├──────
-            └─╥─┘   ┌─┐
-    q_1: ─────╫─────┤M├
-         ┌────╨────┐└╥┘
-    c: 1/╡ c_0=0x1 ╞═╩═
-         └─────────┘ 0
-
-In this example, a user may intend to measure the state of ``q_1`` after the
-:class:`.XGate` is applied to ``q_0``. This is the correct interpretation from
-the viewpoint of topological node ordering, i.e. The :class:`.XGate` node comes in
-front of the :class:`.Measure` node.
-However, according to the measurement model above, the data in the register
-is unchanged during the application of the stimulus, so two nodes are
-simultaneously operated.
-If one tries to `alap`-schedule this circuit, it may return following circuit:
-
-.. code-block:: text
-
-         ┌────────────────┐   ┌───┐
-    q_0: ┤ Delay(500[dt]) ├───┤ X ├──────
-         └────────────────┘   └─╥─┘   ┌─┐
-    q_1: ───────────────────────╫─────┤M├
-                           ┌────╨────┐└╥┘
-    c: 1/══════════════════╡ c_0=0x1 ╞═╩═
-                           └─────────┘ 0
-
-Note that there is no delay on the ``q_1`` wire, and the measure instruction
-immediately starts after t=0, while the conditional gate starts after the delay.
-It looks like the topological ordering between the nodes is flipped in the
-scheduled view.
-This behavior can be understood by considering the control flow model described above,
-
-.. code-block:: text
-
-    : Quantum Circuit, first-measure
-    0 ░░░░░░░░░░░░▒▒▒▒▒▒░
-    1 ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-
-    : In wire q0
-    Q ░░░░░░░░░░░░░░░▒▒▒░
-    C ░░░░░░░░░░░░▒▒░░░░░
-
-    : In wire q1
-    Q ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-    B ░░▒▒▒▒▒▒▒▒░░░░░░░░░
-    D ░░░░░░░░░░▒▒▒▒▒▒░░░
-    C ░░░░░░░░░░░░░░░░▒▒░
-
-Since there is no qubit register overlap between Q0 and Q1, the node ordering is
-determined by the shared classical register C. As you can see, the execution order is still
-preserved on C, i.e. read C then apply ``XGate``, finally store the measured outcome in C.
-But because ``DAGOpNode`` cannot define different durations for the associated registers,
-the time ordering of the two nodes is inverted.
-
-This behavior can be controlled by ``clbit_write_latency`` and ``conditional_latency``.
-``clbit_write_latency`` determines the delay of the register write-access from
-the beginning of the measure instruction (t0), while ``conditional_latency`` determines
-the delay of conditional gate operations with respect to t0, which is determined
-by the register read-access.
-This information is accessible in the backend configuration and should
-be copied to the pass manager property set before the pass is called.
-
-Due to default latencies, the `alap`-scheduled circuit of above example may become
-
-.. code-block:: text
-
-            ┌───┐
-    q_0: ───┤ X ├──────
-            └─╥─┘   ┌─┐
-    q_1: ─────╫─────┤M├
-         ┌────╨────┐└╥┘
-    c: 1/╡ c_0=0x1 ╞═╩═
-         └─────────┘ 0
-
-If the backend microarchitecture supports smart scheduling of the control flow
-instructions, such as separately scheduling qubits and classical registers,
-the insertion of the delay yields an unnecessarily longer total execution time.
-
-.. code-block:: text
-
-    : Quantum Circuit, first-XGate
-    0 ░▒▒▒░░░░░░░░░░░░░░░
-    1 ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-
-    : In wire q0
-    Q ░▒▒▒░░░░░░░░░░░░░░░
-    C ░░░░░░░░░░░░░░░░░░░ (zero latency)
-
-    : In wire q1
-    Q ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-    C ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░ (zero latency, scheduled after C0 read-access)
-
-However, this result is much more intuitive in the topological ordering view.
-If a finite conditional latency value is provided, for example, 30 dt, the circuit
-is scheduled as follows:
-
-.. code-block:: text
-
-         ┌───────────────┐   ┌───┐
-    q_0: ┤ Delay(30[dt]) ├───┤ X ├──────
-         ├───────────────┤   └─╥─┘   ┌─┐
-    q_1: ┤ Delay(30[dt]) ├─────╫─────┤M├
-         └───────────────┘┌────╨────┐└╥┘
-    c: 1/═════════════════╡ c_0=0x1 ╞═╩═
-                          └─────────┘ 0
-
-with the timing model:
-
-.. code-block:: text
-
-    : Quantum Circuit, first-xgate
-    0 ░░▒▒▒░░░░░░░░░░░░░░░
-    1 ░░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-
-    : In wire q0
-    Q ░░▒▒▒░░░░░░░░░░░░░░░
-    C ░▒░░░░░░░░░░░░░░░░░░ (30dt latency)
-
-    : In wire q1
-    Q ░░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-    C ░░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
-
-See https://arxiv.org/abs/2102.01682 for more details.
-
 Transpiler API
 ==============
 

qiskit/transpiler/basepasses.py

@@ -19,13 +19,11 @@ from collections.abc import Callable, Hashable, Iterable
 from inspect import signature
 
 from qiskit.circuit import QuantumCircuit
-from qiskit.converters import circuit_to_dag, dag_to_circuit
 from qiskit.dagcircuit import DAGCircuit
 from qiskit.passmanager.base_tasks import GenericPass, PassManagerIR
 from qiskit.passmanager.compilation_status import PropertySet, RunState, PassManagerState
 
 from .exceptions import TranspilerError
-from .layout import TranspileLayout
 
 
 class MetaPass(abc.ABCMeta):
@@ -126,57 +124,31 @@ class BasePass(GenericPass, metaclass=MetaPass):
 
         Args:
             circuit: The dag on which the pass is run.
-            property_set: Input/output property set. An analysis pass
-                might change the property set in-place.
+            property_set: Input/output property set. An analysis pass might change the property set
+                in-place.  If not given, the existing ``property_set`` attribute of the pass will
+                be used (if set).
 
         Returns:
             If on transformation pass, the resulting QuantumCircuit.
             If analysis pass, the input circuit.
         """
-        property_set_ = None
-        if isinstance(property_set, dict):  # this includes (dict, PropertySet)
-            property_set_ = PropertySet(property_set)
-
-        if isinstance(property_set_, PropertySet):
-            # pylint: disable=attribute-defined-outside-init
-            self.property_set = property_set_
-
-        result = self.run(circuit_to_dag(circuit))
-
-        result_circuit = circuit
-
-        if isinstance(property_set, dict):  # this includes (dict, PropertySet)
+        from qiskit.transpiler import PassManager  # pylint: disable=cyclic-import
+
+        pm = PassManager([self])
+        # Previous versions of the `__call__` function would not construct a `PassManager`, but just
+        # call `self.run` directly (this caused issues with `requires`).  It only overrode
+        # `self.property_set` if the input was not `None`, which some users might have been relying
+        # on (as our test suite was).
+        if property_set is None:
+            property_set = self.property_set
+        out = pm.run(circuit, property_set=property_set)
+        if property_set is not None and property_set is not pm.property_set:
+            # When this `__call__` was first added, it contained this behaviour of mutating the
+            # input `property_set` in-place, but didn't use the `PassManager` infrastructure.  This
+            # preserves the output-variable nature of the `property_set` parameter.
             property_set.clear()
-            property_set.update(self.property_set)
-
-        if isinstance(result, DAGCircuit):
-            result_circuit = dag_to_circuit(result, copy_operations=False)
-        elif result is None:
-            result_circuit = circuit.copy()
-
-        if self.property_set["layout"]:
-            result_circuit._layout = TranspileLayout(
-                initial_layout=self.property_set["layout"],
-                input_qubit_mapping=self.property_set["original_qubit_indices"],
-                final_layout=self.property_set["final_layout"],
-                _input_qubit_count=len(circuit.qubits),
-                _output_qubit_list=result_circuit.qubits,
-            )
-        if self.property_set["clbit_write_latency"] is not None:
-            result_circuit._clbit_write_latency = self.property_set["clbit_write_latency"]
-        if self.property_set["conditional_latency"] is not None:
-            result_circuit._conditional_latency = self.property_set["conditional_latency"]
-        if self.property_set["node_start_time"]:
-            # This is dictionary keyed on the DAGOpNode, which is invalidated once
-            # dag is converted into circuit. So this schedule information is
-            # also converted into list with the same ordering with circuit.data.
-            topological_start_times = []
-            start_times = self.property_set["node_start_time"]
-            for dag_node in result.topological_op_nodes():
-                topological_start_times.append(start_times[dag_node])
-            result_circuit._op_start_times = topological_start_times
-
-        return result_circuit
+            property_set.update(pm.property_set)
+        return out
 
 
 class AnalysisPass(BasePass):  # pylint: disable=abstract-method
@@ -199,10 +171,7 @@ class TransformationPass(BasePass):  # pylint: disable=abstract-method
         )
 
         if state.workflow_status.previous_run == RunState.SUCCESS:
-            if isinstance(new_dag, DAGCircuit):
-                # Copy calibration data from the original program
-                new_dag._calibrations_prop = passmanager_ir._calibrations_prop
-            else:
+            if not isinstance(new_dag, DAGCircuit):
                 raise TranspilerError(
                     "Transformation passes should return a transformed dag."
                     f"The pass {self.__class__.__name__} is returning a {type(new_dag)}"