pyadi-jif 0.1.0__py2.py3-none-any.whl

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Files changed (73) hide show
  1. adijif/__init__.py +32 -0
  2. adijif/adijif.py +1 -0
  3. adijif/cli.py +21 -0
  4. adijif/clocks/__init__.py +10 -0
  5. adijif/clocks/ad9523.py +321 -0
  6. adijif/clocks/ad9523_1_bf.py +91 -0
  7. adijif/clocks/ad9528.py +444 -0
  8. adijif/clocks/ad9528_bf.py +70 -0
  9. adijif/clocks/ad9545.py +553 -0
  10. adijif/clocks/clock.py +153 -0
  11. adijif/clocks/hmc7044.py +558 -0
  12. adijif/clocks/hmc7044_bf.py +68 -0
  13. adijif/clocks/ltc6952.py +624 -0
  14. adijif/clocks/ltc6952_bf.py +67 -0
  15. adijif/clocks/ltc6953.py +509 -0
  16. adijif/common.py +70 -0
  17. adijif/converters/__init__.py +3 -0
  18. adijif/converters/ad9081.py +679 -0
  19. adijif/converters/ad9081_dp.py +206 -0
  20. adijif/converters/ad9081_util.py +124 -0
  21. adijif/converters/ad9084.py +588 -0
  22. adijif/converters/ad9084_dp.py +111 -0
  23. adijif/converters/ad9084_draw.py +203 -0
  24. adijif/converters/ad9084_util.py +365 -0
  25. adijif/converters/ad9144.py +316 -0
  26. adijif/converters/ad9144_bf.py +44 -0
  27. adijif/converters/ad9680.py +201 -0
  28. adijif/converters/ad9680_bf.py +43 -0
  29. adijif/converters/ad9680_draw.py +184 -0
  30. adijif/converters/adc.py +83 -0
  31. adijif/converters/adrv9009.py +426 -0
  32. adijif/converters/adrv9009_bf.py +43 -0
  33. adijif/converters/adrv9009_util.py +89 -0
  34. adijif/converters/converter.py +399 -0
  35. adijif/converters/dac.py +85 -0
  36. adijif/converters/resources/AD9084_JTX_JRX.xlsx +0 -0
  37. adijif/converters/resources/ad9081_JRx_204B.csv +180 -0
  38. adijif/converters/resources/ad9081_JRx_204C.csv +411 -0
  39. adijif/converters/resources/ad9081_JTx_204B.csv +1488 -0
  40. adijif/converters/resources/ad9081_JTx_204C.csv +1064 -0
  41. adijif/converters/resources/full_rx_mode_table_ad9081.csv +1904 -0
  42. adijif/converters/resources/full_tx_mode_table_ad9081.csv +994 -0
  43. adijif/d2/__init__.py +26 -0
  44. adijif/d2/d2lib.h +81 -0
  45. adijif/draw.py +498 -0
  46. adijif/fpgas/__init__.py +1 -0
  47. adijif/fpgas/fpga.py +64 -0
  48. adijif/fpgas/xilinx/__init__.py +1143 -0
  49. adijif/fpgas/xilinx/bf.py +101 -0
  50. adijif/fpgas/xilinx/pll.py +232 -0
  51. adijif/fpgas/xilinx/sevenseries.py +531 -0
  52. adijif/fpgas/xilinx/ultrascaleplus.py +485 -0
  53. adijif/fpgas/xilinx/xilinx_draw.py +516 -0
  54. adijif/gekko_trans.py +295 -0
  55. adijif/jesd.py +760 -0
  56. adijif/plls/__init__.py +3 -0
  57. adijif/plls/adf4030.py +259 -0
  58. adijif/plls/adf4371.py +419 -0
  59. adijif/plls/adf4382.py +581 -0
  60. adijif/plls/pll.py +103 -0
  61. adijif/solvers.py +54 -0
  62. adijif/sys/__init__.py +1 -0
  63. adijif/sys/s_plls.py +185 -0
  64. adijif/system.py +567 -0
  65. adijif/system_draw.py +65 -0
  66. adijif/types.py +151 -0
  67. adijif/utils.py +191 -0
  68. pyadi_jif-0.1.0.dist-info/METADATA +62 -0
  69. pyadi_jif-0.1.0.dist-info/RECORD +73 -0
  70. pyadi_jif-0.1.0.dist-info/WHEEL +6 -0
  71. pyadi_jif-0.1.0.dist-info/licenses/AUTHORS.rst +13 -0
  72. pyadi_jif-0.1.0.dist-info/licenses/LICENSE +277 -0
  73. pyadi_jif-0.1.0.dist-info/top_level.txt +1 -0
adijif/types.py ADDED
@@ -0,0 +1,151 @@
1
+ """ADI JIF utility types and functions."""
2
+
3
+ from typing import Dict, Union
4
+
5
+ import numpy as np
6
+
7
+ from adijif.solvers import GEKKO, CpoModel, integer_var # type: ignore
8
+
9
+
10
+ class range:
11
+ """Model range of possible values.
12
+
13
+ This class is similar to range but interfaces with
14
+ the modeling layers to create correct mappings for internal
15
+ solvers
16
+ """
17
+
18
+ def __init__(self, start: int, stop: int, step: int, name: str) -> None:
19
+ """Model range of possible values.
20
+
21
+ This class is similar to range but interfaces with
22
+ the modeling layers to create correct mappings for internal
23
+ solvers
24
+
25
+ Args:
26
+ start (int): Start value of range
27
+ stop (int): Last value of range-step
28
+ step (int): Difference between successive values in range
29
+ name (str): Name of variable
30
+ """
31
+ assert isinstance(start, int), "start must be an int"
32
+ assert isinstance(stop, int), "stop must be an int"
33
+ assert isinstance(step, int), "step must be an int"
34
+ assert isinstance(name, str), "name must be a string"
35
+
36
+ self.start = start
37
+ self.stop = stop
38
+ self.step = step
39
+ self.name = name
40
+
41
+ def __call__(self, model: Union[GEKKO, CpoModel]) -> Dict:
42
+ """Generate range for parameter solver.
43
+
44
+ Args:
45
+ model (GEKKO, CpoModel): Model of JESD system or part to solve
46
+
47
+ Returns:
48
+ Dict: Dictionary of solver variable(s) for model
49
+ """
50
+ if GEKKO and CpoModel:
51
+ assert isinstance(
52
+ model, (GEKKO, CpoModel)
53
+ ), "range must be called with input type model"
54
+ elif GEKKO:
55
+ assert isinstance(
56
+ model, GEKKO
57
+ ), "range must be called with input type model"
58
+ elif CpoModel:
59
+ assert isinstance(
60
+ model, CpoModel
61
+ ), "range must be called with input type model"
62
+
63
+ config = {}
64
+ if isinstance(model, CpoModel):
65
+ o_array = np.arange(self.start, self.stop, self.step)
66
+ config["range"] = integer_var(domain=o_array, name=self.name + "_Var")
67
+ return config
68
+
69
+ if self.step == 1:
70
+ config["range"] = model.Var(
71
+ integer=True,
72
+ lb=self.start,
73
+ ub=self.stop,
74
+ value=self.start,
75
+ name=self.name + "_Var",
76
+ )
77
+ else:
78
+ # Create piecewise problem with binary values (DO NOT USE SOS1!)
79
+ o_array = np.arange(self.start, self.stop, self.step)
80
+ o_array = list(map(int, o_array))
81
+
82
+ options = model.Array(model.Var, len(o_array), lb=0, ub=1, integer=True)
83
+ model.Equation(model.sum(options) == 1) # only select one
84
+ config["range"] = model.Intermediate(model.sum(o_array * options))
85
+
86
+ return config
87
+
88
+
89
+ class arb_source:
90
+ """Arbitrary source for solver.
91
+
92
+ This internally uses a division of two integers to create an arbitrary clock
93
+ source.
94
+ """
95
+
96
+ _max_scalar = int(1e11)
97
+
98
+ def __init__(self, name: str) -> None:
99
+ """Arbitrary source for solver.
100
+
101
+ Args:
102
+ name (str): Name of source
103
+ """
104
+ self.name = name
105
+
106
+ self._a = integer_var(0, self._max_scalar, name=name + "_a")
107
+ self._b = integer_var(0, self._max_scalar, name=name + "_b")
108
+
109
+ def __call__(self, model: Union[GEKKO, CpoModel]) -> Dict:
110
+ """Generate arbitrary source for solver.
111
+
112
+ Args:
113
+ model (GEKKO, CpoModel): Model of JESD system or part to solve
114
+
115
+ Returns:
116
+ Dict: Dictionary of solver variable(s) for model
117
+
118
+ Raises:
119
+ NotImplementedError: Only CpoModel is supported
120
+ """
121
+ if GEKKO and CpoModel:
122
+ assert isinstance(
123
+ model, (GEKKO, CpoModel)
124
+ ), "arb_source must be called with input type model"
125
+ elif GEKKO:
126
+ assert isinstance(
127
+ model, GEKKO
128
+ ), "arb_source must be called with input type model"
129
+ elif CpoModel:
130
+ assert isinstance(
131
+ model, CpoModel
132
+ ), "arb_source must be called with input type model"
133
+
134
+ # config = {}
135
+ if isinstance(model, CpoModel):
136
+ # config[self.name] = self._a / self._b
137
+ # return config
138
+ return self._a / self._b
139
+
140
+ raise NotImplementedError("Only CpoModel is supported")
141
+
142
+ def get_config(self, solution: Dict) -> Dict:
143
+ """Get configuration from solver results.
144
+
145
+ Args:
146
+ solution (Dict): Solver results
147
+
148
+ Returns:
149
+ Dict: Dictionary of solver variable(s) for model
150
+ """
151
+ return {self.name: solution[self._a] / solution[self._b]}
adijif/utils.py ADDED
@@ -0,0 +1,191 @@
1
+ """Collection of utility scripts for specialized checks."""
2
+
3
+ import copy
4
+ from typing import List, Optional
5
+
6
+ import numpy as np
7
+
8
+ import adijif.fpgas.xilinx.sevenseries as xp
9
+ import adijif.fpgas.xilinx.ultrascaleplus as us
10
+ from adijif.converters.converter import converter
11
+ from adijif.fpgas.fpga import fpga
12
+
13
+
14
+ def get_jesd_mode_from_params(conv: converter, **kwargs: int) -> List[dict]:
15
+ """Find the JESD mode that matches the supplied parameters.
16
+
17
+ Args:
18
+ conv (converter): Converter object of desired device
19
+ kwargs: Parameters and values to match against
20
+
21
+ Raises:
22
+ Exception: Converter does not have specified JESD property
23
+
24
+ Returns:
25
+ List[dict]: JESD mode that matches the supplied parameters
26
+ """
27
+ results = []
28
+ needed = len(kwargs.items())
29
+
30
+ # Remove JESD modes if not needed
31
+ if any([i == "jesd_class" for i in kwargs.items()]):
32
+ modes = conv.quick_configuration_modes[kwargs["jesd_class"]]
33
+ modes = {kwargs["jesd_class"]: modes}
34
+ else:
35
+ modes = conv.quick_configuration_modes
36
+
37
+ modes = copy.deepcopy(modes)
38
+
39
+ for standard in modes:
40
+ for mode in modes[standard]:
41
+ found = 0
42
+ settings = modes[standard][mode]
43
+ for key, value in kwargs.items():
44
+ if key not in settings:
45
+ raise Exception(f"{key} not in JESD Configs")
46
+ if isinstance(value, list):
47
+ for v in value:
48
+ if settings[key] == v:
49
+ found += 1
50
+ else:
51
+ if settings[key] == value:
52
+ found += 1
53
+ if found == needed:
54
+ results.append(
55
+ {"mode": mode, "jesd_class": standard, "settings": settings}
56
+ )
57
+
58
+ if not results:
59
+ raise Exception(f"No JESD mode found for {kwargs}")
60
+
61
+ return results
62
+
63
+
64
+ def get_max_sample_rates(
65
+ conv: converter, fpga: Optional[fpga] = None, limits: Optional[dict] = None
66
+ ) -> dict:
67
+ """Determine the maximum sample rates for the device.
68
+
69
+ Determine the maximum sample rate across all values of M (number of
70
+ virtual converters and supplied limits
71
+
72
+ Args:
73
+ conv (converter): Converter object of desired device
74
+ fpga (Optional[fpga]): FPGA object of desired fpga device
75
+ limits (Optional[dict]): Limits to apply to the device and JESD mode
76
+
77
+ Raises:
78
+ Exception: Converter does not have specified property
79
+ Exception: Numeric limits must be described in a nested dict
80
+ AttributeError: FPGA object does not have specified property
81
+
82
+ Returns:
83
+ dict: Dictionary of maximum sample rates per M
84
+ """
85
+ if fpga:
86
+ max_lanes = fpga.max_serdes_lanes
87
+ if int(fpga.transceiver_type[4]) == 2:
88
+ trx = xp.SevenSeries(parent=fpga, transceiver_type=fpga.transceiver_type)
89
+ max_lane_rate = trx.plls["QPLL"].vco_max
90
+ elif int(fpga.transceiver_type[4]) in [3, 4]:
91
+ trx = us.UltraScalePlus(parent=fpga, transceiver_type=fpga.transceiver_type)
92
+ max_lane_rate = trx.plls["QPLL"].vco_max * 2
93
+ else:
94
+ raise Exception("Unsupported FPGA transceiver type")
95
+ else:
96
+ max_lanes = None
97
+ max_lane_rate = None
98
+
99
+ if limits:
100
+ assert isinstance(limits, dict), "limits must be a dictionary"
101
+
102
+ results = []
103
+ # Loop across enabled channel counts
104
+ for channels in conv.M_available:
105
+ sample_rates = []
106
+ mode_vals = []
107
+ standards = []
108
+ modes = conv.quick_configuration_modes
109
+ # Cycle through all modes to determine
110
+ for standard in modes:
111
+ for mode in modes[standard]:
112
+ if modes[standard][mode]["M"] not in [channels]:
113
+ continue
114
+ # Set mode
115
+ conv.set_quick_configuration_mode(mode, standard)
116
+ if max_lanes:
117
+ if conv.L > max_lanes:
118
+ continue
119
+
120
+ # Set bit_clock
121
+ max_bit_clock = conv.bit_clock_max
122
+ if max_lane_rate:
123
+ max_bit_clock = min(max_lane_rate, max_bit_clock)
124
+
125
+ conv.sample_clock = conv.sample_clock_max
126
+ max_bit_clock_at_max_adc_rate = conv.bit_clock
127
+
128
+ # Update model with valid max so we can get true sample clock
129
+ conv.bit_clock = min(
130
+ max_bit_clock,
131
+ max_bit_clock_at_max_adc_rate,
132
+ )
133
+
134
+ # Apply extra checks
135
+ b = False
136
+ if limits:
137
+ for limit in limits:
138
+ if not hasattr(conv, limit):
139
+ raise AttributeError(
140
+ f"converter does not have property {limit}"
141
+ )
142
+ if isinstance(limits[limit], str):
143
+ if getattr(conv, limit) != limits[limit]:
144
+ b = True
145
+ break
146
+ elif isinstance(limits[limit], dict):
147
+ ld = limits[limit]
148
+ for lc in ld:
149
+ if lc in [">", "<", "<=", ">=", "=="]:
150
+ attr = getattr(conv, limit)
151
+ e = eval( # noqa: S307
152
+ f"{attr} {lc} {limits[limit][lc]}"
153
+ )
154
+ if not e:
155
+ b = True
156
+ break
157
+ if b:
158
+ break
159
+
160
+ else:
161
+ raise Exception(
162
+ "Numeric limits must be described in a nested dict"
163
+ )
164
+ if b:
165
+ continue
166
+
167
+ # Collect sample rate
168
+ sr = min(conv.sample_clock, conv.converter_clock_max)
169
+ sample_rates.append(sr)
170
+ mode_vals.append(mode)
171
+ standards.append(standard)
172
+
173
+ if not sample_rates:
174
+ continue
175
+
176
+ i = np.argmax(sample_rates)
177
+ mode = mode_vals[i]
178
+ standard = standards[i]
179
+ conv.set_quick_configuration_mode(mode, standard)
180
+ conv.sample_clock = sample_rates[i]
181
+ results.append(
182
+ {
183
+ "sample_clock": conv.sample_clock,
184
+ "bit_clock": conv.bit_clock,
185
+ "L": conv.L,
186
+ "M": conv.M,
187
+ "quick_configuration_mode": mode,
188
+ "jesd_class": standard,
189
+ }
190
+ )
191
+ return results
@@ -0,0 +1,62 @@
1
+ Metadata-Version: 2.4
2
+ Name: pyadi-jif
3
+ Version: 0.1.0
4
+ Summary: Python interface and configurator for ADI JESD Interface Framework
5
+ Author-email: "Travis F. Collins" <travis.collins@analog.com>
6
+ Maintainer: Analog Devices, Inc.
7
+ Maintainer-email: Travis Collins <travis.collins@analog.com>
8
+ License: EPL-2.0
9
+ Requires-Python: >=3.9
10
+ Description-Content-Type: text/markdown
11
+ License-File: LICENSE
12
+ License-File: AUTHORS.rst
13
+ Requires-Dist: numpy<2
14
+ Requires-Dist: openpyxl>=3.1.3
15
+ Requires-Dist: pandas[openpyxl]>=1.1.5
16
+ Provides-Extra: cplex
17
+ Requires-Dist: cplex; extra == "cplex"
18
+ Requires-Dist: docplex==2.24.231; extra == "cplex"
19
+ Provides-Extra: gekko
20
+ Requires-Dist: gekko; extra == "gekko"
21
+ Dynamic: license-file
22
+
23
+ # pyadi-jif: Python Configurator for ADI JESD204 Interface Framework (JIF)
24
+
25
+ A framework to simplify the use of JESD204 with Analog Devices, Inc. data converters and clock chips.
26
+
27
+ <p align="center">
28
+ <img src="doc/source/imgs/PyADI-JIF_logo.png" width="500" alt="PyADI-JIF Logo"> </br>
29
+ </p>
30
+
31
+ <p align="center">
32
+
33
+ <a href="https://opensource.org/licenses/">
34
+ <img src="https://img.shields.io/badge/License-EPL%20v2-blue.svg" alt="EPL v2.0>
35
+ </a>
36
+
37
+ <a href="https://github.com/analogdevicesinc/pyadi-jif/actions/workflows/tests.yml">
38
+ <img src="https://github.com/analogdevicesinc/pyadi-jif/actions/workflows/tests.yml/badge.svg" alt="Test Status">
39
+ </a>
40
+
41
+ <a href="https://codecov.io/gh/analogdevicesinc/pyadi-jif">
42
+ <img src="https://codecov.io/gh/analogdevicesinc/pyadi-jif/branch/main/graph/badge.svg?token=WVSRCSXFWL" alt="Coverage Status">
43
+ </a>
44
+ </p>
45
+
46
+ ## Installation
47
+
48
+ Install JIF with pip
49
+
50
+ ```bash
51
+ pip install --index-url https://test.pypi.org/simple/ pyadi-jif
52
+ ```
53
+
54
+
55
+ ## Documentation
56
+
57
+ [Documentation](https://analogdevicesinc.github.io/pyadi-jif/main/)
58
+
59
+
60
+ ## License
61
+
62
+ [EPL-2.0](https://www.eclipse.org/legal/epl-2.0/)
@@ -0,0 +1,73 @@
1
+ adijif/__init__.py,sha256=2JlAIBypC54oGJdn77NCrptFtxlF75n_7i4HFHt2Mq0,990
2
+ adijif/adijif.py,sha256=h0hwdogXGFqerm-5ZPeT-irPn91pCcQRjiHThXsRzEk,19
3
+ adijif/cli.py,sha256=HCW6Qtm6dVxeRQ0AiTm03FxGM4BFXQGF9lwz7QPagVg,480
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+ adijif/common.py,sha256=2L09c8DE3heEHLirD-sahfs3gllhgWRsVEjtaMu0wcg,2117
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+ adijif/draw.py,sha256=kwQTDzfgliVJhzKZwe5b7QPN9vrGZ99WoN54aQM8Fos,17185
6
+ adijif/gekko_trans.py,sha256=xe5FjEjgxwl3TGC_en_VNT7Wf3H1IqE5tehZr738hug,9435
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+ adijif/jesd.py,sha256=d9Rvg7erqkFh-4wB784QIOdwaex9596C5ihIVh_G_O8,21053
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+ adijif/solvers.py,sha256=gwifcsxh1jWLU-y4pKzpzucjOPUX_TVbisq6qIs22ns,1670
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+ adijif/system.py,sha256=qtnQK2gLEPHJ4iTov_HWlF-HdNQyv2zBJQjx20-hA6w,21711
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+ adijif/system_draw.py,sha256=Q8fpouIjtkJAD7a8BdRDI2vGU5b0RqCYNcHHEz4g2Wc,1837
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+ adijif/types.py,sha256=XkdHxfc_qUeU46JQVWo9esCoK6eOKfuY_2-pgSQG4Oc,4794
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+ adijif/utils.py,sha256=EZGsdX7JAFsfknmlUXyhc57PJA7QsaIlTqOUWt1vw24,6811
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+ adijif/clocks/__init__.py,sha256=5idFQgZfdY8emHPDex8d459kB_MbcEgE3BDKkKzzsGg,145
14
+ adijif/clocks/ad9523.py,sha256=wCBwmxe3c23-mMBUROhQ7ErQiZBDLvpDfr5lKQAkyCA,9687
15
+ adijif/clocks/ad9523_1_bf.py,sha256=Nj4DqVIYWNPDreQf8g-HqSV1xL8ff6TGqEcv-Zh7aTo,3707
16
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+ pyadi_jif-0.1.0.dist-info/RECORD,,
@@ -0,0 +1,6 @@
1
+ Wheel-Version: 1.0
2
+ Generator: setuptools (80.9.0)
3
+ Root-Is-Purelib: true
4
+ Tag: py2-none-any
5
+ Tag: py3-none-any
6
+
@@ -0,0 +1,13 @@
1
+ =======
2
+ Credits
3
+ =======
4
+
5
+ Development Lead
6
+ ----------------
7
+
8
+ * Travis F. Collins <travis.collins@analog.com>
9
+
10
+ Contributors
11
+ ------------
12
+
13
+ None yet. Why not be the first?