pyadi-jif 0.1.0__py2.py3-none-any.whl

adijif/converters/ad9680_draw.py

@@ -0,0 +1,184 @@
+"""Drawing features for AD9680."""
+
+from typing import Dict
+
+from adijif.draw import Layout, Node  # type: ignore # isort: skip  # noqa: I202
+
+
+class ad9680_draw:
+    """AD9680 drawing features."""
+
+    _system_draw = False
+    show_rates = True
+
+    def _init_diagram(self) -> None:
+        """Initialize diagram for AD9680 alone."""
+        self.ic_diagram_node = None
+        self._diagram_output_dividers = []
+
+        self.ic_diagram_node = Node("AD9680")
+
+        # External
+        # ref_in = Node("REF_IN", ntype="input")
+        # lo.add_node(ref_in)
+
+        crossbar = Node("Crossbar", ntype="crossbar")
+        self.ic_diagram_node.add_child(crossbar)
+        for adc in range(2):
+            adc_node = Node(f"ADC{adc}", ntype="adc")
+            self.ic_diagram_node.add_child(adc_node)
+            adc_node.shape = "parallelogram"
+            self.ic_diagram_node.add_connection(
+                {"from": adc_node, "to": crossbar, "type": "data"}
+            )
+
+        for ddc in range(4):
+            ddc_node = Node(f"DDC{ddc}", ntype="ddc")
+            self.ic_diagram_node.add_child(ddc_node)
+            self.ic_diagram_node.add_connection(
+                {"from": crossbar, "to": ddc_node, "type": "data"}
+            )
+
+        jesd204_framer = Node("JESD204 Framer", ntype="jesd204framer")
+        self.ic_diagram_node.add_child(jesd204_framer)
+
+        for ddc in range(4):
+            ddc = self.ic_diagram_node.get_child(f"DDC{ddc}")
+            self.ic_diagram_node.add_connection(
+                {"from": ddc, "to": jesd204_framer, "type": "data"}
+            )
+
+    def _update_diagram(self, config: Dict) -> None:
+        """Update diagram with configuration.
+
+        Args:
+            config (Dict): Configuration dictionary
+
+        Raises:
+            Exception: If key is not D followed by a number
+        """
+        # Add output dividers
+        keys = config.keys()
+        output_dividers = self.ic_diagram_node.get_child("Output Dividers")
+        for key in keys:
+            if key.startswith("D"):
+                div = Node(key, ntype="divider")
+                output_dividers.add_child(div)
+                self.ic_diagram_node.add_connection(
+                    {"from": output_dividers, "to": div}
+                )
+            else:
+                raise Exception(
+                    f"Unknown key {key}. Must be of for DX where X is a number"
+                )
+
+    def draw(
+        self, clocks: Dict, lo: Layout = None, clock_chip_node: Node = None
+    ) -> str:
+        """Draw diagram in d2 language for IC alone with reference clock.
+
+        Args:
+            clocks (Dict): Dictionary of clocks
+            lo (Layout): Layout object to add to. Defaults to None.
+            clock_chip_node (Node): Node to connect to. Defaults to None.
+
+        Returns:
+            str: Diagram in d2 language
+
+        Raises:
+            Exception: If no solution is saved
+        """
+        if not self._saved_solution:
+            raise Exception("No solution to draw. Must call solve first.")
+
+        system_draw = lo is not None
+
+        if not system_draw:
+            lo = Layout("AD9680 Example")
+            lo.show_rates = self.show_rates
+        else:
+            # Verify lo is a Layout object
+            assert isinstance(lo, Layout), "lo must be a Layout object"
+        lo.add_node(self.ic_diagram_node)
+
+        static_options = self.get_config()
+
+        if not system_draw:
+            ref_in = Node("REF_IN", ntype="input")
+            lo.add_node(ref_in)
+        else:
+            to_node = lo.get_node("AD9680_ref_clk")
+            # Locate node connected to this one
+            from_node = lo.get_connection(to=to_node.name)
+            assert from_node, "No connection found"
+            assert isinstance(from_node, list), "Connection must be a list"
+            assert len(from_node) == 1, "Only one connection allowed"
+            ref_in = from_node[0]["from"]
+            # Remove to_node since it is not needed
+            lo.remove_node(to_node.name)
+
+        for i in range(2):
+            adc = self.ic_diagram_node.get_child(f"ADC{i}")
+            lo.add_connection(
+                {"from": ref_in, "to": adc, "rate": clocks["AD9680_ref_clk"]}
+            )
+
+        # Update Node values
+        for ddc in range(4):
+            rate = clocks["AD9680_ref_clk"]
+            self.ic_diagram_node.update_connection("Crossbar", f"DDC{ddc}", rate)
+
+            ddc_node = self.ic_diagram_node.get_child(f"DDC{ddc}")
+            ddc_node.value = str(static_options["decimation"])
+            drate = rate / static_options["decimation"]
+
+            self.ic_diagram_node.update_connection(f"DDC{ddc}", "JESD204 Framer", drate)
+
+        # Connect clock to framer
+        if not system_draw:
+            sysref_in = Node("SYSREF_IN", ntype="input")
+
+            lo.add_connection(
+                {
+                    "from": sysref_in,
+                    "to": self.ic_diagram_node.get_child("JESD204 Framer"),
+                    "rate": clocks["AD9680_sysref"],
+                }
+            )
+        else:
+            to_node = lo.get_node("AD9680_sysref")
+            # Locate node connected to this one
+            from_node = lo.get_connection(to=to_node.name)
+            assert from_node, "No connection found"
+            assert isinstance(from_node, list), "Connection must be a list"
+            assert len(from_node) == 1, "Only one connection allowed"
+            sysref_in = from_node[0]["from"]
+            # Remove to_node since it is not needed
+            lo.remove_node(to_node.name)
+
+            lo.add_connection(
+                {
+                    "from": sysref_in,
+                    "to": self.ic_diagram_node.get_child("JESD204 Framer"),
+                    "rate": clocks["AD9680_sysref"],
+                }
+            )
+
+        # Connect Remote Deframer
+        remote_deframer = Node("JESD204 Deframer", ntype="deframer")
+        lo.add_node(remote_deframer)
+
+        # Add connect for each lane
+        for _ in range(self.L):
+            lane_rate = self.bit_clock
+            lo.add_connection(
+                {
+                    "from": self.ic_diagram_node.get_child("JESD204 Framer"),
+                    "to": remote_deframer,
+                    "rate": lane_rate,
+                    "type": "data",
+                }
+            )
+
+        if not system_draw:
+            return lo.draw()

adijif/converters/adc.py

@@ -0,0 +1,83 @@
+"""Converter base meta class for all converter clocking models."""
+
+from abc import ABCMeta, abstractmethod
+from typing import List, Union
+
+from adijif.converters.converter import converter
+
+
+class adc(converter, metaclass=ABCMeta):
+    """ADC base meta class used to enforce all ADC classes.
+
+    This class should be inherited from for all ADCs and transceivers.
+
+    """
+
+    def _check_valid_internal_configuration(self) -> None:
+        """Verify current internal clocking configuration for part is valid.
+
+        Raises:
+            Exception: Invalid clocking configuration
+        """
+        if self.decimation * self.sample_clock > self.converter_clock_max:
+            raise Exception(
+                "ADC rate too fast for configuration {}".format(
+                    self.decimation * self.sample_clock
+                )
+            )
+        if self.decimation * self.sample_clock < self.converter_clock_min:
+            raise Exception(
+                "ADC rate too slow for configuration {}".format(
+                    self.decimation * self.sample_clock
+                )
+            )
+
+    @property
+    @abstractmethod
+    def decimation_available(self) -> List[int]:
+        """Decimation settings available.
+
+        Must be a list or None
+
+        Raises:
+            NotImplementedError: If child classes do not implement method/property
+        """
+        raise NotImplementedError  # pragma: no cover
+
+    _decimation = 1
+
+    @property
+    def decimation(self) -> Union[int, float]:
+        """Decimation between DAC and JESD framer. If none device is not an ADC.
+
+        Generally a multiple of 2
+
+        Returns:
+            int: decimation value
+        """
+        return self._decimation
+
+    @decimation.setter
+    def decimation(self, value: int) -> None:
+        """Decimation between DAC and JESD framer. If none device is not an ADC.
+
+        Args:
+            value (int): decimation
+
+        Raises:
+            Exception: decimation not an integer or not in range
+        """
+        if int(value) != value:
+            raise Exception("decimation_available must be an integer")
+        if value not in self.decimation_available:
+            raise Exception("decimation_available not in range for device")
+        self._decimation = value
+
+    @property
+    def converter_clock(self) -> Union[int, float]:
+        """Get rate of converter in samples per second.
+
+        Returns:
+            float: converter clock rate in samples per second
+        """
+        return self.sample_clock * self.decimation

adijif/converters/adrv9009.py

@@ -0,0 +1,426 @@
+"""ADRV9009 transceiver clocking model."""
+
+from abc import ABCMeta
+from typing import Any, Dict, List, Union
+
+import numpy as np
+
+from adijif.converters.adrv9009_bf import adrv9009_bf
+
+from ..solvers import CpoModel  # type: ignore # noqa: I202,BLK100
+from ..solvers import GEKKO, CpoSolveResult
+from .adc import adc
+from .adrv9009_util import quick_configuration_modes_rx  # type: ignore
+from .adrv9009_util import _extra_jesd_check, quick_configuration_modes_tx
+from .converter import converter
+from .dac import dac
+
+# References
+# https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/103757/adrv9009-clock-configuration/308013#308013
+
+
+class adrv9009_core(converter, metaclass=ABCMeta):
+    """ADRV9009 transceiver clocking model.
+
+    This model manage the JESD configuration and input clock constraints.
+    External LO constraints are not modeled.
+
+    Clocking: ADRV9009 uses onboard PLLs to generate the JESD clocks
+
+        Lane Rate = I/Q Sample Rate * M * Np * (10 / 8) / L
+        Lane Rate = sample_clock * M * Np * (10 / 8) / L
+    """
+
+    device_clock_available = None  # FIXME
+    device_clock_ranges = None  # FIXME
+
+    name = "ADRV9009"
+
+    # JESD configurations
+    quick_configuration_modes = None  # FIXME
+    available_jesd_modes = ["jesd204b"]
+    M_available = [1, 2, 4]
+    L_available = [1, 2, 3, 4, 6, 8]
+    N_available = [12, 16]
+    Np_available = [12, 16, 24]
+    F_available = [1, 2, 3, 4, 8]
+    S_available = [1]  # FIXME?
+    K_available = [*np.arange(1, 32 + 1)]
+    CS_available = [0]
+    CF_available = [0]
+
+    # Clock constraints
+    converter_clock_min = 39.063e6 * 8
+    converter_clock_max = 12288e6
+
+    sample_clock_min = 39.063e6
+    sample_clock_max = 491520000
+
+    device_clock_min = 10e6
+    device_clock_max = 1e9
+
+    clocking_option_available = ["integrated_pll"]
+    _clocking_option = "integrated_pll"
+
+    # Divider ranges
+    input_clock_dividers_available = [1 / 2, 1, 2, 4, 8, 16]
+    input_clock_dividers_times2_available = [1, 2, 4, 8, 16, 32]
+
+    _lmfc_divisor_sysref_available = [*range(1, 20)]
+
+    # Unused
+    max_rx_sample_clock = 250e6
+    max_tx_sample_clock = 500e6
+    max_obs_sample_clock = 500e6
+
+    def _check_valid_internal_configuration(self) -> None:
+        # FIXME
+        pass
+
+    def get_required_clock_names(self) -> List[str]:
+        """Get list of strings of names of requested clocks.
+
+        This list of names is for the clocks defined by
+        get_required_clocks
+
+        Returns:
+            List[str]: List of strings of clock names mapped by get_required_clocks
+        """
+        return ["adrv9009_ref_clk", "adrv9009_sysref"]
+
+    def get_config(self, solution: CpoSolveResult = None) -> Dict:
+        """Extract configurations from solver results.
+
+        Collect internal converter configuration and output clock definitions
+        leading to connected devices (clock chips, FPGAs)
+
+        Args:
+            solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver
+
+        Returns:
+            Dict: Dictionary of clocking rates and dividers for configuration
+        """
+        if solution:
+            self.solution = solution
+        return {}
+
+
+class adrv9009_clock_common(adrv9009_core, adrv9009_bf):
+    """ADRV9009 class managing common singleton (Rx,Tx) methods."""
+
+    def _check_valid_jesd_mode(self) -> None:
+        """Verify current JESD configuration for part is valid."""
+        _extra_jesd_check(self)
+        return super()._check_valid_jesd_mode()
+
+    def get_config(self, solution: CpoSolveResult = None) -> Dict:
+        """Extract configurations from solver results.
+
+        Collect internal converter configuration and output clock definitions
+        leading to connected devices (clock chips, FPGAs)
+
+        Args:
+            solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver
+
+        Returns:
+            Dict: Dictionary of clocking rates and dividers for configuration
+        """
+        return {"clocking_option": self.clocking_option}
+
+    def _gekko_get_required_clocks(self) -> List[Dict]:
+        possible_sysrefs = []
+        for n in range(1, 20):
+            r = self.multiframe_clock / (n * n)
+            if r == int(r):
+                possible_sysrefs.append(r)
+
+        self.config = {"sysref": self.model.sos1(possible_sysrefs)}
+        self.model.Obj(self.config["sysref"])
+
+        possible_device_clocks = []
+        for div in self.input_clock_dividers_available:
+            dev_clock = self.sample_clock / div
+            if self.device_clock_min <= dev_clock <= self.device_clock_max:
+                possible_device_clocks.append(dev_clock)
+
+        self.config["ref_clk"] = self.model.sos1(possible_device_clocks)
+        # self.model.Obj(-1 * self.config["device_clock"])
+
+        return [self.config["ref_clk"], self.config["sysref"]]
+
+    def get_required_clocks(self) -> List[Dict]:
+        """Generate list of required clocks.
+
+        For ADRV9009 this will contain:
+        [device clock requirement SOS, sysref requirement SOS]
+
+        Returns:
+            list[dict]: List of dictionaries of solver variables, equations, and constants
+        """
+        if self.solver == "gekko":
+            return self._gekko_get_required_clocks()
+        self.config = {}
+        self.config["lmfc_divisor_sysref"] = self._convert_input(
+            [*range(1, 20)], name="lmfc_divisor_sysref"
+        )
+
+        self.config["input_clock_divider_x2"] = self._convert_input(
+            self.input_clock_dividers_times2_available
+        )
+        self.config["ref_clk"] = self._add_intermediate(
+            self.sample_clock / self.config["input_clock_divider_x2"]
+        )
+        self.config["sysref"] = self._add_intermediate(
+            self.multiframe_clock
+            / (self.config["lmfc_divisor_sysref"] * self.config["lmfc_divisor_sysref"])
+        )
+
+        self._add_equation(
+            [
+                self.device_clock_min <= self.config["ref_clk"],
+                self.config["ref_clk"] <= self.device_clock_max,
+            ]
+        )
+
+        return [self.config["ref_clk"], self.config["sysref"]]
+
+
+class adrv9009_rx(adc, adrv9009_clock_common, adrv9009_core):
+    """ADRV9009 Receive model."""
+
+    quick_configuration_modes = {"jesd204b": quick_configuration_modes_rx}
+    name = "ADRV9009_RX"
+    converter_type = "adc"
+
+    # JESD configurations
+    K_available = [*np.arange(1, 32 + 1)]
+    L_available = [1, 2, 4]
+    M_available = [1, 2, 4]
+    N_available = [12, 14, 16, 24]
+    Np_available = [12, 16, 24]
+    F_available = [
+        1,
+        2,
+        3,
+        4,
+        6,
+        8,
+    ]
+    CS_available = [0]
+    CF_available = [0]
+    S_available = [1, 2, 4]
+
+    # Clock constraints
+    bit_clock_min_available = {"jesd204b": 3.6864e9}
+    bit_clock_max_available = {"jesd204b": 12.288e9}
+
+    _decimation = 8
+    decimation_available = [4, 5, 8, 10, 16, 20, 32, 40]
+    """
+    ADRV9009 Rx decimation stages.
+
+    .. code-block:: none
+
+            +-----------+
+            +-----------+ Dec 5 (5) +---------+
+            |           +-----------+         |
+            |                                 |
+            |   +----------+   +----------+   |  +------------+   +--------------+
+        >---+---+ RHB3 (2) +---+ RHB2 (2) +---+--+ RHB1 (1,2) +---+ RFIR (1,2,4) +
+                +----------+   +----------+      +------------+   +--------------+
+    """
+
+    def __init__(self, *args: Any, **kwargs: Any) -> None:  # noqa: ANN401
+        """Initialize ADRV9009-RX class.
+
+        Objects will default to mode and sample_clock.
+
+        Args:
+            *args (Any): Pass through arguments
+            **kwargs (Any): Pass through keyword arguments
+        """
+        # Set default mode
+        self.set_quick_configuration_mode(str(16))
+        # self.K = 32
+        self.sample_clock = int(122.88e6)
+        super().__init__(*args, **kwargs)
+        # self._init_diagram()
+
+    def get_required_clock_names(self) -> List[str]:
+        """Get list of strings of names of requested clocks.
+
+        This list of names is for the clocks defined by
+        get_required_clocks
+
+        Returns:
+            List[str]: List of strings of clock names mapped by get_required_clocks
+        """
+        return ["adrv9009_rx_ref_clk", "adrv9009_rx_sysref"]
+
+
+class adrv9009_tx(dac, adrv9009_clock_common, adrv9009_core):
+    """ADRV9009 Transmit model."""
+
+    quick_configuration_modes = {"jesd204b": quick_configuration_modes_tx}
+    name = "ADRV9009_TX"
+    converter_type = "dac"
+
+    # JESD configurations
+    K_available = [*np.arange(1, 32 + 1)]
+    L_available = [1, 2, 4]
+    M_available = [1, 2, 4]
+    N_available = [12, 16]
+    Np_available = [12, 16]
+    F_available = [1, 2, 3, 4, 8]
+    CS_available = [0]
+    CF_available = [0]
+    S_available = [1]
+
+    # Clock constraints
+    bit_clock_min_available = {"jesd204b": 2457.6e6}
+    bit_clock_max_available = {"jesd204b": 12.288e9}
+
+    _interpolation = 8
+    interpolation_available = [1, 2, 4, 5, 8, 10, 16, 20, 32]
+    """
+    ADRV9009 Tx interpolation stages.
+
+    .. code-block:: none
+
+                                +------------+
+            +--------------------+ Int 5  (5) +--------------------+
+            |                    +------------+                    |
+            |                                                      |
+            |   +------------+   +------------+   +------------+   |   +--------------+
+        <---+---+ THB3 (1,2) +---+ THB2 (1,2) +---+ THB1 (1,2) +---+---+ TFIR (1,2,4) +
+                +------------+   +------------+   +------------+       +--------------+
+
+    """
+
+    def __init__(self, *args: Any, **kwargs: Any) -> None:  # noqa: ANN401
+        """Initialize ADRV9009-TX class.
+
+        Objects will default to mode and sample_clock.
+
+        Args:
+            *args (Any): Pass through arguments
+            **kwargs (Any): Pass through keyword arguments
+        """
+        # Set default mode
+        self.set_quick_configuration_mode(str(6))
+        self.sample_clock = int(122.88e6)
+        super().__init__(*args, **kwargs)
+        # self._init_diagram()
+
+    def get_required_clock_names(self) -> List[str]:
+        """Get list of strings of names of requested clocks.
+
+        This list of names is for the clocks defined by
+        get_required_clocks
+
+        Returns:
+            List[str]: List of strings of clock names mapped by get_required_clocks
+        """
+        return ["adrv9009_tx_ref_clk", "adrv9009_tx_sysref"]
+
+
+class adrv9009(adrv9009_core):
+    """ADRV9009 combined transmit and receive model."""
+
+    name = "ADRV9009"
+    solver = "CPLEX"
+    _nested = ["adc", "dac"]
+    converter_type = "adc_dac"
+
+    def __init__(
+        self, model: Union[GEKKO, CpoModel] = None, solver: str = None
+    ) -> None:
+        """Initialize ADRV9009 clocking model for TX and RX.
+
+        This is a common class used to handle TX and RX constraints
+        together.
+
+        Args:
+            model (GEKKO,CpoModel): Solver model
+            solver (str): Solver name (gekko or CPLEX)
+        """
+        if solver:
+            self.solver = solver
+        self.adc = adrv9009_rx(model, solver=self.solver)
+        self.dac = adrv9009_tx(model, solver=self.solver)
+        self.model = model
+
+    def validate_config(self) -> None:
+        """Validate device configurations including JESD and clocks of both ADC and DAC.
+
+        This check only is for static configuration that does not include
+        variables which are solved.
+        """
+        self.adc.validate_config()
+        self.dac.validate_config()
+
+    def _get_converters(self) -> List[Union[converter, converter]]:
+        return [self.adc, self.dac]
+
+    def get_required_clocks(self) -> List[Dict]:
+        """Generate list of required clocks.
+
+        For ADRV9009 this will contain:
+        [device clock requirement SOS, sysref requirement SOS]
+
+        Returns:
+            list[dict]: List of dictionaries of solver variables, equations, and constants
+
+        Raises:
+            Exception: Invalid relation of rates between RX and TX
+            AssertionError: Gekko called
+        """
+        # Validate sample rates feasible
+        if self.dac.sample_clock / self.adc.sample_clock not in [
+            1,
+            2,
+            4,
+        ] or self.adc.sample_clock / self.dac.sample_clock not in [1, 2, 4]:
+            raise Exception(
+                "ADRV9009 RX and TX sample rates must be related by power of 2"
+            )
+
+        if self.solver == "gekko":
+            raise AssertionError
+
+        self.config = {}
+        self.config["adc_lmfc_divisor_sysref"] = self._convert_input(
+            self._lmfc_divisor_sysref_available, name="adc_lmfc_divisor_sysref"
+        )
+        self.config["dac_lmfc_divisor_sysref"] = self._convert_input(
+            self._lmfc_divisor_sysref_available, name="dac_lmfc_divisor_sysref"
+        )
+
+        self.config["input_clock_divider_x2"] = self._convert_input(
+            self.input_clock_dividers_times2_available
+        )
+
+        faster_clk = max([self.adc.sample_clock, self.dac.sample_clock])
+        self.config["ref_clk"] = self._add_intermediate(
+            faster_clk / self.config["input_clock_divider_x2"]
+        )
+
+        self.config["sysref_adc"] = self._add_intermediate(
+            self.adc.multiframe_clock / self.config["adc_lmfc_divisor_sysref"]
+        )
+        self.config["sysref_dac"] = self._add_intermediate(
+            self.dac.multiframe_clock / self.config["dac_lmfc_divisor_sysref"]
+        )
+
+        self._add_equation(
+            [
+                self.device_clock_min <= self.config["ref_clk"],
+                self.config["ref_clk"] <= self.device_clock_max,
+            ]
+        )
+
+        return [
+            self.config["ref_clk"],
+            self.config["sysref_adc"],
+            self.config["sysref_dac"],
+        ]