pyadi-jif 0.1.0__py2.py3-none-any.whl → 0.1.1__py2.py3-none-any.whl

adijif/tools/explorer/src/pages/systemconfigurator.py

@@ -0,0 +1,252 @@
+"""System configurator page."""
+
+from typing import Optional
+
+import pandas as pd
+import streamlit as st
+
+import adijif
+from adijif.clocks import supported_parts as csp
+from adijif.converters import supported_parts as xsp
+
+# from adijif.utils import get_jesd_mode_from_params
+from ..utils import Page
+from .helpers.datapath import gen_datapath
+
+# Clocks
+options_to_skip = ["list_references_available", "d_syspulse"]
+parts_to_ignore = ["ad9545", "ad9523_1"]
+sp = [p for p in csp if p not in parts_to_ignore]
+# Put HMC7044 at the front
+sp = [p for p in sp if p != "hmc7044"]
+sp.insert(0, "hmc7044")
+
+# Converters
+
+
+class SystemConfigurator(Page):
+    """System configurator tool page."""
+
+    def __init__(self, state: Optional[object]) -> None:
+        """Initialize system configurator page.
+
+        Args:
+            state: Application state object
+        """
+        self.state = state
+
+    def write(self) -> None:
+        """Render the system configurator page."""
+        st.title("System Configurator")
+
+        with st.expander("System Settings", expanded=True):
+            hsx = st.selectbox(
+                label="Select a converter part",
+                options=xsp,
+                format_func=lambda x: x.upper(),
+                key="converter_part_select",
+            )
+
+            clock = st.selectbox(
+                label="Select a clock part",
+                options=sp,
+                format_func=lambda x: x.upper(),
+                key="clock_part_select",
+            )
+
+            fpga_kit = st.selectbox(
+                label="Select an FPGA development kit",
+                options=adijif.xilinx._available_dev_kit_names,
+                format_func=lambda x: x.upper(),
+                key="fpga_dev_kit_select",
+            )
+
+            reference_rate = st.number_input(
+                f"Reference Rate (VCXO) for {clock.upper()} (Hz)",
+                value=125000000,
+                min_value=int(100e6),
+                max_value=int(400e6),
+            )
+
+        sys = adijif.system(hsx.lower(), clock.lower(), "xilinx", reference_rate)
+
+        # Get Converter clocking requirements
+        sys.Debug_Solver = False
+
+        # Get FPGA clocking requirements
+        sys.fpga.setup_by_dev_kit_name(fpga_kit.lower())
+
+        converter_c, fpga_c = st.columns(2)
+
+        with converter_c:
+            # st.header("Converter Configuration")
+            with st.expander("Converter Settings", expanded=True):
+
+                # Units GHz, MHz, kHz
+                units = st.selectbox(
+                    label="Select units for Converter Clock",
+                    options=["Hz", "kHz", "MHz", "GHz"],
+                    index=2,
+                )
+                if units == "Hz":
+                    multiplier = 1
+                elif units == "kHz":
+                    multiplier = 1e3
+                elif units == "MHz":
+                    multiplier = 1e6
+                elif units == "GHz":
+                    multiplier = 1e9
+
+                # Converter Clock
+                converter_clock = st.number_input(
+                    f"Converter Clock ({units})",
+                    value=1e9 / multiplier,
+                    format="%f",
+                    min_value=1e6 / multiplier,
+                    max_value=20e9 / multiplier,
+                )
+                # sys.converter.decimation = 1
+
+                decimation = gen_datapath(sys.converter)
+                sys.converter.sample_clock = converter_clock * multiplier / decimation
+
+                # JESD modes
+                qsm = sys.converter.quick_configuration_modes
+
+                # Flatten dict for display as a list
+                qsm_flat = {}
+                for jesdclasses in qsm:
+                    for mode in qsm[jesdclasses]:
+                        other_settings = (
+                            f" (M={sys.converter.M}, "
+                            + f"F={sys.converter.F}, K={sys.converter.K}, "
+                            + f"Np={sys.converter.Np}, CS={sys.converter.CS}, "
+                            + f"L={sys.converter.L}, S={sys.converter.S})"
+                        )
+                        qsm_flat[
+                            f"{jesdclasses.upper()} Mode: {mode} {other_settings}"
+                        ] = {
+                            "mode": mode,
+                            "jesdclass": jesdclasses,
+                        }
+
+                mode = st.selectbox(
+                    label="Select JESD Configuration Mode",
+                    options=list(qsm_flat.keys()),
+                    # options=list(qsm_flat.keys()),
+                    # format_func=lambda x: f"{x} : {qsm_flat[x]}",
+                )
+                sys.converter.set_quick_configuration_mode(
+                    qsm_flat[mode]["mode"], qsm_flat[mode]["jesdclass"]
+                )
+
+        # with clock_c:
+        #     st.header("Clock Configuration")
+
+        #     with st.container(border=True):
+        #         st.markdown(cfg["clock"])
+
+        with fpga_c:
+            with st.expander("FPGA Settings", expanded=True):
+
+                # sys.fpga.ref_clock_constraint = "Unconstrained"
+                ref_clock_constraint = st.selectbox(
+                    options=adijif.xilinx._ref_clock_constraint_options,
+                    label="FPGA Reference Clock Constraint",
+                    index=adijif.xilinx._ref_clock_constraint_options.index(
+                        "Unconstrained"
+                    ),
+                )
+                sys.fpga.ref_clock_constraint = ref_clock_constraint
+
+                # sys.fpga.sys_clk_select = "XCVR_QPLL0"  # Use faster QPLL
+                sys_clk_select = st.multiselect(
+                    options=adijif.xilinx.sys_clk_selections,
+                    label="XCVR System Clock Source Selection",
+                    default=adijif.xilinx.sys_clk_selections,
+                )
+                sys.fpga.sys_clk_select = sys_clk_select
+
+                # Enable all adijif.xilinx._out_clk_selections for selection by default
+                out_clk_select = st.multiselect(
+                    options=adijif.xilinx._out_clk_selections,
+                    label="XCVR Output Clock Selection",
+                    default=adijif.xilinx._out_clk_selections,
+                )
+                sys.fpga.out_clk_select = out_clk_select
+
+                # sys.fpga.force_qpll = 1
+                force_qpll_options = ["Auto", "Force QPLL", "Force QPLL1", "Force CPLL"]
+                force_qpll_selection = st.selectbox(
+                    options=force_qpll_options,
+                    label="Transceiver PLL Selection",
+                    index=0,
+                )
+                if force_qpll_selection == "Force QPLL":
+                    sys.fpga.force_qpll = True
+                elif force_qpll_selection == "Force QPLL1":
+                    sys.fpga.force_qpll1 = True
+                elif force_qpll_selection == "Force CPLL":
+                    sys.fpga.force_cpll = True
+
+        with st.expander("Derived Settings", expanded=True):
+
+            # Table with lane rate and core clock
+            lane_rate = sys.converter.bit_clock
+            core_clock = (
+                sys.converter.bit_clock / 66
+                if sys.converter.jesd_class == "jesd204c"
+                else sys.converter.bit_clock / 40
+            )
+            sample_clock = sys.converter.sample_clock
+            converter_clock = sys.converter.converter_clock
+
+            # Build pandas DataFrame
+            df = pd.DataFrame(
+                {
+                    "Setting": [
+                        "Lane Rate (Gbps)",
+                        "Needed Core Clock (MHz)",
+                        "Sample Clock (MHz)",
+                        "Converter Clock (MHz)",
+                    ],
+                    "Value": [
+                        f"{lane_rate/1e9:.4f}",
+                        f"{core_clock/1e6:.4f}",
+                        f"{sample_clock/1e6:.4f}",
+                        f"{converter_clock/1e6:.4f}",
+                    ],
+                }
+            )
+            # Remove index
+            df.index = df["Setting"]
+            df = df.drop(columns=["Setting"])
+            st.table(df)
+
+        with st.expander("System Configuration", expanded=False):
+            try:
+                cfg = sys.solve()
+
+                st.subheader("Clock Configuration")
+                st.write(cfg["clock"])
+
+                st.subheader("Converter Configuration")
+                st.write(cfg["converter"])
+
+                st.subheader("FPGA Configuration")
+                st.write(cfg["fpga_" + sys.converter.name.upper()])
+
+                st.subheader("Converter JESD Configuration")
+                st.write(cfg["jesd_" + sys.converter.name.upper()])
+
+                diagram = sys.draw(cfg)
+
+            except Exception as e:
+                diagram = None
+                st.error(f"Error solving system configuration: {e}")
+
+        with st.expander("Diagram", expanded=False):
+            if diagram:
+                st.image(diagram, width="stretch")
+            else:
+                st.write("No diagram available.")

adijif/tools/explorer/src/state.py

@@ -0,0 +1,141 @@
+"""Session state management for Streamlit application."""
+
+from copy import deepcopy
+from typing import TYPE_CHECKING, Any, Callable, Dict, Optional
+
+from streamlit.runtime import get_instance
+from streamlit.runtime.legacy_caching.hashing import _CodeHasher
+from streamlit.runtime.scriptrunner import get_script_run_ctx
+
+if TYPE_CHECKING:
+    from streamlit.runtime.state.session_state import SessionState as Session
+
+
+class _SessionState:
+    """Internal session state management class."""
+
+    def __init__(
+        self, session: "Session", hash_funcs: Optional[Dict[type, Callable[[Any], str]]]
+    ) -> None:
+        """Initialize SessionState instance."""
+        self.__dict__["_state"] = {
+            "data": {},
+            "hash": None,
+            "hasher": _CodeHasher(hash_funcs),
+            "is_rerun": False,
+            "session": session,
+        }
+
+    def __call__(self, **kwargs: Dict[str, Any]) -> None:  # type: ignore[misc]
+        """Initialize state data once."""
+        for item, value in kwargs.items():
+            if item not in self._state["data"]:
+                self._state["data"][item] = value
+
+    def __getitem__(self, item: str) -> Any:  # noqa: ANN401
+        """Return a saved state value, None if item is undefined."""
+        return self._state["data"].get(item, None)
+
+    def __getattr__(self, item: str) -> Any:  # noqa: ANN401
+        """Return a saved state value, None if item is undefined."""
+        return self._state["data"].get(item, None)
+
+    def __setitem__(self, item: str, value: Any) -> None:  # noqa: ANN401
+        """Set state value."""
+        self._state["data"][item] = value
+
+    def __setattr__(self, item: str, value: Any) -> None:  # noqa: ANN401
+        """Set state value."""
+        self._state["data"][item] = value
+
+    def clear(self) -> None:
+        """Clear session state and request a rerun."""
+        self._state["data"].clear()
+        self._state["session"].request_rerun()
+
+    def sync(self) -> None:
+        """Rerun the app with all state values up to date.
+
+        This fixes rollbacks from the beginning.
+        """
+        # Ensure to rerun only once to avoid infinite loops
+        # caused by a constantly changing state value at each run.
+        #
+        # Example: state.value += 1
+        if self._state["is_rerun"]:
+            self._state["is_rerun"] = False
+
+        elif self._state["hash"] is not None:
+            if self._state["hash"] != self._state["hasher"].to_bytes(
+                self._state["data"], None
+            ):
+                self._state["is_rerun"] = True
+                self._state["session"].request_rerun(None)
+
+        self._state["hash"] = self._state["hasher"].to_bytes(self._state["data"], None)
+
+
+def _get_session() -> Any:  # noqa: ANN401
+    """Get the current Streamlit session."""
+    runtime = get_instance()
+    session_id = get_script_run_ctx().session_id
+    session_info = runtime._session_mgr.get_session_info(session_id)
+
+    if session_info is None:
+        raise RuntimeError("Couldn't get your Streamlit Session object.")
+
+    return session_info.session
+
+
+def get_state(
+    hash_funcs: Optional[Dict[type, Callable[[Any], str]]] = None,
+) -> _SessionState:
+    """Get or create session state.
+
+    Args:
+        hash_funcs: Optional hash functions for state comparison
+
+    Returns:
+        Session state object
+    """
+    session = _get_session()
+
+    if not hasattr(session, "_custom_session_state"):
+        session._custom_session_state = _SessionState(session, hash_funcs)
+
+    return session._custom_session_state
+
+
+# Only used for separating namespace
+# Everything can be saved at state variable as well.
+CONFIG_DEFAULTS: Dict[str, Any] = {"slider_value": 0}
+
+
+def provide_state(
+    hash_funcs: Optional[Dict[type, Callable[[Any], str]]] = None,
+) -> Callable[[Callable[..., Any]], Callable[..., Any]]:
+    """Decorator to provide state to a function.
+
+    Args:
+        hash_funcs: Optional hash functions for state comparison
+
+    Returns:
+        Decorator function
+    """
+
+    def inner(func: Callable[..., Any]) -> Callable[..., Any]:  # noqa: ANN401
+        """Inner decorator function."""
+
+        def wrapper(*args: Any, **kwargs: Any) -> Any:  # noqa: ANN401
+            """Wrapper function that injects state."""
+            state = get_state(hash_funcs=hash_funcs)
+            if state.client_config is None:
+                state.client_config = deepcopy(CONFIG_DEFAULTS)
+
+            return_value = func(*args, state=state, **kwargs)  # noqa: B026
+            state.sync()
+            return return_value
+
+        return wrapper
+
+    return inner

adijif/tools/explorer/src/utils.py

@@ -0,0 +1,37 @@
+"""Utility functions and base classes for the explorer."""
+
+from abc import ABC, abstractmethod
+
+import streamlit as st
+
+# st.set_page_config(layout="wide")
+
+
+class Page(ABC):
+    """Base class for all page types."""
+
+    @abstractmethod
+    def write(self) -> None:
+        """Render the page content."""
+        pass
+
+
+def add_custom_css() -> None:
+    """Add custom CSS styling to the Streamlit app."""
+    st.html(
+        """
+        <style>
+            .stMainBlockContainer {
+                max-width:1200px;
+            }
+        </style>
+        """,
+    )
+    # st .markdown(
+    #     """
+    #     <style>
+    #         section.main > div {max-width:1000px;}
+    #     </style>
+    #     """,
+    #     unsafe_allow_html=True,
+    # )

adijif/types.py

@@ -95,16 +95,35 @@ class arb_source:
 
     _max_scalar = int(1e11)
 
-    def __init__(self, name: str) -> None:
+    def __init__(
+        self,
+        name: str,
+        a_min: Union[None, int] = None,
+        b_min: Union[None, int] = None,
+        a_max: Union[None, int] = None,
+        b_max: Union[None, int] = None,
+    ) -> None:
         """Arbitrary source for solver.
 
         Args:
             name (str): Name of source
+            a_min (int, optional): Minimum value for numerator. Defaults to None.
+            b_min (int, optional): Minimum value for denominator. Defaults to None.
+            a_max (int, optional): Maximum value for numerator. Defaults to None.
+            b_max (int, optional): Maximum value for denominator. Defaults to None.
         """
         self.name = name
-
-        self._a = integer_var(0, self._max_scalar, name=name + "_a")
-        self._b = integer_var(0, self._max_scalar, name=name + "_b")
+        if a_min is None:
+            a_min = 0
+        if a_max is None:
+            a_max = self._max_scalar
+        if b_min is None:
+            b_min = 0
+        if b_max is None:
+            b_max = self._max_scalar
+
+        self._a = integer_var(a_min, a_max, name=name + "_a")
+        self._b = integer_var(b_min, b_max, name=name + "_b")
 
     def __call__(self, model: Union[GEKKO, CpoModel]) -> Dict:
         """Generate arbitrary source for solver.

{pyadi_jif-0.1.0.dist-info → pyadi_jif-0.1.1.dist-info}/METADATA

@@ -1,29 +1,39 @@
 Metadata-Version: 2.4
 Name: pyadi-jif
-Version: 0.1.0
+Version: 0.1.1
 Summary: Python interface and configurator for ADI JESD Interface Framework
 Author-email: "Travis F. Collins" <travis.collins@analog.com>
 Maintainer: Analog Devices, Inc.
 Maintainer-email: Travis Collins <travis.collins@analog.com>
 License: EPL-2.0
+Classifier: Programming Language :: Python
+Classifier: Programming Language :: Python :: 3
+Classifier: Programming Language :: Python :: 3 :: Only
+Classifier: Programming Language :: Python :: 3.9
 Requires-Python: >=3.9
 Description-Content-Type: text/markdown
 License-File: LICENSE
 License-File: AUTHORS.rst
-Requires-Dist: numpy<2
+Requires-Dist: numpy
 Requires-Dist: openpyxl>=3.1.3
-Requires-Dist: pandas[openpyxl]>=1.1.5
+Requires-Dist: pandas>=1.1.5
 Provides-Extra: cplex
 Requires-Dist: cplex; extra == "cplex"
-Requires-Dist: docplex==2.24.231; extra == "cplex"
+Requires-Dist: docplex; extra == "cplex"
 Provides-Extra: gekko
 Requires-Dist: gekko; extra == "gekko"
+Provides-Extra: draw
+Requires-Dist: pyd2lang-native==0.0.3; extra == "draw"
+Provides-Extra: tools
+Requires-Dist: streamlit; extra == "tools"
 Dynamic: license-file
 
 # pyadi-jif: Python Configurator for ADI JESD204 Interface Framework (JIF)
 
 A framework to simplify the use of JESD204 with Analog Devices, Inc. data converters and clock chips.
 
+**New:** Try the interactive web-based [JIF Tools Explorer](#jif-tools-explorer) for a graphical interface!
+
 <p align="center">
 <img src="doc/source/imgs/PyADI-JIF_logo.png" width="500" alt="PyADI-JIF Logo"> </br>
 </p>
@@ -33,7 +43,7 @@ A framework to simplify the use of JESD204 with Analog Devices, Inc. data conver
 <a href="https://opensource.org/licenses/">
 <img src="https://img.shields.io/badge/License-EPL%20v2-blue.svg" alt="EPL v2.0>
 </a>
-    
+
 <a href="https://github.com/analogdevicesinc/pyadi-jif/actions/workflows/tests.yml">
 <img src="https://github.com/analogdevicesinc/pyadi-jif/actions/workflows/tests.yml/badge.svg" alt="Test Status">
 </a>
@@ -41,22 +51,36 @@ A framework to simplify the use of JESD204 with Analog Devices, Inc. data conver
 <a href="https://codecov.io/gh/analogdevicesinc/pyadi-jif">
 <img src="https://codecov.io/gh/analogdevicesinc/pyadi-jif/branch/main/graph/badge.svg?token=WVSRCSXFWL" alt="Coverage Status">
 </a>
-</p> 
-  
-## Installation 
+</p>
+
+## Installation
 
 Install JIF with pip
 
-```bash 
-  pip install --index-url https://test.pypi.org/simple/ pyadi-jif
+```bash
+pip install 'pyadi-jif[cplex]'
+```
+
+## JIF Tools Explorer
+
+Launch the interactive web-based tools for JESD204 configuration:
+
+```bash
+jiftools
 ```
 
+The JIF Tools Explorer provides:
+- **JESD204 Mode Selector** - Find and filter valid JESD204 modes for ADI converters
+- **Clock Configurator** - Configure ADI clock chips (HMC7044, AD9545, etc.)
+- **System Configurator** - Complete end-to-end system design (FPGA + Converter + Clock)
+
+See the [Tools Documentation](https://analogdevicesinc.github.io/pyadi-jif/main/tools.html) for detailed usage guide.
 
 ## Documentation
 
-[Documentation](https://analogdevicesinc.github.io/pyadi-jif/main/)
+[Documentation](https://analogdevicesinc.github.io/pyadi-jif)
+
 
-  
 ## License
 
 [EPL-2.0](https://www.eclipse.org/legal/epl-2.0/)