pyadi-jif 0.1.0__py2.py3-none-any.whl → 0.1.1__py2.py3-none-any.whl

adijif/__init__.py

@@ -2,7 +2,7 @@
 
 __author__ = """Analog Devices, Inc."""
 __email__ = "travis.collins@analog.com"
-__version__ = "0.1.0"
+__version__ = "0.1.1"
 
 import adijif.solvers
 import adijif.utils
@@ -20,7 +20,7 @@ from adijif.converters.ad9081 import (
     ad9082_rx,
     ad9082_tx,
 )
-from adijif.converters.ad9084 import ad9084_rx
+from adijif.converters.ad9084 import ad9084_rx, ad9088_rx
 from adijif.converters.ad9144 import ad9144
 from adijif.converters.ad9680 import ad9680
 from adijif.converters.adrv9009 import adrv9009, adrv9009_rx, adrv9009_tx

adijif/clocks/ad9523_1_bf.py

@@ -55,7 +55,7 @@ class ad9523_1_bf(clock):
                         if (vco / m1) % mod == 0:
                             # See if we can use only m1 and not both m1+m2
                             rods = (vco / m1) / required_output_rates
-                            if np.all(np.in1d(rods, self.d_available)):
+                            if np.all(np.isin(rods, self.d_available)):
                                 configs.append(
                                     {
                                         "m1": m1,
@@ -67,10 +67,10 @@ class ad9523_1_bf(clock):
                                 )
                             else:
                                 # Try to use m2 as well to meet required out clocks
-                                f1 = np.in1d(rods, self.d_available)
+                                f1 = np.isin(rods, self.d_available)
                                 for m2 in self.m1_available:
                                     rods2 = (vco / m2) / required_output_rates
-                                    f2 = np.in1d(rods2, self.d_available)
+                                    f2 = np.isin(rods2, self.d_available)
                                     if np.logical_or(f1, f2).all():
                                         configs.append(
                                             {

adijif/clocks/ad9528_bf.py

@@ -56,7 +56,7 @@ class ad9528_bf(clock):
                         and (vco / m1) % mod == 0
                     ):
                         required_output_divs = (vco / m1) / required_output_rates
-                        if np.all(np.in1d(required_output_divs, self.d_available)):
+                        if np.all(np.isin(required_output_divs, self.d_available)):
                             configs.append(
                                 {
                                     "m1": m1,

adijif/clocks/hmc7044_bf.py

@@ -52,7 +52,7 @@ class hmc7044_bf(clock):
                     # Check if required dividers for output clocks are in set
                     if f % mod == 0:
                         d = f / rates
-                        if np.all(np.in1d(d, odivs)) and f not in vcos:
+                        if np.all(np.isin(d, odivs)) and f not in vcos:
                             if f not in vcos:
                                 vcos.append(f)
                                 config = {

adijif/clocks/ltc6952.py

@@ -600,7 +600,7 @@ class ltc6952(ltc6952_bf):
         self._clk_names = clk_names
 
         # Add requested clocks to output constraints
-        for out_freq in out_freqs:
+        for out_freq, clk_name in zip(out_freqs, clk_names):  # noqa: B905
             if self.solver == "gekko":
                 __d = self._d if isinstance(self._d, list) else [self._d]
                 if __d.sort() != self.d_available.sort():
@@ -613,7 +613,7 @@ class ltc6952(ltc6952_bf):
                 od = self.model.Intermediate(mp * pow(2, nx))
 
             elif self.solver == "CPLEX":
-                od = self._convert_input(self._d, "d_" + str(out_freq))
+                od = self._convert_input(self._d, f"d_{out_freq}_{clk_name}")
 
             self._add_equation(
                 [self.vcxo / self.config["r2"] * self.config["n2"] / od == out_freq]

adijif/clocks/ltc6952_bf.py

@@ -51,7 +51,7 @@ class ltc6952_bf(clock):
                     # Check if required dividers for output clocks are in set
                     if f % mod == 0:
                         d = f / rates
-                        if np.all(np.in1d(d, odivs)) and f not in vcos:
+                        if np.all(np.isin(d, odivs)) and f not in vcos:
                             if f not in vcos:
                                 vcos.append(f)
                                 config = {

adijif/clocks/ltc6953.py

@@ -490,7 +490,7 @@ class ltc6953(clock):
         self._setup(input_ref)
 
         # Add requested clocks to output constraints
-        for out_freq in out_freqs:
+        for out_freq, clk_name in zip(out_freqs, clk_names):  # noqa: B905
             if self.solver == "gekko":
                 __m = self._d if isinstance(self.__m, list) else [self.__m]
                 if __m.sort() != self.m_available.sort():
@@ -503,7 +503,7 @@ class ltc6953(clock):
                 od = self.model.Intermediate(mp * pow(2, nx))
 
             elif self.solver == "CPLEX":
-                od = self._convert_input(self._m, "m_" + str(out_freq))
+                od = self._convert_input(self._m, f"m_{out_freq}_{clk_name}")
 
             self._add_equation([self.input_ref / od == out_freq])
             self.config["out_dividers"].append(od)

adijif/converters/__init__.py

@@ -1,3 +1,14 @@
 """ADI JIF converter models."""
 
-supported_parts = ["ad9680", "adrv9009_rx", "ad9081_rx", "ad9144", "ad9084_rx"]
+supported_parts = [
+    "ad9680",
+    "adrv9009_rx",
+    "adrv9009_tx",
+    "ad9081_rx",
+    "ad9081_tx",
+    "ad9082_rx",
+    "ad9082_tx",
+    "ad9144",
+    "ad9084_rx",
+    "ad9088_rx",
+]

adijif/converters/ad9081.py

@@ -70,7 +70,7 @@ class ad9081_core(converter, metaclass=ABCMeta):
     M_available = [1, 2, 3, 4, 6, 8, 12, 16]
     L_available = [1, 2, 3, 4, 6, 8]
     N_available = [12, 16]
-    Np_available = [12, 16, 24]
+    Np_available = [8, 12, 16, 24]
     F_available = [1, 2, 3, 4, 6, 8, 12, 16, 24, 32]
     S_available = [1, 2, 4, 8]
     # FIXME

adijif/converters/ad9081_dp.py

@@ -120,11 +120,13 @@ class ad9081_dp_tx:
 
     cduc_enabled = [True, True, True, True]
     cduc_interpolation = 1
+    cduc_interpolations_available = [1, 2, 4, 6, 8, 12]
     cduc_nco_frequencies = [0, 0, 0, 0]
     cduc_nco_phases = [0, 0, 0, 0]
 
     fduc_enabled = [False, False, False, False, False, False, False, False]
     fduc_interpolation = 1
+    fduc_interpolations_available = [1, 2, 3, 4, 6, 8]
     fduc_nco_frequencies = [0, 0, 0, 0, 0, 0, 0, 0]
     fduc_nco_phases = [0, 0, 0, 0, 0, 0, 0, 0]
 

adijif/converters/ad9084.py

@@ -8,6 +8,7 @@ from .ad9084_dp import ad9084_dp_rx
 from .ad9084_draw import ad9084_draw
 from .ad9084_util import _load_rx_config_modes, apply_settings
 from .ad9084_util import parse_json_config as parse_json_cfg
+from .ad9088_dp import ad9088_dp_rx
 from .adc import adc
 from .converter import converter
 
@@ -132,7 +133,8 @@ class ad9084_core(ad9084_draw, converter, metaclass=ABCMeta):
         Returns:
             List[str]: List of strings of clock names in order
         """
-        return ["AD9084_ref_clk", "AD9084_sysref"]
+        name = "AD9084" if "9084" in self.name else "AD9088"
+        return [f"{name}_ref_clk", f"{name}_sysref"]
 
     @property
     @abstractmethod
@@ -280,7 +282,7 @@ class ad9084_rx(adc, ad9084_core):
     sample_clock_min = 312.5e6 / 16  # FIXME
     sample_clock_max = 20e9
 
-    quick_configuration_modes = _load_rx_config_modes()
+    quick_configuration_modes = _load_rx_config_modes(part="AD9084")
 
     datapath = ad9084_dp_rx()
 
@@ -310,11 +312,14 @@ class ad9084_rx(adc, ad9084_core):
             *args (Any): Pass through arguments
             **kwargs (Any): Pass through keyword arguments
         """
-        self.sample_clock = int(2.5e9)
-        self.datapath.cddc_decimations = [4] * 4
-        self.datapath.fddc_decimations = [2] * 8
-        self.datapath.fddc_enabled = [True] * 8
-        self.set_quick_configuration_mode("47", "jesd204c")
+        self.sample_clock = int(2.5e9) if "AD9084" in self.name else int(1e9)
+        N = 1 if "9084" in self.name else 2
+        self.datapath.cddc_decimations = [4] * 4 * N
+        self.datapath.fddc_decimations = [2] * 8 * N
+        self.datapath.fddc_enabled = [True] * 8 * N
+        mode = "47" if "9084" in self.name else "45"
+
+        self.set_quick_configuration_mode(mode, "jesd204c")
 
         super().__init__(*args, **kwargs)
         self._init_diagram()
@@ -372,6 +377,23 @@ class ad9084_rx(adc, ad9084_core):
         #     raise Exception("Decimation not valid")
 
 
+class ad9088_rx(ad9084_rx):
+    """AD9088 Receive model."""
+
+    converter_type = "adc"
+    name = "AD9088_RX"
+
+    converter_clock_min = 2.9e9
+    converter_clock_max = 8e9
+
+    sample_clock_min = 2.9e9 / (6 * 24)  # with max decimation
+    sample_clock_max = 8e9
+
+    datapath = ad9088_dp_rx()
+
+    quick_configuration_modes = _load_rx_config_modes(part="AD9088")
+
+
 # class ad9084_tx(dac, ad9084_core):
 #     """AD9084 Transmit model."""
 

adijif/converters/ad9084_draw.py

@@ -16,7 +16,10 @@ class ad9084_draw:
         self.ic_diagram_node = None
         self._diagram_output_dividers = []
 
-        self.ic_diagram_node = Node("AD9084")
+        name = "AD9084" if "9084" in self.name else "AD9088"
+        N = 4 if "9084" in self.name else 8
+
+        self.ic_diagram_node = Node(name)
 
         # External
         # ref_in = Node("REF_IN", ntype="input")
@@ -28,19 +31,19 @@ class ad9084_draw:
         self.ic_diagram_node.add_child(crossbar)
         self.ic_diagram_node.add_child(crossbar_rm)
 
-        for adc in range(4):
+        for adc in range(N):
             adc_node = Node(f"ADC{adc}", ntype="adc")
             self.ic_diagram_node.add_child(adc_node)
             adc_node.shape = "parallelogram"
             self.ic_diagram_node.add_connection({"from": adc_node, "to": crossbar})
 
-        for cddc in range(4):
+        for cddc in range(N):
             cddc_node = Node(f"CDDC{cddc}", ntype="ddc")
             self.ic_diagram_node.add_child(cddc_node)
             self.ic_diagram_node.add_connection({"from": crossbar, "to": cddc_node})
             self.ic_diagram_node.add_connection({"from": cddc_node, "to": crossbar_rm})
 
-        for fddc in range(8):
+        for fddc in range(N * 2):
             fddc_node = Node(f"FDDC{fddc}", ntype="ddc")
             self.ic_diagram_node.add_child(fddc_node)
             self.ic_diagram_node.add_connection({"from": crossbar_rm, "to": fddc_node})
@@ -48,7 +51,7 @@ class ad9084_draw:
         jesd204_framer = Node("JESD204 Framer", ntype="jesd204framer")
         self.ic_diagram_node.add_child(jesd204_framer)
 
-        for ddc in range(8):
+        for ddc in range(N * 2):
             fddc = self.ic_diagram_node.get_child(f"FDDC{ddc}")
             self.ic_diagram_node.add_connection({"from": fddc, "to": jesd204_framer})
 
@@ -97,8 +100,11 @@ class ad9084_draw:
 
         system_draw = lo is not None
 
+        name = "AD9084" if "9084" in self.name else "AD9088"
+        N = 4 if "9084" in self.name else 8
+
         if not system_draw:
-            lo = Layout("AD9084 Example")
+            lo = Layout(f"{name} Example")
             lo.show_rates = self.show_rates
         else:
             # Verify lo is a Layout object
@@ -109,7 +115,7 @@ class ad9084_draw:
             ref_in = Node("REF_IN", ntype="input")
             lo.add_node(ref_in)
         else:
-            to_node = lo.get_node("AD9084_ref_clk")
+            to_node = lo.get_node(f"{name}_ref_clk")
             # Locate node connected to this one
             from_node = lo.get_connection(to=to_node.name)
             assert from_node, "No connection found"
@@ -119,16 +125,16 @@ class ad9084_draw:
             # Remove to_node since it is not needed
             lo.remove_node(to_node.name)
 
-        for i in range(4):
+        for i in range(N):
             adc = self.ic_diagram_node.get_child(f"ADC{i}")
             lo.add_connection(
-                {"from": ref_in, "to": adc, "rate": clocks["AD9084_ref_clk"]}
+                {"from": ref_in, "to": adc, "rate": clocks[f"{name}_ref_clk"]}
             )
 
         # Update Node values
         fddc_index = 0
-        for cddc in range(4):
-            rate = clocks["AD9084_ref_clk"]
+        for cddc in range(N):
+            rate = clocks[f"{name}_ref_clk"]
             self.ic_diagram_node.update_connection("MUX0", f"CDDC{cddc}", rate)
 
             cddc_node = self.ic_diagram_node.get_child(f"CDDC{cddc}")
@@ -163,11 +169,11 @@ class ad9084_draw:
                 {
                     "from": sysref_in,
                     "to": self.ic_diagram_node.get_child("JESD204 Framer"),
-                    "rate": clocks["AD9084_sysref"],
+                    "rate": clocks[f"{name}_sysref"],
                 }
             )
         else:
-            to_node = lo.get_node("AD9084_sysref")
+            to_node = lo.get_node(f"{name}_sysref")
             # Locate node connected to this one
             from_node = lo.get_connection(to=to_node.name)
             assert from_node, "No connection found"
@@ -181,7 +187,7 @@ class ad9084_draw:
                 {
                     "from": sysref_in,
                     "to": self.ic_diagram_node.get_child("JESD204 Framer"),
-                    "rate": clocks["AD9084_sysref"],
+                    "rate": clocks[f"{name}_sysref"],
                 }
             )
 

adijif/converters/ad9084_util.py

@@ -41,12 +41,23 @@ def _convert_to_config(
     }
 
 
-def _load_rx_config_modes() -> Dict:
-    """Load RX JESD configuration tables from file."""
-    return _read_table_xlsx("AD9084_JTX_JRX.xlsx")
+def _load_rx_config_modes(part: str) -> Dict:
+    """Load RX JESD configuration tables from file.
+
+    Args:
+        part (str): Part name, either "AD9084" or "AD9088".
+
+    Returns:
+        Dict: Dictionary of JESD configuration modes.
+
+    Raises:
+        AssertionError: If the part is not supported.
+    """
+    assert part in ["AD9084", "AD9088"], f"Unsupported part: {part}"
+    return _read_table_xlsx("AD9084_JTX_JRX.xlsx", part)
 
 
-def _read_table_xlsx(filename: str) -> Dict:
+def _read_table_xlsx(filename: str, part: str) -> Dict:
     loc = os.path.dirname(__file__)
     fn = os.path.join(loc, "resources", filename)
     table = pd.read_excel(open(fn, "rb"), sheet_name="JTX_RxPath")
@@ -57,7 +68,15 @@ def _read_table_xlsx(filename: str) -> Dict:
     jrx_modes_204c = {}
     for prow in table.iterrows():
         row = prow[1].to_dict()
-        # print(row)
+
+        field = "8T8R" if part == "AD9088" else "4T4R"
+        data = str(row[field])
+
+        if "nan" in data:
+            continue
+        if "Not Supported" in data:
+            continue
+
         jrx_modes_204c[str(row["Mode"])] = {
             "L": row["L"],
             "M": row["M"],

adijif/converters/ad9088_dp.py

@@ -0,0 +1,111 @@
+"""AD9088 Datapath Description Class."""
+
+
+class ad9088_dp_rx:
+    """AD9088 RX Data Path Configuration."""
+
+    cddc_enabled = [True, True, True, True]
+    cddc_decimations = [1, 1, 1, 1, 1, 1, 1, 1]
+    cddc_decimations_available = [1, 2, 3, 4, 6, 12]
+    cddc_nco_frequencies = [0, 0, 0, 0, 0, 0, 0, 0]
+    cddc_nco_phases = [0, 0, 0, 0, 0, 0, 0, 0]
+
+    fddc_enabled = [False] * 16
+    fddc_decimations = [1] * 16
+    fddc_decimations_available = [1, 2, 4, 8, 16, 32, 64]
+    fddc_nco_frequencies = [0] * 16
+    fddc_nco_phases = [0] * 16
+
+    fddc_source = [1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8]
+
+    def get_config(self) -> dict:
+        """Get the datapath configuration for the AD9088 RX.
+
+        Returns:
+            dict: datapath configuration
+        """
+        datapath = {}
+        datapath["cddc"] = {}
+        datapath["cddc"]["enabled"] = self.cddc_enabled
+        datapath["cddc"]["decimations"] = self.cddc_decimations
+        datapath["cddc"]["nco_frequencies"] = self.cddc_nco_frequencies
+        datapath["cddc"]["nco_phases"] = self.cddc_nco_phases
+
+        datapath["fddc"] = {}
+        datapath["fddc"]["enabled"] = self.fddc_enabled
+        datapath["fddc"]["decimations"] = self.fddc_decimations
+        datapath["fddc"]["nco_frequencies"] = self.fddc_nco_frequencies
+        datapath["fddc"]["nco_phases"] = self.fddc_nco_phases
+        datapath["fddc"]["source"] = self.fddc_source
+
+        return datapath
+
+    @property
+    def decimation_overall(self) -> int:
+        """Minimum Overall Decimation factor.
+
+        Raises:
+            Exception: No FDDC or CDDC enabled
+            Exception: Enabled FDDC's source CDDC not enabled
+
+        Returns:
+            int: minimum overall decimation factor
+        """
+        if (not any(self.fddc_enabled)) and (not any(self.cddc_enabled)):
+            raise Exception("No FDDCs or CDDCs enabled")
+
+        if any(self.fddc_enabled):
+            min_dec = -1
+            for i, fdec in enumerate(self.fddc_decimations):
+                if self.fddc_enabled[i]:
+                    cddc = self.fddc_source[i]
+                    if not self.cddc_enabled:
+                        raise Exception(f"Source CDDC {cddc} not enabled for FDDC {i}")
+                    cdec = self.cddc_decimations[cddc - 1]
+                    if (cdec * fdec < min_dec) or min_dec == -1:
+                        min_dec = cdec * fdec
+        else:
+            min_dec = -1
+            for i, cdec in enumerate(self.cddc_decimations):
+                if self.cddc_enabled[i] and (min_dec == -1 or cdec < min_dec):
+                    min_dec = cdec
+
+        return min_dec
+
+
+# class ad9088_dp_tx:
+#     """AD9088 TX Data Path Configuration."""
+
+#     cduc_enabled = [True, True, True, True]
+#     cduc_interpolation = 1
+#     cduc_nco_frequencies = [0, 0, 0, 0]
+#     cduc_nco_phases = [0, 0, 0, 0]
+
+#     fduc_enabled = [False, False, False, False, False, False, False, False]
+#     fduc_interpolation = 1
+#     fduc_nco_frequencies = [0, 0, 0, 0, 0, 0, 0, 0]
+#     fduc_nco_phases = [0, 0, 0, 0, 0, 0, 0, 0]
+
+#     cduc_sources = [[1], [1], [3], [3]]
+
+#     def get_config(self) -> dict:
+#         """Get the datapath configuration for the AD9088 TX.
+
+#         Returns:
+#             dict: Datapath configuration
+#         """
+#         datapath = {}
+#         datapath["cduc"] = {}
+#         datapath["cduc"]["enabled"] = self.cduc_enabled
+#         datapath["cduc"]["interpolation"] = self.cduc_interpolation
+#         datapath["cduc"]["nco_frequencies"] = self.cduc_nco_frequencies
+#         datapath["cduc"]["nco_phases"] = self.cduc_nco_phases
+#         datapath["cduc"]["sources"] = self.cduc_sources
+
+#         datapath["fduc"] = {}
+#         datapath["fduc"]["enabled"] = self.fduc_enabled
+#         datapath["fduc"]["interpolation"] = self.fduc_interpolation
+#         datapath["fduc"]["nco_frequencies"] = self.fduc_nco_frequencies
+#         datapath["fduc"]["nco_phases"] = self.fduc_nco_phases
+
+#         return datapath