pyadi-jif 0.1.0__py2.py3-none-any.whl → 0.1.1__py2.py3-none-any.whl

adijif/converters/converter.py

@@ -24,6 +24,9 @@ class converter(core, jesd, gekko_translation, metaclass=ABCMeta):
     """DSP data path of device"""
     datapath = None
 
+    """Show rates on drawing diagrams."""
+    show_rates = True
+
     config: Dict = {}
     _jesd_params_to_skip = [
         "E",
@@ -36,10 +39,10 @@ class converter(core, jesd, gekko_translation, metaclass=ABCMeta):
         "global_index",
     ]
 
-    def draw(
+    def draw_dac(
         self, clocks: Dict, lo: Layout = None, clock_chip_node: Node = None
     ) -> str:
-        """Generic Draw converter model.
+        """Generic Draw converter DAC model.
 
         Args:
             clocks (Dict): Clocking configuration
@@ -57,6 +60,7 @@ class converter(core, jesd, gekko_translation, metaclass=ABCMeta):
 
         if not system_draw:
             lo = Layout(f"{name} Example")
+            lo.show_rates = self.show_rates
         else:
             assert isinstance(lo, Layout), "lo must be a Layout object"
 
@@ -102,9 +106,133 @@ class converter(core, jesd, gekko_translation, metaclass=ABCMeta):
 
         lo.add_connection({"from": ref_in, "to": ic_node, "rate": rate})
 
+        # Add deframer
+        jesd204_deframer = Node("JESD204 Deframer", ntype="jesd204deframer")
+        ic_node.add_child(jesd204_deframer)
+
+        # Add DAC
+        dac = Node("DAC", ntype="dac")
+        ic_node.add_child(dac)
+        ic_node.add_connection({"from": jesd204_deframer, "to": dac})
+
+        # SYSREF
+        if not system_draw:
+            sysref_in = Node("SYSREF_IN", ntype="input")
+            lo.add_connection(
+                {
+                    "from": sysref_in,
+                    "to": jesd204_deframer,
+                    # "rate": clocks[f"{name}_sysref"],
+                    "rate": clocks[sysref_clk_name],
+                }
+            )
+        else:
+            # to_node = lo.get_node(f"{name}_sysref")
+            to_node = lo.get_node(sysref_clk_name)
+            from_node = lo.get_connection(to=to_node.name)
+            assert from_node, "No connection found"
+            assert isinstance(from_node, list), "Connection must be a list"
+            assert len(from_node) == 1, "Only one connection allowed"
+            sysref_in = from_node[0]["from"]
+            lo.remove_node(to_node.name)
+
+            lo.add_connection(
+                {
+                    "from": sysref_in,
+                    "to": jesd204_deframer,
+                    # "rate": clocks[f"{name}_sysref"],
+                    "rate": clocks[sysref_clk_name],
+                }
+            )
+
+        # WIP Add remote framer
+        jesd204_framer = Node("JESD204 Framer", ntype="framer")
+
+        # Add connect for each lane
+        for _ in range(self.L):
+            lane_rate = self.bit_clock
+            lo.add_connection(
+                {"from": jesd204_framer, "to": jesd204_deframer, "rate": lane_rate}
+            )
+
+        if not system_draw:
+            return lo.draw()
+
+    def draw_adc(
+        self, clocks: Dict, lo: Layout = None, clock_chip_node: Node = None
+    ) -> str:
+        """Generic Draw converter ADC model.
+
+        Args:
+            clocks (Dict): Clocking configuration
+            lo (Layout): Layout object to draw on
+            clock_chip_node (Node): Clock chip node to add to. Defaults to None.
+
+        Returns:
+            str: Path to image file
+
+        Raises:
+            Exception: If no solution is saved
+        """
+        system_draw = lo is not None
+        name = self.name.lower()
+
+        if not system_draw:
+            lo = Layout(f"{name} Example")
+            lo.show_rates = self.show_rates
+        else:
+            assert isinstance(lo, Layout), "lo must be a Layout object"
+
+        ic_node = Node(self.name)
+        lo.add_node(ic_node)
+
+        # rate = clocks[f"{name}_ref_clk"]
+        # Find key with ending
+        ref_clk_name = None
+        for key in clocks.keys():
+            if key.lower().endswith(f"{name.lower()}_ref_clk"):
+                ref_clk_name = key
+                break
+        if ref_clk_name is None:
+            raise Exception(
+                f"No clock found for {name}_ref_clk\n.Options: {clocks.keys()}"
+            )
+
+        sysref_clk_name = None
+        for key in clocks.keys():
+            if key.lower().endswith(f"{name.lower()}_sysref"):
+                sysref_clk_name = key
+                break
+        if sysref_clk_name is None:
+            raise Exception(
+                f"No clock found for {name}_sysref\n.Options: {clocks.keys()}"
+            )
+
+        if not system_draw:
+            ref_in = Node("REF_IN", ntype="input")
+            lo.add_node(ref_in)
+        else:
+            to_node = lo.get_node(ref_clk_name)
+            from_node = lo.get_connection(to=to_node.name)
+            assert from_node, "No connection found"
+            assert isinstance(from_node, list), "Connection must be a list"
+            assert len(from_node) == 1, "Only one connection allowed"
+            ref_in = from_node[0]["from"]
+            # Remove to_node since it is not needed
+            lo.remove_node(to_node.name)
+
+        rate = clocks[ref_clk_name]
+
+        lo.add_connection({"from": ref_in, "to": ic_node, "rate": rate})
+
+        # Add ADC
+        adc = Node("ADC", ntype="adc")
+        ic_node.add_child(adc)
+
         # Add framer
         jesd204_framer = Node("JESD204 Framer", ntype="jesd204framer")
         ic_node.add_child(jesd204_framer)
+        ic_node.add_connection({"from": adc, "to": jesd204_framer})
 
         # SYSREF
         if not system_draw:
@@ -149,6 +277,29 @@ class converter(core, jesd, gekko_translation, metaclass=ABCMeta):
         if not system_draw:
             return lo.draw()
 
+    def draw(
+        self, clocks: Dict, lo: Layout = None, clock_chip_node: Node = None
+    ) -> str:
+        """Generic Draw converter model.
+
+        Args:
+            clocks (Dict): Clocking configuration
+            lo (Layout): Layout object to draw on
+            clock_chip_node (Node): Clock chip node to add to. Defaults to None.
+
+        Returns:
+            str: Path to image file
+
+        Raises:
+            Exception: If no solution is saved
+        """
+        if self.converter_type.lower() == "adc":
+            return self.draw_adc(clocks, lo, clock_chip_node)
+        elif self.converter_type.lower() == "dac":
+            return self.draw_dac(clocks, lo, clock_chip_node)
+        else:
+            raise Exception("Unknown converter type")
+
     def validate_config(self) -> None:
         """Validate device configuration including JESD and clocks.
 

adijif/draw.py

@@ -3,6 +3,7 @@
 from __future__ import annotations
 
 import os
+from importlib.util import find_spec
 from typing import Union
 
 connection_style_types = {
@@ -191,7 +192,7 @@ class Layout:
 
     si = "    "
     use_d2_cli = False
-    _write_out_d2_file = True
+    _write_out_d2_file = False
 
     def __init__(self, name: str) -> None:
         """Initialize layout with name.
@@ -313,6 +314,9 @@ class Layout:
 
         Returns:
             str: Path to the output image file.
+
+        Raises:
+            Exception: d2 support not installed.
         """
         diag = "direction: right\n\n"
 
@@ -488,7 +492,12 @@ class Layout:
                 print(f"Saved to {self.output_filename}")
 
             # Use bindings
-            from .d2 import compile
+            if find_spec("d2"):
+                from d2 import compile
+            else:
+                raise Exception(
+                    "d2 support not installed. Please install package pyd2lang-native"
+                )
 
             out = compile(diag)
             # with open(self.output_image_filename, "w") as f:

adijif/fpgas/xilinx/__init__.py

@@ -280,6 +280,8 @@ class xilinx(xilinx_bf, xilinx_draw):
         """
         return self._ref_clock_constraint
 
+    _ref_clock_constraint_options = ["CORE_CLOCK", "CORE_CLOCK_DIV2", "Unconstrained"]
+
     @ref_clock_constraint.setter
     def ref_clock_constraint(self, value: str) -> None:
         """Set reference clock constraint.
@@ -295,10 +297,10 @@ class xilinx(xilinx_bf, xilinx_draw):
         Raises:
             Exception: Invalid ref_clock_constraint selection.
         """
-        if value not in ["CORE_CLOCK", "CORE_CLOCK_DIV2", "Unconstrained"]:
+        if value not in self._ref_clock_constraint_options:
             raise Exception(
                 f"Invalid ref_clock_constraint {value}, "
-                + "options are CORE_CLOCK, CORE_CLOCK_DIV2, Unconstrained"
+                + f"options are {self._ref_clock_constraint_options}"
             )
         self._ref_clock_constraint = value
 

adijif/jesd.py

@@ -631,7 +631,9 @@ class jesd(metaclass=ABCMeta):
         if int(value) != value:
             raise Exception("Np must be an integer")
         if value not in self.Np_available:
-            raise Exception("Np not in range for device")
+            msg = "Np not in range for device. "
+            msg += f"Got {value}, valid are {self.Np_available}"
+            raise Exception(msg)
         self._Np = value
 
     # DERIVED SCALERS

adijif/plls/adf4030.py

@@ -4,6 +4,7 @@ from typing import Dict, List, Union
 
 from docplex.cp.solution import CpoSolveResult  # type: ignore
 
+from adijif.clocks.clock import clock as clockc
 from adijif.plls.pll import pll
 from adijif.solvers import CpoExpr, GK_Intermediate
 
@@ -193,11 +194,15 @@ class adf4030(pll):
             ]
         )
 
-    def _setup(self, input_ref: int) -> None:
+    def _setup(self, input_ref: Union[int, clockc]) -> None:
         if isinstance(input_ref, (float, int)):
             assert (
                 self.input_freq_max >= input_ref >= self.input_freq_min
             ), "Input frequency out of range"
+        else:
+            self._add_equation(
+                [input_ref <= self.input_freq_max, input_ref >= self.input_freq_min]
+            )
 
         # Setup clock chip internal constraints
         self._setup_solver_constraints(input_ref)

adijif/plls/adf4382.py

@@ -576,6 +576,5 @@ class adf4382(pll):
         """
         self._setup(ref_in)
         self._clk_names = ["rf_out"]
-        print(f"Output: {out_freq}")
 
         self._add_equation([self.config["o"] * out_freq == self.config["vco"]])

adijif/solvers.py

@@ -2,9 +2,10 @@
 # pytype: skip-file
 """Common solver API management layer."""
 
+from importlib.util import find_spec
 from typing import Union
 
-try:
+if find_spec("docplex"):
     from docplex.cp.expression import CpoExpr  # type: ignore
     from docplex.cp.expression import CpoFunctionCall  # type: ignore
     from docplex.cp.expression import CpoIntVar  # type: ignore
@@ -13,7 +14,7 @@ try:
     from docplex.cp.solution import CpoSolveResult  # type: ignore
 
     cplex_solver = True
-except ImportError:
+else:
     cplex_solver = False
     CpoExpr = None
     CpoFunctionCall = None
@@ -22,7 +23,7 @@ except ImportError:
     continuous_var = None
     interval_var = None
 
-try:
+if find_spec("gekko"):
     import gekko  # type: ignore
     from gekko import GEKKO  # type: ignore
     from gekko.gk_operators import GK_Intermediate  # type: ignore
@@ -30,7 +31,7 @@ try:
     from gekko.gk_variable import GKVariable  # type: ignore
 
     gekko_solver = True
-except ImportError:
+else:
     gekko_solver = False
     gekko = None
     GEKKO = None

adijif/system.py

@@ -330,7 +330,8 @@ class system(SystemPLL, system_draw):
 
             # Setup external sysref PLLs
             for pll in self._plls_sysref:
-                pll._setup(pll._ref)
+                if not isinstance(pll._ref, clockc):
+                    pll._setup(pll._ref)
 
             for conv in convs:
                 if conv._nested:  # MxFE, Transceivers
@@ -368,6 +369,20 @@ class system(SystemPLL, system_draw):
                 if conv.name + "_ref_clk" in config:
                     raise Exception("Duplicate converter names found")
 
+                # Setup sysref generator is separate (ADF4030) and driven by clock-chip
+                for pll_sr in self._plls_sysref:
+                    if isinstance(pll._ref, clockc):
+                        for name in pll_sr._connected_to_output:
+                            if name == conv.name:
+                                # Get clock from clockchip
+                                if conv._nested:
+                                    raise Exception("Nested converters not supported")
+                            else:
+                                config, clock_names = self._get_ref_clock(
+                                    pll_sr, config, clock_names
+                                )
+                                pll_sr._setup(config[pll_sr.name + "_ref_clk"])
+
                 # Ask clock chip for converter ref
                 config, clock_names = self._get_ref_clock(conv, config, clock_names)
                 config, sys_ref_names = self._get_sysref_clock(

adijif/tools/explorer/cli.py

@@ -0,0 +1,36 @@
+"""CLI entry point for PyADI-JIF Tools Explorer."""
+
+import os
+import sys
+from typing import Optional
+
+from streamlit.web import cli as stcli
+
+
+def run_streamlit(args: Optional[list[str]] = None) -> None:
+    """Run the Streamlit tools explorer app."""
+    # Get the directory where this file is located
+    current_dir = os.path.dirname(os.path.abspath(__file__))
+    main_file = os.path.join(current_dir, "main.py")
+
+    # Get arguments from sys.argv if not provided
+    if args is None:
+        args = sys.argv[1:]
+
+    # Set up sys.argv for streamlit
+    sys.argv = [
+        "streamlit",
+        "run",
+        main_file,
+        "--logger.level=error",
+        "--browser.gatherUsageStats=false",
+        "--server.showEmailPrompt=false",
+    ] + args
+
+    # Run streamlit
+    sys.exit(stcli.main())
+
+
+if __name__ == "__main__":
+    args = sys.argv[1:]
+    run_streamlit(args)

adijif/tools/explorer/main.py

@@ -0,0 +1,41 @@
+"""Main entry point for PyADI-JIF Tools Explorer Streamlit application."""
+
+import logging
+import os
+from typing import Optional
+
+import streamlit as st
+from src.pages import PAGE_MAP
+from src.utils import add_custom_css
+
+# from src.state import provide_state
+
+
+# Global logging configuration
+logging.basicConfig(level=logging.ERROR)
+
+# Configure page settings - must be first Streamlit command
+st.set_page_config(
+    page_title="PyADI-JIF Tools Explorer",
+    page_icon=os.path.join(os.path.dirname(__file__), "PyADI-JIF_logo.png"),
+    initial_sidebar_state="expanded",
+)
+
+# Apply custom CSS to main page and sidebar
+add_custom_css()
+
+
+# @provide_state()
+def main(state: Optional[object] = None) -> None:
+    """Run the main Streamlit application."""
+    logo_image = os.path.join(os.path.dirname(__file__), "PyADI-JIF_logo.png")
+    st.sidebar.image(logo_image)
+    st.sidebar.title("Tools Explorer")
+    current_page = st.sidebar.radio(
+        "Select a Tool", list(PAGE_MAP), label_visibility="hidden"
+    )
+    PAGE_MAP[current_page](state=state).write()
+
+
+if __name__ == "__main__":
+    main()

adijif/tools/explorer/src/pages/__init__.py

@@ -0,0 +1,16 @@
+"""Page definitions for PyADI-JIF Tools Explorer."""
+
+from typing import Dict, Type
+
+from ..utils import Page
+from .clockconfigurator import ClockConfigurator
+from .jesdmodeselector import JESDModeSelector
+from .systemconfigurator import SystemConfigurator
+
+PAGE_MAP: Dict[str, Type[Page]] = {
+    "JESD204 Mode Selector": JESDModeSelector,
+    "Clock Configurator": ClockConfigurator,
+    "System Configurator": SystemConfigurator,
+}
+
+__all__ = ["PAGE_MAP"]

adijif/tools/explorer/src/pages/clockconfigurator.py

@@ -0,0 +1,193 @@
+"""Clock configurator page for PyADI-JIF Tools Explorer."""
+
+import logging
+from typing import Optional
+
+import streamlit as st
+
+from adijif.clocks import supported_parts as sp
+
+from ..utils import Page
+
+try:
+    import adidt as dt
+except ImportError:
+    dt = None
+
+log = logging.getLogger(__name__)
+log.setLevel(logging.ERROR)
+
+# Parse parts and options to skip
+options_to_skip = ["list_references_available", "d_syspulse"]
+parts_to_ignore = ["ad9545", "ad9523_1"]
+sp = [p for p in sp if p not in parts_to_ignore]
+sp = [p for p in sp if p != "hmc7044"]
+sp.insert(0, "hmc7044")
+
+
+class ClockConfigurator(Page):
+    """Clock configurator tool page."""
+
+    def __init__(self, state: Optional[object]) -> None:
+        """Initialize clock configurator page.
+
+        Args:
+            state: Application state object
+        """
+        self.state = state
+
+    def write(self) -> None:
+        """Render the clock configurator page."""
+        st.title("Clock Configurator")
+        # sp = ["hmc7044"]
+
+        sb = st.selectbox(
+            label="Select a part",
+            options=sp,
+            format_func=lambda x: x.upper().replace("_", "-"),
+        )
+
+        with st.expander("Clock Inputs and Outputs", expanded=True):
+            reference = st.number_input(
+                "Reference Clock",
+                value=125000000,
+                min_value=1,
+                max_value=int(1e9),
+                step=1,
+            )
+
+            with st.container(border=True):
+                num_outputs = st.number_input(
+                    "Number of Clock Outputs",
+                    value=2,
+                    min_value=1,
+                    max_value=10,
+                    step=1,
+                )
+                outputs = []
+                output_names = []
+                for i in range(num_outputs):
+                    columns = st.columns(2)
+                    with columns[0]:
+                        outputs.append(
+                            st.number_input(
+                                f"Output Clock {i+1}",
+                                value=125000000,
+                                min_value=1,
+                                max_value=int(1e9),
+                                step=1,
+                            )
+                        )
+                    with columns[1]:
+                        output_names.append(
+                            st.text_input(f"Output Clock Name {i+1}", f"CLK{i+1}")
+                        )
+
+        import adijif  # noqa: F401
+
+        class_def = eval(f"adijif.{sb}")  # noqa: S307
+        props = dir(class_def)
+
+        props = [p for p in props if not p.startswith("__")]
+        props = [p for p in props if not p.startswith("_")]
+        configurable_props = [
+            p.replace("_available", "") for p in props if "_available" in p
+        ]
+
+        prop_and_options = {}
+        for prop in configurable_props:
+            if prop in options_to_skip or prop + "_available" not in props:
+                continue
+            prop_and_options[prop] = getattr(class_def, prop + "_available")
+
+        selections = {}
+        with st.expander("Internal Clock Configuration"):
+            for prop, options in prop_and_options.items():
+                prop_docstring = getattr(class_def, prop).__doc__
+                with st.container(border=True):
+                    label = f"""
+                    {prop} : {prop_docstring}"""
+                    if len(options) > 16:
+                        v_min, v_max = min(options), max(options)
+                        start, end = st.select_slider(
+                            label, options, value=(v_min, v_max)
+                        )
+                        selections[prop] = {"start": start, "end": end}
+                    else:
+                        selections[prop] = st.multiselect(label, options)
+
+        clk_chip = eval(f"adijif.{sb}()")  # noqa: S307
+
+        for prop, values in selections.items():
+            if isinstance(values, dict):
+                props_available = getattr(clk_chip, prop + "_available")
+                if (
+                    min(props_available) == values["start"]
+                    and max(props_available) == values["end"]
+                ):
+                    continue
+                picked = [
+                    v for v in props_available if values["start"] <= v <= values["end"]
+                ]
+                setattr(clk_chip, prop, picked)
+            else:
+                if not values:
+                    continue
+                setattr(clk_chip, prop, values)
+
+        output_clocks = outputs
+        output_clocks = list(map(int, output_clocks))  # force to be ints
+
+        # Remove duplicates
+        output_clocks_filtered = output_clocks
+        output_names_filtered = output_names
+
+        clk_chip.set_requested_clocks(
+            reference, output_clocks_filtered, output_names_filtered
+        )
+
+        try:
+            clk_chip.solve()
+            o = clk_chip.get_config()
+            log.info("Solution found")
+            log.info(o)
+
+            # if dt:
+            #     columns_results = st.columns(2)
+
+            #     with columns_results[0]:
+            #         with st.expander("Found Configuration"):
+            #             st.write(o)
+
+            #     with columns_results[1]:
+            #         if sb == "hmc7044":
+
+            #             clk = dt.hmc7044_dt(offline=True)
+            #             dtsi = clk.map_config_to_fragment(o)
+            #             with st.expander("Device Tree Fragment"):
+            #                 st.code(dtsi)
+            # else:
+            #     with st.expander("Found Configuration"):
+            #         st.write(o)
+
+            config_out = o
+            image_data = clk_chip.draw()
+
+            warning = False
+
+        except Exception as e:
+            log.warning(e)
+
+            warning = True
+
+        with st.expander("Found Configuration", expanded=True):
+            if warning:
+                st.warning("No valid configuration found")
+            else:
+                st.write(config_out)
+
+        with st.expander("Diagram", expanded=True):
+            if warning:
+                st.warning("No diagram to show")
+            else:
+                st.image(image_data, width="stretch")