peakrdl-busdecoder 0.2.0__py3-none-any.whl

peakrdl_busdecoder/identifier_filter.py

@@ -0,0 +1,263 @@
+# All SystemVerilog 2017 keywords
+SV_KEYWORDS = {
+    "accept_on",
+    "alias",
+    "always",
+    "always_comb",
+    "always_ff",
+    "always_latch",
+    "and",
+    "assert",
+    "assign",
+    "assume",
+    "automatic",
+    "before",
+    "begin",
+    "bind",
+    "bins",
+    "binsof",
+    "bit",
+    "break",
+    "buf",
+    "bufif0",
+    "bufif1",
+    "byte",
+    "case",
+    "casex",
+    "casez",
+    "cell",
+    "chandle",
+    "checker",
+    "class",
+    "clocking",
+    "cmos",
+    "config",
+    "const",
+    "constraint",
+    "context",
+    "continue",
+    "cover",
+    "covergroup",
+    "coverpoint",
+    "cross",
+    "deassign",
+    "default",
+    "defparam",
+    "design",
+    "disable",
+    "dist",
+    "do",
+    "edge",
+    "else",
+    "end",
+    "endcase",
+    "endchecker",
+    "endclass",
+    "endclocking",
+    "endconfig",
+    "endfunction",
+    "endgenerate",
+    "endgroup",
+    "endinterface",
+    "endmodule",
+    "endpackage",
+    "endprimitive",
+    "endprogram",
+    "endproperty",
+    "endspecify",
+    "endsequence",
+    "endtable",
+    "endtask",
+    "enum",
+    "event",
+    "eventually",
+    "expect",
+    "export",
+    "extends",
+    "extern",
+    "final",
+    "first_match",
+    "for",
+    "force",
+    "foreach",
+    "forever",
+    "fork",
+    "forkjoin",
+    "function",
+    "generate",
+    "genvar",
+    "global",
+    "highz0",
+    "highz1",
+    "if",
+    "iff",
+    "ifnone",
+    "ignore_bins",
+    "illegal_bins",
+    "implements",
+    "implies",
+    "import",
+    "incdir",
+    "include",
+    "initial",
+    "inout",
+    "input",
+    "inside",
+    "instance",
+    "int",
+    "integer",
+    "interconnect",
+    "interface",
+    "intersect",
+    "join",
+    "join_any",
+    "join_none",
+    "large",
+    "let",
+    "liblist",
+    "library",
+    "local",
+    "localparam",
+    "logic",
+    "longint",
+    "macromodule",
+    "matches",
+    "medium",
+    "modport",
+    "module",
+    "nand",
+    "negedge",
+    "nettype",
+    "new",
+    "nexttime",
+    "nmos",
+    "nor",
+    "noshowcancelled",
+    "not",
+    "notif0",
+    "notif1",
+    "null",
+    "or",
+    "output",
+    "package",
+    "packed",
+    "parameter",
+    "pmos",
+    "posedge",
+    "primitive",
+    "priority",
+    "program",
+    "property",
+    "protected",
+    "pull0",
+    "pull1",
+    "pulldown",
+    "pullup",
+    "pulsestyle_ondetect",
+    "pulsestyle_onevent",
+    "pure",
+    "rand",
+    "randc",
+    "randcase",
+    "randsequence",
+    "rcmos",
+    "real",
+    "realtime",
+    "ref",
+    "reg",
+    "reject_on",
+    "release",
+    "repeat",
+    "restrict",
+    "return",
+    "rnmos",
+    "rpmos",
+    "rtran",
+    "rtranif0",
+    "rtranif1",
+    "s_always",
+    "s_eventually",
+    "s_nexttime",
+    "s_until",
+    "s_until_with",
+    "scalared",
+    "sequence",
+    "shortint",
+    "shortreal",
+    "showcancelled",
+    "signed",
+    "small",
+    "soft",
+    "solve",
+    "specify",
+    "specparam",
+    "static",
+    "string",
+    "strong",
+    "strong0",
+    "strong1",
+    "struct",
+    "super",
+    "supply0",
+    "supply1",
+    "sync_accept_on",
+    "sync_reject_on",
+    "table",
+    "tagged",
+    "task",
+    "this",
+    "throughout",
+    "time",
+    "timeprecision",
+    "timeunit",
+    "tran",
+    "tranif0",
+    "tranif1",
+    "tri",
+    "tri0",
+    "tri1",
+    "triand",
+    "trior",
+    "trireg",
+    "type",
+    "typedef",
+    "union",
+    "unique",
+    "unique0",
+    "unsigned",
+    "until",
+    "until_with",
+    "untyped",
+    "use",
+    "uwire",
+    "var",
+    "vectored",
+    "virtual",
+    "void",
+    "wait",
+    "wait_order",
+    "wand",
+    "weak",
+    "weak0",
+    "weak1",
+    "while",
+    "wildcard",
+    "wire",
+    "with",
+    "within",
+    "wor",
+    "xnor",
+    "xor",
+}
+
+
+def kw_filter(s: str) -> str:
+    """
+    Make all user identifiers 'safe' and ensure they do not collide with
+    SystemVerilog keywords.
+
+    If an SV keyword is encountered, add an underscore suffix
+    """
+    if s in SV_KEYWORDS:
+        s += "_"
+    return s

peakrdl_busdecoder/listener.py

@@ -0,0 +1,58 @@
+from collections import deque
+
+from systemrdl.node import AddressableNode, RegNode
+from systemrdl.walker import RDLListener, WalkerAction
+
+from .design_state import DesignState
+
+
+class BusDecoderListener(RDLListener):
+    def __init__(self, ds: DesignState) -> None:
+        self._array_stride_stack: deque[int] = deque()  # Tracks nested array strides
+        self._ds = ds
+        self._depth = 0
+
+    def should_skip_node(self, node: AddressableNode) -> bool:
+        """Check if this node should be skipped (not decoded)."""
+        # Check if current depth exceeds max depth
+        if self._depth > self._ds.max_decode_depth:
+            return True
+
+        # Check if this node only contains external addressable children
+        if node != self._ds.top_node and not isinstance(node, RegNode):
+            if any(isinstance(c, AddressableNode) for c in node.children()) and all(
+                c.external for c in node.children() if isinstance(c, AddressableNode)
+            ):
+                return True
+
+        return False
+
+    def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
+        if node.array_dimensions:
+            assert node.array_stride is not None, "Array stride should be defined for arrayed components"
+            current_stride = node.array_stride
+            self._array_stride_stack.append(current_stride)
+
+            # Work backwards from rightmost to leftmost dimension (fastest to slowest changing)
+            # Each dimension's stride is the product of its size and the previous dimension's stride
+            for dim in node.array_dimensions[-1:0:-1]:
+                current_stride = current_stride * dim
+                self._array_stride_stack.appendleft(current_stride)
+
+        self._depth += 1
+
+        # Check if we should skip this node's descendants
+        if self.should_skip_node(node):
+            return WalkerAction.SkipDescendants
+
+        return WalkerAction.Continue
+
+    def exit_AddressableComponent(self, node: AddressableNode) -> None:
+        if node.array_dimensions:
+            for _ in node.array_dimensions:
+                self._array_stride_stack.pop()
+
+        self._depth -= 1
+
+    def __str__(self) -> str:
+        return ""

peakrdl_busdecoder/module_tmpl.sv

@@ -0,0 +1,79 @@
+//==========================================================
+//  Module: {{ds.module_name}}
+//  Description: CPU Interface Bus Decoder
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: {{current_date}}
+//  Version: {{version}}
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+module {{ds.module_name}}
+{%- if cpuif.parameters %} #(
+    {{cpuif.parameters|join(",\n")|indent(4)}}
+) {%- endif %} (
+    {{cpuif.port_declaration|indent(4)}}
+);
+    //--------------------------------------------------------------------------
+    // CPU Bus interface logic
+    //--------------------------------------------------------------------------
+    logic cpuif_req;
+    logic cpuif_wr_en;
+    logic cpuif_rd_en;
+    logic [{{cpuif.addr_width-1}}:0] cpuif_wr_addr;
+    logic [{{cpuif.addr_width-1}}:0] cpuif_rd_addr;
+
+    logic cpuif_wr_ack;
+    logic cpuif_wr_err;
+    logic [{{cpuif.data_width-1}}:0] cpuif_wr_data;
+    logic [{{cpuif.data_width//8-1}}:0] cpuif_wr_byte_en;
+
+    logic cpuif_rd_ack;
+    logic cpuif_rd_err;
+    logic [{{cpuif.data_width-1}}:0] cpuif_rd_data;
+
+    //--------------------------------------------------------------------------
+    // Child instance signals
+    //--------------------------------------------------------------------------
+    {{cpuif_select|walk|indent(4)}}
+    cpuif_sel_t cpuif_wr_sel;
+    cpuif_sel_t cpuif_rd_sel;
+
+    //--------------------------------------------------------------------------
+    // Slave <-> Internal CPUIF <-> Master
+    //--------------------------------------------------------------------------
+    {{cpuif.get_implementation()|indent(4)}}
+
+    //--------------------------------------------------------------------------
+    // Write Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all write select signals to 0
+        cpuif_wr_sel = '0;
+
+        if (cpuif_req && cpuif_wr_en) begin
+            // A write request is pending
+            {{cpuif_decode|walk(flavor=cpuif_decode_flavor.WRITE)|indent(12)}}
+        end else begin
+            // No write request, all select signals remain 0
+        end
+    end
+
+    //--------------------------------------------------------------------------
+    // Read Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all read select signals to 0
+        cpuif_rd_sel = '0;
+
+        if (cpuif_req && cpuif_rd_en) begin
+            // A read request is pending
+            {{cpuif_decode|walk(flavor=cpuif_decode_flavor.READ)|indent(12)}}
+        end else begin
+            // No read request, all select signals remain 0
+        end
+    end
+endmodule
+{# (eof newline anchor) #}

peakrdl_busdecoder/package_tmpl.sv

@@ -0,0 +1,21 @@
+//==========================================================
+//  Package: {{ds.package_name}}
+//  Description: CPU Interface Bus Decoder Package
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: {{current_date}}
+//  Version: {{version}}
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+package {{ds.package_name}};
+    localparam {{ds.module_name.upper()}}_DATA_WIDTH = {{ds.cpuif_data_width}};
+    localparam {{ds.module_name.upper()}}_MIN_ADDR_WIDTH = {{ds.addr_width}};
+    localparam {{ds.module_name.upper()}}_SIZE = {{SVInt(ds.top_node.size)}};
+{%- for child in cpuif.addressable_children %}
+    localparam {{ds.module_name.upper()}}_{{child.inst_name.upper()}}_ADDR_WIDTH = {{child.size|clog2}};
+{%- endfor %}
+endpackage
+{# (eof newline anchor) #}

peakrdl_busdecoder/struct_gen.py

@@ -0,0 +1,57 @@
+from collections import deque
+
+from systemrdl.node import AddressableNode
+from systemrdl.walker import WalkerAction
+
+from .body import Body, StructBody
+from .design_state import DesignState
+from .identifier_filter import kw_filter as kwf
+from .listener import BusDecoderListener
+
+
+class StructGenerator(BusDecoderListener):
+    def __init__(
+        self,
+        ds: DesignState,
+    ) -> None:
+        super().__init__(ds)
+
+        self._stack: deque[Body] = deque()
+        self._stack.append(StructBody("cpuif_sel_t", True, True))
+
+    def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
+        action = super().enter_AddressableComponent(node)
+
+        self._skip = False
+        if action == WalkerAction.SkipDescendants:
+            self._skip = True
+
+        if node.children():
+            # Push new body onto stack
+            body = StructBody(f"cpuif_sel_{node.inst_name}_t", True, True)
+            self._stack.append(body)
+
+        return action
+
+    def exit_AddressableComponent(self, node: AddressableNode) -> None:
+        type = "logic"
+
+        if node.children():
+            body = self._stack.pop()
+            if body and isinstance(body, StructBody) and not self._skip:
+                self._stack.appendleft(body)
+                type = body.name
+
+        name = kwf(node.inst_name)
+
+        if node.array_dimensions:
+            for dim in node.array_dimensions:
+                name = f"[{dim - 1}:0]{name}"
+
+        self._stack[-1] += f"{type} {name};"
+
+        super().exit_AddressableComponent(node)
+
+    def __str__(self) -> str:
+        self._stack[-1] += "logic cpuif_err;"
+        return "\n".join(map(str, self._stack))

peakrdl_busdecoder/sv_int.py

@@ -0,0 +1,21 @@
+class SVInt:
+    def __init__(self, value: int, width: int | None = None) -> None:
+        self.value = value
+        self.width = width
+
+    def __str__(self) -> str:
+        if self.width is not None:
+            # Explicit width
+            return f"{self.width}'h{self.value:x}"
+        elif self.value.bit_length() > 32:
+            # SV standard only enforces that unsized literals shall be at least 32-bits
+            # To support larger literals, they need to be sized explicitly
+            return f"{self.value.bit_length()}'h{self.value:x}"
+        else:
+            return f"'h{self.value:x}"
+
+    def __add__(self, other: "SVInt") -> "SVInt":
+        if self.width is not None and other.width is not None:
+            return SVInt(self.value + other.value, max(self.width, other.width))
+        else:
+            return SVInt(self.value + other.value, None)

peakrdl_busdecoder/udps/__init__.py

@@ -0,0 +1,5 @@
+from systemrdl.udp import UDPDefinition
+
+ALL_UDPS: list[type[UDPDefinition]] = []
+
+__all__ = ["ALL_UDPS"]

peakrdl_busdecoder/utils.py

@@ -0,0 +1,80 @@
+import re
+from re import Match
+
+from systemrdl.node import AddrmapNode, Node
+from systemrdl.rdltypes.references import PropertyReference
+
+from .identifier_filter import kw_filter as kwf
+
+
+def get_indexed_path(
+    top_node: Node, target_node: Node, indexer: str = "i", skip_kw_filter: bool = False
+) -> str:
+    """
+    Get the relative path from top_node to target_node, replacing any unknown
+    array indexes with incrementing iterators (i0, i1, ...).
+    """
+    path = target_node.get_rel_path(top_node, empty_array_suffix="[!]")
+
+    # replace unknown indexes with incrementing iterators i0, i1, ...
+    class ReplaceUnknown:
+        def __init__(self) -> None:
+            self.i = 0
+
+        def __call__(self, match: Match[str]) -> str:
+            s = f"{indexer}{self.i}"
+            self.i += 1
+            return s
+
+    path = re.sub(r"!", ReplaceUnknown(), path)
+
+    # Sanitize any SV keywords
+    def kw_filter_repl(m: Match[str]) -> str:
+        return kwf(m.group(0))
+
+    if not skip_kw_filter:
+        path = re.sub(r"\w+", kw_filter_repl, path)
+
+    return path
+
+
+def clog2(n: int) -> int:
+    return (n - 1).bit_length()
+
+
+def is_pow2(x: int) -> bool:
+    return (x > 0) and ((x & (x - 1)) == 0)
+
+
+def roundup_pow2(x: int) -> int:
+    return 1 << (x - 1).bit_length()
+
+
+def ref_is_internal(top_node: AddrmapNode, ref: Node | PropertyReference) -> bool:
+    """
+    Determine whether the reference is internal to the top node.
+
+    For the sake of this exporter, root signals are treated as internal.
+    """
+    current_node: Node | None
+    if isinstance(ref, PropertyReference):
+        current_node = ref.node
+    else:
+        current_node = ref
+
+    # pyrefly: ignore[bad-assignment] - false positive due to circular type checking
+    while current_node is not None:
+        if current_node == top_node:
+            # reached top node without finding any external components
+            # is internal!
+            return True
+
+        if current_node.external:
+            # not internal!
+            return False
+
+        current_node = current_node.parent
+
+    # A root signal was referenced, which dodged the top addrmap
+    # This is considered internal for this exporter
+    return True