peakrdl-busdecoder 0.2.0__py3-none-any.whl

peakrdl_busdecoder/__init__.py

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+from .exporter import BusDecoderExporter
+
+__all__ = ["BusDecoderExporter"]

peakrdl_busdecoder/__peakrdl__.py

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+import functools
+from typing import TYPE_CHECKING, Any
+
+from peakrdl.config import schema
+from peakrdl.plugins.entry_points import get_entry_points
+from peakrdl.plugins.exporter import ExporterSubcommandPlugin
+
+from .cpuif import BaseCpuif, apb3, apb4, axi4lite
+from .exporter import BusDecoderExporter
+from .udps import ALL_UDPS
+
+if TYPE_CHECKING:
+    import argparse
+
+    from systemrdl.node import AddrmapNode
+
+
+@functools.lru_cache
+def get_cpuifs(config: list[tuple[str, Any]]) -> dict[str, type[BaseCpuif]]:
+    # All built-in CPUIFs
+    cpuifs: dict[str, type[BaseCpuif]] = {
+        # "passthrough": passthrough.PassthroughCpuif,
+        "apb3": apb3.APB3Cpuif,
+        "apb3-flat": apb3.APB3CpuifFlat,
+        "apb4": apb4.APB4Cpuif,
+        "apb4-flat": apb4.APB4CpuifFlat,
+        "axi4-lite": axi4lite.AXI4LiteCpuif,
+        "axi4-lite-flat": axi4lite.AXI4LiteCpuifFlat,
+    }
+
+    # Load any cpuifs specified via entry points
+    for ep, _ in get_entry_points("peakrdl_busdecoder.cpuif"):
+        name = ep.name
+        cpuif = ep.load()
+        if name in cpuifs:
+            raise RuntimeError(
+                f"A plugin for 'peakrdl-busdecoder' tried to load cpuif '{name}' but it already exists"
+            )
+        if not issubclass(cpuif, BaseCpuif):
+            raise RuntimeError(
+                f"A plugin for 'peakrdl-busdecoder' tried to load cpuif '{name}' but it not a BaseCpuif class"
+            )
+        cpuifs[name] = cpuif
+
+    # Load any CPUIFs via config import
+    for name, cpuif in config:
+        if name in cpuifs:
+            raise RuntimeError(
+                f"A plugin for 'peakrdl-busdecoder' tried to load cpuif '{name}' but it already exists"
+            )
+        if not issubclass(cpuif, BaseCpuif):
+            raise RuntimeError(
+                f"A plugin for 'peakrdl-busdecoder' tried to load cpuif '{name}' but it not a BaseCpuif class"
+            )
+        cpuifs[name] = cpuif
+
+    return cpuifs
+
+
+class Exporter(ExporterSubcommandPlugin):
+    short_desc = "Generate a SystemVerilog bus decoder for splitting CPU interfaces to sub-address spaces"
+
+    udp_definitions = ALL_UDPS
+
+    cfg_schema = {  # noqa: RUF012
+        "cpuifs": {"*": schema.PythonObjectImport()},
+    }
+
+    def get_cpuifs(self) -> dict[str, type[BaseCpuif]]:
+        return get_cpuifs(map(tuple, self.cfg["cpuifs"].items()))
+
+    def add_exporter_arguments(self, arg_group: "argparse.ArgumentParser") -> None:  # type: ignore
+        cpuifs = self.get_cpuifs()
+
+        arg_group.add_argument(
+            "--cpuif",
+            choices=cpuifs.keys(),
+            default="apb4",
+            help="Select the CPU interface protocol to use [apb3]",
+        )
+
+        arg_group.add_argument(
+            "--module-name",
+            metavar="NAME",
+            default=None,
+            help="Override the SystemVerilog module name",
+        )
+
+        arg_group.add_argument(
+            "--package-name",
+            metavar="NAME",
+            default=None,
+            help="Override the SystemVerilog package name",
+        )
+
+        arg_group.add_argument(
+            "--addr-width",
+            type=int,
+            default=None,
+            help="""Override the CPU interface's address width. By default,
+            address width is sized to the contents of the busdecoder.
+            """,
+        )
+
+        arg_group.add_argument(
+            "--unroll",
+            action="store_true",
+            default=False,
+            help="""Unroll arrayed addressable nodes into separate instances in
+            the CPU interface. By default, arrayed nodes are kept as arrays.
+            """,
+        )
+
+        arg_group.add_argument(
+            "--max-decode-depth",
+            type=int,
+            default=1,
+            help="""Maximum depth for address decoder to descend into nested
+            addressable components. Default is 1.
+            """,
+        )
+
+    def do_export(self, top_node: "AddrmapNode", options: "argparse.Namespace") -> None:
+        cpuifs = self.get_cpuifs()
+
+        x = BusDecoderExporter()
+        x.export(
+            top_node,
+            options.output,
+            cpuif_cls=cpuifs[options.cpuif],
+            module_name=options.module_name,
+            package_name=options.package_name,
+            address_width=options.addr_width,
+            cpuif_unroll=options.unroll,
+            max_decode_depth=options.max_decode_depth,
+        )

peakrdl_busdecoder/body/__init__.py

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+from .body import Body, SupportsStr
+from .combinational_body import CombinationalBody
+from .for_loop_body import ForLoopBody
+from .if_body import IfBody
+from .struct_body import StructBody
+
+__all__ = [
+    "Body",
+    "CombinationalBody",
+    "ForLoopBody",
+    "IfBody",
+    "StructBody",
+    "SupportsStr",
+]

peakrdl_busdecoder/body/body.py

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+from typing import Protocol
+
+from typing_extensions import Self
+
+
+class SupportsStr(Protocol):
+    def __str__(self) -> str: ...
+
+
+class Body:
+    def __init__(self) -> None:
+        self.lines: list[SupportsStr] = []
+
+    def __str__(self) -> str:
+        return "\n".join(map(str, self.lines))
+
+    def __add__(self, other: SupportsStr) -> Self:
+        self.lines.append(other)
+        return self
+
+    def __bool__(self) -> bool:
+        return bool(self.lines)

peakrdl_busdecoder/body/combinational_body.py

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+from textwrap import indent
+
+from .body import Body
+
+
+class CombinationalBody(Body):
+    def __str__(self) -> str:
+        return f"""always_comb begin
+{indent(super().__str__(), "    ")}
+end"""

peakrdl_busdecoder/body/for_loop_body.py

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+from textwrap import indent
+
+from .body import Body
+
+
+class ForLoopBody(Body):
+    def __init__(self, type: str, iterator: str, dim: int) -> None:
+        super().__init__()
+        self._type = type
+        self._iterator = iterator
+        self._dim = dim
+
+    def __str__(self) -> str:
+        return f"""for ({self._type} {self._iterator} = 0; {self._iterator} < {self._dim}; {self._iterator}++) begin
+{indent(super().__str__(), "    ")}
+end"""

peakrdl_busdecoder/body/if_body.py

@@ -0,0 +1,91 @@
+from textwrap import indent
+from types import EllipsisType
+
+from typing_extensions import Self
+
+from .body import Body, SupportsStr
+
+
+class IfBody(Body):
+    def __init__(self) -> None:
+        super().__init__()
+        # (None means 'else')
+        self._branches: list[tuple[SupportsStr | None, Body]] = []
+        self._has_else = False
+
+    # --- Item access: if/else-if via condition; else via Ellipsis/None ---
+    def __getitem__(self, condition: SupportsStr | EllipsisType | None) -> Body:
+        if self._has_else:
+            raise RuntimeError("Cannot add branches after an 'else' branch.")
+        if condition is Ellipsis or condition is None:
+            if self._has_else:
+                raise RuntimeError("Only one 'else' branch is allowed.")
+            self._has_else = True
+            b = Body()
+            self._branches.append((None, b))
+            return b
+        # conditional branch
+        b = Body()
+        self._branches.append((condition, b))
+        return b
+
+    # --- In-place or: if/else-if via (cond, Body); else via Body ---
+    def __ior__(self, other: tuple[SupportsStr, Body] | Body) -> Self:
+        if isinstance(other, Body):
+            if self._has_else:
+                raise RuntimeError("Only one 'else' branch is allowed.")
+            if self._has_else or (self._branches and self._branches[-1][0] is None):
+                raise RuntimeError("Cannot add branches after an 'else' branch.")
+            self._branches.append((None, other))
+            self._has_else = True
+            return self
+
+        cond, body = other
+        if self._has_else:
+            raise RuntimeError("Cannot add branches after an 'else' branch.")
+        self._branches.append((cond, body))
+        return self
+
+    # --- Context manager for a branch ---
+    class _BranchCtx:
+        def __init__(self, outer: "IfBody", condition: SupportsStr | None) -> None:
+            self._outer = outer
+            # route through __getitem__ to reuse validation logic
+            self._body = outer[Ellipsis if condition is None else condition]
+
+        def __enter__(self) -> Body:
+            return self._body
+
+        def __exit__(
+            self,
+            exc_type: type[BaseException] | None,
+            exc: BaseException | None,
+            tb: object | None,
+        ) -> bool:
+            return False
+
+    def cm(self, condition: SupportsStr | None) -> "IfBody._BranchCtx":
+        """Use with: with ifb.cm('cond') as b: ...  ; use None for else."""
+        return IfBody._BranchCtx(self, condition)
+
+    # --- Rendering ---
+    def __str__(self) -> str:
+        out: list[str] = []
+        for i, (cond, body) in enumerate(self._branches):
+            if i == 0 and cond is not None:
+                out.append(f"if ({cond}) begin")
+            elif cond is not None:
+                out.append(f"else if ({cond}) begin")
+            else:
+                out.append("else begin")
+            body_str = str(body)
+            if body_str:
+                out.extend(indent(ln, "    ") for ln in body_str.splitlines())
+            out.append("end")
+        return "\n".join(out)
+
+    def __len__(self) -> int:
+        return len(self._branches)
+
+    def __bool__(self) -> bool:
+        return bool(self._branches)

peakrdl_busdecoder/body/struct_body.py

@@ -0,0 +1,25 @@
+from textwrap import indent
+
+from .body import Body
+
+
+class StructBody(Body):
+    def __init__(self, name: str, typedef: bool = False, packed: bool = False) -> None:
+        super().__init__()
+        self._name = name
+        self._typedef = typedef
+        self._packed = packed
+
+    @property
+    def name(self) -> str:
+        return self._name
+
+    def __str__(self) -> str:
+        if self._typedef:
+            return f"""typedef struct {"packed " if self._packed else ""}{{
+{indent(super().__str__(), "    ")}
+}} {self._name};"""
+
+        return f"""struct {{
+{indent(super().__str__(), "    ")}
+}} {self._name};"""

peakrdl_busdecoder/cpuif/__init__.py

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+from .base_cpuif import BaseCpuif
+
+__all__ = ["BaseCpuif"]

peakrdl_busdecoder/cpuif/apb3/__init__.py

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+from .apb3_cpuif import APB3Cpuif
+from .apb3_cpuif_flat import APB3CpuifFlat
+
+__all__ = ["APB3Cpuif", "APB3CpuifFlat"]

peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py

@@ -0,0 +1,67 @@
+from typing import TYPE_CHECKING, overload
+
+from systemrdl.node import AddressableNode
+
+from ...utils import get_indexed_path
+from ..base_cpuif import BaseCpuif
+from .apb3_interface import APB3SVInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
+
+
+class APB3Cpuif(BaseCpuif):
+    template_path = "apb3_tmpl.sv"
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        super().__init__(exp)
+        self._interface = APB3SVInterface(self)
+
+    @property
+    def is_interface(self) -> bool:
+        return self._interface.is_interface
+
+    @property
+    def port_declaration(self) -> str:
+        return self._interface.get_port_declaration("s_apb", "m_apb_")
+
+    @overload
+    def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
+    @overload
+    def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
+    def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
+        return self._interface.signal(signal, node, indexer)
+
+    def fanout(self, node: AddressableNode) -> str:
+        fanout: dict[str, str] = {}
+        fanout[self.signal("PSEL", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        )
+        fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
+        fanout[self.signal("PWRITE", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        )
+        fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
+        fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
+
+        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
+        else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_data"] = "'0"
+        else:
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py

@@ -0,0 +1,68 @@
+from typing import TYPE_CHECKING
+
+from systemrdl.node import AddressableNode
+
+from ...utils import get_indexed_path
+from ..base_cpuif import BaseCpuif
+from .apb3_interface import APB3FlatInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
+
+
+class APB3CpuifFlat(BaseCpuif):
+    template_path = "apb3_tmpl.sv"
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        super().__init__(exp)
+        self._interface = APB3FlatInterface(self)
+
+    @property
+    def is_interface(self) -> bool:
+        return self._interface.is_interface
+
+    @property
+    def port_declaration(self) -> str:
+        return self._interface.get_port_declaration("s_apb_", "m_apb_")
+
+    def signal(
+        self,
+        signal: str,
+        node: AddressableNode | None = None,
+        idx: str | int | None = None,
+    ) -> str:
+        return self._interface.signal(signal, node, idx)
+
+    def fanout(self, node: AddressableNode) -> str:
+        fanout: dict[str, str] = {}
+        fanout[self.signal("PSEL", node)] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        )
+        fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
+        fanout[self.signal("PWRITE", node)] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        )
+        fanout[self.signal("PADDR", node)] = self.signal("PADDR")
+        fanout[self.signal("PWDATA", node)] = "cpuif_wr_data"
+
+        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
+        else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_data"] = "'0"
+        else:
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

peakrdl_busdecoder/cpuif/apb3/apb3_interface.py

@@ -0,0 +1,56 @@
+"""APB3-specific interface implementations."""
+
+from systemrdl.node import AddressableNode
+
+from ..interface import FlatInterface, SVInterface
+
+
+class APB3SVInterface(SVInterface):
+    """APB3 SystemVerilog interface."""
+
+    def get_interface_type(self) -> str:
+        return "apb3_intf"
+
+    def get_slave_name(self) -> str:
+        return "s_apb"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+
+class APB3FlatInterface(FlatInterface):
+    """APB3 flat signal interface."""
+
+    def get_slave_prefix(self) -> str:
+        return "s_apb_"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+    def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
+        return [
+            f"input  logic {slave_prefix}PCLK",
+            f"input  logic {slave_prefix}PRESETn",
+            f"input  logic {slave_prefix}PSEL",
+            f"input  logic {slave_prefix}PENABLE",
+            f"input  logic {slave_prefix}PWRITE",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}PADDR",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PWDATA",
+            f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PRDATA",
+            f"output logic {slave_prefix}PREADY",
+            f"output logic {slave_prefix}PSLVERR",
+        ]
+
+    def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
+        return [
+            f"output logic {self.signal('PCLK', child)}",
+            f"output logic {self.signal('PRESETn', child)}",
+            f"output logic {self.signal('PSEL', child)}",
+            f"output logic {self.signal('PENABLE', child)}",
+            f"output logic {self.signal('PWRITE', child)}",
+            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
+            f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
+            f"input  logic {self.signal('PREADY', child)}",
+            f"input  logic {self.signal('PSLVERR', child)}",
+        ]

peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv

@@ -0,0 +1,33 @@
+{%- if cpuif.is_interface %}
+`ifndef SYNTHESIS
+    initial begin
+        assert_bad_addr_width: assert($bits({{cpuif.signal("PADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("PADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
+        assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
+    end
+`endif
+{% endif -%}
+
+assign cpuif_req   = {{cpuif.signal("PSEL")}};
+assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
+assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
+
+assign cpuif_wr_addr = {{cpuif.signal("PADDR")}};
+assign cpuif_rd_addr = {{cpuif.signal("PADDR")}};
+
+assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
+
+assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
+assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
+assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+
+//--------------------------------------------------------------------------
+// Fanout CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanout|walk(cpuif=cpuif)}}
+
+//--------------------------------------------------------------------------
+// Fanin CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanin|walk(cpuif=cpuif)}}

peakrdl_busdecoder/cpuif/apb4/__init__.py

@@ -0,0 +1,4 @@
+from .apb4_cpuif import APB4Cpuif
+from .apb4_cpuif_flat import APB4CpuifFlat
+
+__all__ = ["APB4Cpuif", "APB4CpuifFlat"]

peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py

@@ -0,0 +1,70 @@
+from typing import TYPE_CHECKING, overload
+
+from systemrdl.node import AddressableNode
+
+from ...utils import get_indexed_path
+from ..base_cpuif import BaseCpuif
+from .apb4_interface import APB4SVInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
+
+
+class APB4Cpuif(BaseCpuif):
+    template_path = "apb4_tmpl.sv"
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        super().__init__(exp)
+        self._interface = APB4SVInterface(self)
+
+    @property
+    def is_interface(self) -> bool:
+        return self._interface.is_interface
+
+    @property
+    def port_declaration(self) -> str:
+        """Returns the port declaration for the APB4 interface."""
+        return self._interface.get_port_declaration("s_apb", "m_apb_")
+
+    @overload
+    def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
+    @overload
+    def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
+    def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
+        return self._interface.signal(signal, node, indexer)
+
+    def fanout(self, node: AddressableNode) -> str:
+        fanout: dict[str, str] = {}
+        fanout[self.signal("PSEL", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        )
+        fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
+        fanout[self.signal("PWRITE", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        )
+        fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
+        fanout[self.signal("PPROT", node, "gi")] = self.signal("PPROT")
+        fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
+        fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en"
+
+        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
+        else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_data"] = "'0"
+        else:
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))