peakrdl-busdecoder 0.2.0__py3-none-any.whl

peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py

@@ -0,0 +1,70 @@
+from typing import TYPE_CHECKING
+
+from systemrdl.node import AddressableNode
+
+from ...utils import get_indexed_path
+from ..base_cpuif import BaseCpuif
+from .apb4_interface import APB4FlatInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
+
+
+class APB4CpuifFlat(BaseCpuif):
+    template_path = "apb4_tmpl.sv"
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        super().__init__(exp)
+        self._interface = APB4FlatInterface(self)
+
+    @property
+    def is_interface(self) -> bool:
+        return self._interface.is_interface
+
+    @property
+    def port_declaration(self) -> str:
+        return self._interface.get_port_declaration("s_apb_", "m_apb_")
+
+    def signal(
+        self,
+        signal: str,
+        node: AddressableNode | None = None,
+        idx: str | int | None = None,
+    ) -> str:
+        return self._interface.signal(signal, node, idx)
+
+    def fanout(self, node: AddressableNode) -> str:
+        fanout: dict[str, str] = {}
+        fanout[self.signal("PSEL", node)] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        )
+        fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
+        fanout[self.signal("PWRITE", node)] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        )
+        fanout[self.signal("PADDR", node)] = self.signal("PADDR")
+        fanout[self.signal("PPROT", node)] = self.signal("PPROT")
+        fanout[self.signal("PWDATA", node)] = "cpuif_wr_data"
+        fanout[self.signal("PSTRB", node)] = "cpuif_wr_byte_en"
+
+        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
+        else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_data"] = "'0"
+        else:
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

peakrdl_busdecoder/cpuif/apb4/apb4_interface.py

@@ -0,0 +1,60 @@
+"""APB4-specific interface implementations."""
+
+from systemrdl.node import AddressableNode
+
+from ..interface import FlatInterface, SVInterface
+
+
+class APB4SVInterface(SVInterface):
+    """APB4 SystemVerilog interface."""
+
+    def get_interface_type(self) -> str:
+        return "apb4_intf"
+
+    def get_slave_name(self) -> str:
+        return "s_apb"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+
+class APB4FlatInterface(FlatInterface):
+    """APB4 flat signal interface."""
+
+    def get_slave_prefix(self) -> str:
+        return "s_apb_"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+    def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
+        return [
+            f"input  logic {slave_prefix}PCLK",
+            f"input  logic {slave_prefix}PRESETn",
+            f"input  logic {slave_prefix}PSEL",
+            f"input  logic {slave_prefix}PENABLE",
+            f"input  logic {slave_prefix}PWRITE",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}PADDR",
+            f"input  logic [2:0] {slave_prefix}PPROT",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PWDATA",
+            f"input  logic [{self.cpuif.data_width // 8 - 1}:0] {slave_prefix}PSTRB",
+            f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PRDATA",
+            f"output logic {slave_prefix}PREADY",
+            f"output logic {slave_prefix}PSLVERR",
+        ]
+
+    def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
+        return [
+            f"output logic {self.signal('PCLK', child)}",
+            f"output logic {self.signal('PRESETn', child)}",
+            f"output logic {self.signal('PSEL', child)}",
+            f"output logic {self.signal('PENABLE', child)}",
+            f"output logic {self.signal('PWRITE', child)}",
+            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
+            f"output logic [2:0] {self.signal('PPROT', child)}",
+            f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
+            f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
+            f"input  logic {self.signal('PREADY', child)}",
+            f"input  logic {self.signal('PSLVERR', child)}",
+        ]

peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv

@@ -0,0 +1,36 @@
+{%- if cpuif.is_interface %}
+`ifndef SYNTHESIS
+    initial begin
+        assert_bad_addr_width: assert($bits({{cpuif.signal("PADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("PADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
+        assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
+    end
+    assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
+        else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+`endif
+{%- endif %}
+
+assign cpuif_req   = {{cpuif.signal("PSEL")}};
+assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
+assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
+
+assign cpuif_wr_addr = {{cpuif.signal("PADDR")}};
+assign cpuif_rd_addr = {{cpuif.signal("PADDR")}};
+
+assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
+assign cpuif_wr_byte_en = {{cpuif.signal("PSTRB")}};
+
+assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
+assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
+assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+
+//--------------------------------------------------------------------------
+// Fanout CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanout|walk(cpuif=cpuif)}}
+
+//--------------------------------------------------------------------------
+// Fanin CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanin|walk(cpuif=cpuif)}}

peakrdl_busdecoder/cpuif/axi4lite/__init__.py

@@ -0,0 +1,4 @@
+from .axi4_lite_cpuif import AXI4LiteCpuif
+from .axi4_lite_cpuif_flat import AXI4LiteCpuifFlat
+
+__all__ = ["AXI4LiteCpuif", "AXI4LiteCpuifFlat"]

peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py

@@ -0,0 +1,84 @@
+from typing import TYPE_CHECKING, overload
+
+from systemrdl.node import AddressableNode
+
+from ...utils import get_indexed_path
+from ..base_cpuif import BaseCpuif
+from .axi4lite_interface import AXI4LiteSVInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
+
+
+class AXI4LiteCpuif(BaseCpuif):
+    template_path = "axi4lite_tmpl.sv"
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        super().__init__(exp)
+        self._interface = AXI4LiteSVInterface(self)
+
+    @property
+    def is_interface(self) -> bool:
+        return self._interface.is_interface
+
+    @property
+    def port_declaration(self) -> str:
+        """Returns the port declaration for the AXI4-Lite interface."""
+        return self._interface.get_port_declaration("s_axil", "m_axil_")
+
+    @overload
+    def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
+    @overload
+    def signal(self, signal: str, node: AddressableNode, indexer: str | None = None) -> str: ...
+    def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
+        return self._interface.signal(signal, node, indexer)
+
+    def fanout(self, node: AddressableNode) -> str:
+        fanout: dict[str, str] = {}
+
+        wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+
+        # Write address channel
+        fanout[self.signal("AWVALID", node, "gi")] = wr_sel
+        fanout[self.signal("AWADDR", node, "gi")] = self.signal("AWADDR")
+        fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
+
+        # Write data channel
+        fanout[self.signal("WVALID", node, "gi")] = wr_sel
+        fanout[self.signal("WDATA", node, "gi")] = "cpuif_wr_data"
+        fanout[self.signal("WSTRB", node, "gi")] = "cpuif_wr_byte_en"
+
+        # Write response channel (master -> slave)
+        fanout[self.signal("BREADY", node, "gi")] = self.signal("BREADY")
+
+        # Read address channel
+        fanout[self.signal("ARVALID", node, "gi")] = rd_sel
+        fanout[self.signal("ARADDR", node, "gi")] = self.signal("ARADDR")
+        fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
+
+        # Read data channel (master -> slave)
+        fanout[self.signal("RREADY", node, "gi")] = self.signal("RREADY")
+
+        return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
+        else:
+            # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
+            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+
+        return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_data"] = "'0"
+        else:
+            fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
+
+        return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())

peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py

@@ -0,0 +1,86 @@
+from typing import TYPE_CHECKING, overload
+
+from systemrdl.node import AddressableNode
+
+from ...utils import get_indexed_path
+from ..base_cpuif import BaseCpuif
+from .axi4lite_interface import AXI4LiteFlatInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
+
+
+class AXI4LiteCpuifFlat(BaseCpuif):
+    """Verilator-friendly variant that flattens the AXI4-Lite interface ports."""
+
+    template_path = "axi4lite_tmpl.sv"
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        super().__init__(exp)
+        self._interface = AXI4LiteFlatInterface(self)
+
+    @property
+    def is_interface(self) -> bool:
+        return self._interface.is_interface
+
+    @property
+    def port_declaration(self) -> str:
+        """Returns the port declaration for the AXI4-Lite interface."""
+        return self._interface.get_port_declaration("s_axil_", "m_axil_")
+
+    @overload
+    def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
+    @overload
+    def signal(self, signal: str, node: AddressableNode, indexer: str | None = None) -> str: ...
+    def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
+        return self._interface.signal(signal, node, indexer)
+
+    def fanout(self, node: AddressableNode) -> str:
+        fanout: dict[str, str] = {}
+
+        wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+
+        # Write address channel
+        fanout[self.signal("AWVALID", node, "gi")] = wr_sel
+        fanout[self.signal("AWADDR", node, "gi")] = self.signal("AWADDR")
+        fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
+
+        # Write data channel
+        fanout[self.signal("WVALID", node, "gi")] = wr_sel
+        fanout[self.signal("WDATA", node, "gi")] = "cpuif_wr_data"
+        fanout[self.signal("WSTRB", node, "gi")] = "cpuif_wr_byte_en"
+
+        # Write response channel (master -> slave)
+        fanout[self.signal("BREADY", node, "gi")] = self.signal("BREADY")
+
+        # Read address channel
+        fanout[self.signal("ARVALID", node, "gi")] = rd_sel
+        fanout[self.signal("ARADDR", node, "gi")] = self.signal("ARADDR")
+        fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
+
+        # Read data channel (master -> slave)
+        fanout[self.signal("RREADY", node, "gi")] = self.signal("RREADY")
+
+        return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
+        else:
+            # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
+            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+
+        return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_data"] = "'0"
+        else:
+            fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
+
+        return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())

peakrdl_busdecoder/cpuif/axi4lite/axi4lite_interface.py

@@ -0,0 +1,84 @@
+"""AXI4-Lite-specific interface implementations."""
+
+from systemrdl.node import AddressableNode
+
+from ..interface import FlatInterface, SVInterface
+
+
+class AXI4LiteSVInterface(SVInterface):
+    """AXI4-Lite SystemVerilog interface."""
+
+    def get_interface_type(self) -> str:
+        return "axi4lite_intf"
+
+    def get_slave_name(self) -> str:
+        return "s_axil"
+
+    def get_master_prefix(self) -> str:
+        return "m_axil_"
+
+
+class AXI4LiteFlatInterface(FlatInterface):
+    """AXI4-Lite flat signal interface."""
+
+    def get_slave_prefix(self) -> str:
+        return "s_axil_"
+
+    def get_master_prefix(self) -> str:
+        return "m_axil_"
+
+    def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
+        return [
+            # Write address channel
+            f"input  logic {slave_prefix}AWVALID",
+            f"output logic {slave_prefix}AWREADY",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}AWADDR",
+            f"input  logic [2:0] {slave_prefix}AWPROT",
+            # Write data channel
+            f"input  logic {slave_prefix}WVALID",
+            f"output logic {slave_prefix}WREADY",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {slave_prefix}WDATA",
+            f"input  logic [{self.cpuif.data_width // 8 - 1}:0] {slave_prefix}WSTRB",
+            # Write response channel
+            f"output logic {slave_prefix}BVALID",
+            f"input  logic {slave_prefix}BREADY",
+            f"output logic [1:0] {slave_prefix}BRESP",
+            # Read address channel
+            f"input  logic {slave_prefix}ARVALID",
+            f"output logic {slave_prefix}ARREADY",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}ARADDR",
+            f"input  logic [2:0] {slave_prefix}ARPROT",
+            # Read data channel
+            f"output logic {slave_prefix}RVALID",
+            f"input  logic {slave_prefix}RREADY",
+            f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}RDATA",
+            f"output logic [1:0] {slave_prefix}RRESP",
+        ]
+
+    def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
+        return [
+            # Write address channel
+            f"output logic {self.signal('AWVALID', child)}",
+            f"input  logic {self.signal('AWREADY', child)}",
+            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('AWADDR', child)}",
+            f"output logic [2:0] {self.signal('AWPROT', child)}",
+            # Write data channel
+            f"output logic {self.signal('WVALID', child)}",
+            f"input  logic {self.signal('WREADY', child)}",
+            f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('WDATA', child)}",
+            f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('WSTRB', child)}",
+            # Write response channel
+            f"input  logic {self.signal('BVALID', child)}",
+            f"output logic {self.signal('BREADY', child)}",
+            f"input  logic [1:0] {self.signal('BRESP', child)}",
+            # Read address channel
+            f"output logic {self.signal('ARVALID', child)}",
+            f"input  logic {self.signal('ARREADY', child)}",
+            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('ARADDR', child)}",
+            f"output logic [2:0] {self.signal('ARPROT', child)}",
+            # Read data channel
+            f"input  logic {self.signal('RVALID', child)}",
+            f"output logic {self.signal('RREADY', child)}",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('RDATA', child)}",
+            f"input  logic [1:0] {self.signal('RRESP', child)}",
+        ]

peakrdl_busdecoder/cpuif/axi4lite/axi4lite_tmpl.sv

@@ -0,0 +1,60 @@
+{%- if cpuif.is_interface -%}
+`ifndef SYNTHESIS
+    initial begin
+        // Width checks (AXI4-Lite)
+        assert_bad_awaddr_width: assert($bits({{cpuif.signal("AWADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
+            else $error("AWADDR width %0d < MIN_ADDR_WIDTH %0d",
+                        $bits({{cpuif.signal("AWADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
+
+        assert_bad_araddr_width: assert($bits({{cpuif.signal("ARADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
+            else $error("ARADDR width %0d < MIN_ADDR_WIDTH %0d",
+                        $bits({{cpuif.signal("ARADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
+
+        assert_bad_data_width: assert($bits({{cpuif.signal("WDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
+            else $error("WDATA width %0d != DATA_WIDTH %0d",
+                        $bits({{cpuif.signal("WDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
+    end
+
+    // Simple handshake sanity (one-cycle implication; relax/adjust as needed)
+    assert_rd_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
+        {{cpuif.signal("RVALID")}} |-> (^{{cpuif.signal("RRESP")}} !== 1'bx))
+            else $error("RRESP must be a legal AXI response when RVALID is high");
+
+    assert_wr_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
+        {{cpuif.signal("BVALID")}} |-> (^{{cpuif.signal("BRESP")}} !== 1'bx))
+            else $error("BRESP must be a legal AXI response when BVALID is high");
+`endif
+{% endif -%}
+
+
+assign cpuif_req     = {{cpuif.signal("AWVALID")}} | {{cpuif.signal("ARVALID")}};
+assign cpuif_wr_en   = {{cpuif.signal("AWVALID")}} & {{cpuif.signal("WVALID")}};
+assign cpuif_rd_en   = {{cpuif.signal("ARVALID")}};
+
+assign cpuif_wr_addr = {{cpuif.signal("AWADDR")}};
+assign cpuif_rd_addr = {{cpuif.signal("ARADDR")}};
+
+assign cpuif_wr_data    = {{cpuif.signal("WDATA")}};
+assign cpuif_wr_byte_en = {{cpuif.signal("WSTRB")}};
+
+//
+// Return paths back to AXI master from generic cpuif_*
+// Read: ack=RVALID, err=RRESP[1] (SLVERR/DECERR), data=RDATA
+//
+assign {{cpuif.signal("RDATA")}}  = cpuif_rd_data;
+assign {{cpuif.signal("RVALID")}} = cpuif_rd_ack;
+assign {{cpuif.signal("RRESP")}}  = (cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err) ? 2'b10 : 2'b00;
+
+// Write: ack=BVALID, err=BRESP[1]
+assign {{cpuif.signal("BVALID")}} = cpuif_wr_ack;
+assign {{cpuif.signal("BRESP")}}  = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpuif_rd_sel.cpuif_err) ? 2'b10 : 2'b00;
+
+//--------------------------------------------------------------------------
+// Fanout CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanout|walk(cpuif=cpuif)}}
+
+//--------------------------------------------------------------------------
+// Fanin CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanin|walk(cpuif=cpuif)}}

peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -0,0 +1,118 @@
+import inspect
+import os
+from typing import TYPE_CHECKING
+
+import jinja2 as jj
+from systemrdl.node import AddressableNode
+
+from ..utils import clog2, get_indexed_path, is_pow2, roundup_pow2
+from .fanin_gen import FaninGenerator
+from .fanout_gen import FanoutGenerator
+
+if TYPE_CHECKING:
+    from ..exporter import BusDecoderExporter
+
+
+class BaseCpuif:
+    # Path is relative to the location of the class that assigns this variable
+    template_path = ""
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        self.exp = exp
+        self.reset = exp.ds.top_node.cpuif_reset
+        self.unroll = exp.ds.cpuif_unroll
+
+    @property
+    def addressable_children(self) -> list[AddressableNode]:
+        return [
+            child
+            for child in self.exp.ds.top_node.children(unroll=self.unroll)
+            if isinstance(child, AddressableNode)
+        ]
+
+    @property
+    def addr_width(self) -> int:
+        return self.exp.ds.addr_width
+
+    @property
+    def data_width(self) -> int:
+        return self.exp.ds.cpuif_data_width
+
+    @property
+    def data_width_bytes(self) -> int:
+        return self.data_width // 8
+
+    @property
+    def port_declaration(self) -> str:
+        raise NotImplementedError()
+
+    @property
+    def parameters(self) -> list[str]:
+        """
+        Optional list of additional parameters this CPU interface provides to
+        the module's definition
+        """
+        array_parameters = [
+            f"localparam N_{child.inst_name.upper()}S = {child.n_elements}"
+            for child in self.addressable_children
+            if self.check_is_array(child)
+        ]
+        return array_parameters
+
+    def _get_template_path_class_dir(self) -> str:
+        """
+        Traverse up the MRO and find the first class that explicitly assigns
+        template_path. Returns the directory that contains the class definition.
+        """
+        for cls in inspect.getmro(self.__class__):
+            if "template_path" in cls.__dict__:
+                class_dir = os.path.dirname(inspect.getfile(cls))
+                return class_dir
+        raise RuntimeError
+
+    def check_is_array(self, node: AddressableNode) -> bool:
+        # When unrolling is enabled, children(unroll=True) returns individual
+        # array elements with current_idx set. These should NOT be treated as arrays.
+        if self.unroll and hasattr(node, "current_idx") and node.current_idx is not None:
+            return False
+        return node.is_array
+
+    def get_implementation(self) -> str:
+        class_dir = self._get_template_path_class_dir()
+        loader = jj.FileSystemLoader(class_dir)
+        jj_env = jj.Environment(
+            loader=loader,
+            undefined=jj.StrictUndefined,
+        )
+        jj_env.tests["array"] = self.check_is_array  # type: ignore
+        jj_env.filters["clog2"] = clog2  # type: ignore
+        jj_env.filters["is_pow2"] = is_pow2  # type: ignore
+        jj_env.filters["roundup_pow2"] = roundup_pow2  # type: ignore
+        jj_env.filters["address_slice"] = self.get_address_slice  # type: ignore
+        jj_env.filters["get_path"] = lambda x: get_indexed_path(self.exp.ds.top_node, x, "i")  # type: ignore
+        jj_env.filters["walk"] = self.exp.walk  # type: ignore
+
+        context = {  # type: ignore
+            "cpuif": self,
+            "ds": self.exp.ds,
+            "fanout": FanoutGenerator,
+            "fanin": FaninGenerator,
+        }
+
+        template = jj_env.get_template(self.template_path)
+        return template.render(context)
+
+    def get_address_slice(self, node: AddressableNode, cpuif_addr: str = "cpuif_addr") -> str:
+        addr = node.raw_absolute_address - self.exp.ds.top_node.raw_absolute_address
+        size = node.size
+
+        return f"({cpuif_addr} - 'h{addr:x})[{clog2(size) - 1}:0]"
+
+    def fanout(self, node: AddressableNode) -> str:
+        raise NotImplementedError
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        raise NotImplementedError
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        raise NotImplementedError

peakrdl_busdecoder/cpuif/fanin_gen.py

@@ -0,0 +1,64 @@
+from collections import deque
+from typing import TYPE_CHECKING
+
+from systemrdl.node import AddressableNode
+from systemrdl.walker import WalkerAction
+
+from ..body import Body, CombinationalBody, ForLoopBody, IfBody
+from ..design_state import DesignState
+from ..listener import BusDecoderListener
+from ..utils import get_indexed_path
+
+if TYPE_CHECKING:
+    from .base_cpuif import BaseCpuif
+
+
+class FaninGenerator(BusDecoderListener):
+    def __init__(self, ds: DesignState, cpuif: "BaseCpuif") -> None:
+        super().__init__(ds)
+        self._cpuif = cpuif
+
+        self._stack: deque[Body] = deque()
+        cb = CombinationalBody()
+        cb += cpuif.fanin()
+        cb += cpuif.readback()
+        self._stack.append(cb)
+
+    def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
+        action = super().enter_AddressableComponent(node)
+
+        if node.array_dimensions:
+            for i, dim in enumerate(node.array_dimensions):
+                fb = ForLoopBody(
+                    "int",
+                    f"i{i}",
+                    dim,
+                )
+                self._stack.append(fb)
+
+        ifb = IfBody()
+        with ifb.cm(
+            f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)} || cpuif_wr_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}"
+        ) as b:
+            b += self._cpuif.fanin(node)
+        self._stack[-1] += ifb
+
+        ifb = IfBody()
+        with ifb.cm(f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}") as b:
+            b += self._cpuif.readback(node)
+        self._stack[-1] += ifb
+
+        return action
+
+    def exit_AddressableComponent(self, node: AddressableNode) -> None:
+        if node.array_dimensions:
+            for _ in node.array_dimensions:
+                b = self._stack.pop()
+                if not b:
+                    continue
+                self._stack[-1] += b
+
+        super().exit_AddressableComponent(node)
+
+    def __str__(self) -> str:
+        return "\n".join(map(str, self._stack))