lambdapdk 0.1.56__py3-none-any.whl → 0.2.0rc1__py3-none-any.whl

lambdapdk/ihp130/libs/sg13g2_stdcell.py

@@ -1,139 +1,117 @@
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
-from lambdapdk.ihp130 import register_ihp130_data_source
+from pathlib import Path
 
+from lambdapdk import LambdaLibrary
+from lambdapdk.ihp130 import IHP130PDK, _IHP130Path
 
-def setup():
+
+class _IHP130StdCell(LambdaLibrary, _IHP130Path):
     '''
-    Standrad cell library for IHP130
+    Standard cell library for IHP130
     '''
-    libname = 'sg13g2_stdcell'
-    process = 'ihp130'
-    stackup = '5M2TL'
-    libtype = '9t'
-    version = 'r1p0'
-
-    lib = siliconcompiler.Library(libname, package='ihp130')
-    register_ihp130_data_source(lib)
-    register_data_source(lib)
-
-    libdir = os.path.join('lambdapdk', process, 'libs', libname)
-
-    # version
-    lib.set('package', 'version', version)
-
-    # list of stackups supported
-    lib.set('option', 'stackup', stackup)
-
-    # list of pdks supported
-    lib.set('option', 'pdk', process)
-
-    # footprint/type/sites
-    lib.set('asic', 'libarch', libtype)
-    lib.set('asic', 'site', libtype, 'CoreSite')
-
-    # timing
-    lib.add('output', 'typ', 'nldm',
-            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib')
-    lib.add('output', 'fast', 'nldm',
-            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p32V_m40C.lib')
-    lib.add('output', 'slow', 'nldm',
-            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib')
-
-    # lef
-    lib.add('output', stackup, 'lef',
-            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef')
-
-    # gds
-    lib.add('output', stackup, 'gds',
-            'ihp-sg13g2/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds')
-
-    # cdl
-    lib.add('output', stackup, 'cdl',
-            'ihp-sg13g2/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl')
-
-    lib.add('output', 'rtl', 'verilog',
-            'ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v')
-
-    # tie cells
-    lib.add('asic', 'cells', 'tie', ["sg13g2_tiehi",
-                                     "sg13g2_tielo"])
-
-    # hold cells
-    lib.add('asic', 'cells', 'hold', ["sg13g2_dlygate4sd1_1",
-                                      "sg13g2_dlygate4sd2_1",
-                                      "sg13g2_dlygate4sd3_1"])
-
-    # filler
-    lib.add('asic', 'cells', 'filler', ["sg13g2_fill_1",
-                                        "sg13g2_fill_2",
-                                        "sg13g2_fill_4",
-                                        "sg13g2_fill_8"])
-
-    # decap
-    lib.add('asic', 'cells', 'decap', ["sg13g2_decap_4",
-                                       "sg13g2_decap_8"])
-
-    # antenna
-    lib.add('asic', 'cells', 'antenna', ["sg13g2_antennanp"])
-
-    # Dont use
-    lib.add('asic', 'cells', 'dontuse', ["sg13g2_lgcp_1",
-                                         "sg13g2_sighold",
-                                         "sg13g2_slgcp_1",
-                                         "sg13g2_dfrbp_2"])
-
-    # Techmap
-    lib.add('option', 'file', 'yosys_techmap',
-            libdir + '/techmap/yosys/cells_latch.v',
-            package='lambdapdk')
-    lib.add('option', 'file', 'yosys_tbufmap',
-            libdir + '/techmap/yosys/cells_tristatebuf.v',
-            package='lambdapdk')
-
-    # Defaults for OpenROAD tool variables
-    lib.set('option', 'var', 'openroad_place_density', '0.65')
-    lib.set('option', 'var', 'openroad_pad_global_place', '0')
-    lib.set('option', 'var', 'openroad_pad_detail_place', '0')
-    lib.set('option', 'var', 'openroad_macro_place_halo', ['40', '40'])
-    lib.set('option', 'var', 'openroad_macro_place_channel', ['80', '80'])
-
-    lib.set('option', 'file', 'openroad_tapcells', libdir + '/apr/openroad/tapcell.tcl',
-            package='lambdapdk')
-    lib.set('option', 'file', 'openroad_pdngen', libdir + '/apr/openroad/pdngen.tcl',
-            package='lambdapdk')
-    lib.set('option', 'file', 'openroad_global_connect',
-            libdir + '/apr/openroad/global_connect.tcl',
-            package='lambdapdk')
-
-    lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
-    lib.set('option', 'var', 'yosys_abc_constraint_load', "0.017pF")
-    lib.set('option', 'var', 'yosys_driver_cell', "sg13g2_buf_4")
-    lib.set('option', 'var', 'yosys_buffer_cell', "sg13g2_buf_4")
-    lib.set('option', 'var', 'yosys_buffer_input', "A")
-    lib.set('option', 'var', 'yosys_buffer_output', "X")
-    for tool in ('yosys', 'openroad'):
-        lib.set('option', 'var', f'{tool}_tiehigh_cell', "sg13g2_tiehi")
-        lib.set('option', 'var', f'{tool}_tiehigh_port', "L_HI")
-        lib.set('option', 'var', f'{tool}_tielow_cell', "sg13g2_tielo")
-        lib.set('option', 'var', f'{tool}_tielow_port', "L_LO")
-
-    # Bambu setup
-    lib.set('option', 'var', 'bambu_clock_multiplier', "1")  # convert from ns -> ns
-
-    libs = [lib]
-    for libtype in ('stdlib', 'auxlib'):
-        lambda_lib = siliconcompiler.Library(f'lambdalib_{libtype}_{libname}',
-                                             package='lambdapdk')
-        register_data_source(lambda_lib)
-        lambda_lib.add('option', 'ydir', libdir + f'/lambda/{libtype}')
-        libs.append(lambda_lib)
-
-    return libs
-
-
-#########################
-if __name__ == "__main__":
-    lib = setup()
-    lib.write_manifest(f'{lib.top()}.json')
+    def __init__(self, voltage):
+        super().__init__()
+        self.set_name(f"sg13g2_stdcell_{voltage}")
+
+        self.add_asic_pdk(IHP130PDK())
+
+        self.add_asic_site("CoreSite")
+
+        lib_path = Path('lambdapdk', "ihp130", 'libs', "sg13g2_stdcell")
+
+        with self.active_dataroot("ihp130"):
+            if voltage == "1p2V":
+                for corner_name, filename in [
+                        ('slow', 'sg13g2_stdcell_slow_1p08V_125C.lib'),
+                        ('typical', 'sg13g2_stdcell_typ_1p20V_25C.lib'),
+                        ('fast', 'sg13g2_stdcell_fast_1p32V_m40C.lib')]:
+                    with self.active_fileset(f"models.timing.{corner_name}.nldm"):
+                        self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/{filename}")
+                        self.add_asic_libcornerfileset(corner_name, "nldm")
+            else:
+                for corner_name, filename in [
+                        ('slow', 'sg13g2_stdcell_slow_1p35V_125C.lib'),
+                        ('typical', 'sg13g2_stdcell_typ_1p50V_25C.lib'),
+                        ('fast', 'sg13g2_stdcell_fast_1p65V_m40C.lib')]:
+                    with self.active_fileset(f"models.timing.{corner_name}.nldm"):
+                        self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/{filename}")
+                        self.add_asic_libcornerfileset(corner_name, "nldm")
+
+            with self.active_fileset("models.spice"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/spice/sg13g2_stdcell.spice")
+
+        with self.active_dataroot("ihp130"):
+            with self.active_fileset("models.physical"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef")
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("rtl"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v")
+                self.add_asic_aprfileset()
+
+        # tie cells
+        self.add_asic_celllist('tie', ["sg13g2_tiehi",
+                                       "sg13g2_tielo"])
+
+        # hold cells
+        self.add_asic_celllist('hold', ["sg13g2_dlygate4sd1_1",
+                                        "sg13g2_dlygate4sd2_1",
+                                        "sg13g2_dlygate4sd3_1"])
+
+        # filler
+        self.add_asic_celllist('filler', ["sg13g2_fill_1",
+                                          "sg13g2_fill_2",
+                                          "sg13g2_fill_4",
+                                          "sg13g2_fill_8"])
+
+        # decap
+        self.add_asic_celllist('decap', ["sg13g2_decap_4",
+                                         "sg13g2_decap_8"])
+
+        # antenna
+        self.add_asic_celllist('antenna', ["sg13g2_antennanp"])
+
+        # Dont use
+        self.add_asic_celllist('dontuse', ["sg13g2_lgcp_1",
+                                           "sg13g2_sighold",
+                                           "sg13g2_slgcp_1",
+                                           "sg13g2_dfrbp_2"])
+
+        # Setup for yosys
+        with self.active_dataroot("lambdapdk"):
+            self.set_yosys_driver_cell("sg13g2_buf_4")
+            self.set_yosys_buffer_cell("sg13g2_buf_4", "A", "X")
+            self.set_yosys_tielow_cell("sg13g2_tielo", "L_LO")
+            self.set_yosys_tiehigh_cell("sg13g2_tiehi", "L_HI")
+            self.set_yosys_abc(1000, 17)
+            self.set_yosys_tristatebuffer_map(
+                lib_path / "techmap" / "yosys" / "cells_tristatebuf.v")
+            self.add_yosys_tech_map(lib_path / "techmap" / "yosys" / "cells_latch.v")
+
+        # Setup for OpenROAD
+        with self.active_dataroot("lambdapdk"):
+            self.set_openroad_placement_density(0.65)
+            self.set_openroad_tielow_cell("sg13g2_tielo", "L_LO")
+            self.set_openroad_tiehigh_cell("sg13g2_tiehi", "L_HI")
+            self.set_openroad_macro_placement_halo(40, 40)
+            self.set_openroad_tapcells_file(lib_path / "apr" / "openroad" / "tapcell.tcl")
+            self.add_openroad_global_connect_file(
+                lib_path / "apr" / "openroad" / "global_connect.tcl")
+            self.add_openroad_power_grid_file(lib_path / "apr" / "openroad" / "pdngen.tcl")
+
+        # Setup for bambu
+        self.set_bambu_clock_multiplier(1)
+
+
+class IHP130StdCell_1p2(_IHP130StdCell):
+    def __init__(self):
+        super().__init__("1p2")
+
+
+class IHP130StdCell_1p5(_IHP130StdCell):
+    def __init__(self):
+        super().__init__("1p5")

lambdapdk/interposer/__init__.py

@@ -1,18 +1,9 @@
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
+from pathlib import Path
 
+from lambdapdk import LambdaPDK
 
-stackups = []
-for m in ("3ML", "4ML", "5ML"):
-    for w in ("0400", "0800", "2000", "0400_2000"):
-        stackups.append(f'{m}_{w}')
 
-
-####################################################
-# PDK Setup
-####################################################
-def setup():
+class _Interposer(LambdaPDK):
     '''
     The interposer PDK is a passive technology with a number of
     simulated stackups. The PDK contains enablement for place and
@@ -20,60 +11,37 @@ def setup():
     Note that this process design kit is provided as an academic
     and research aid only and the resulting designs are not manufacturable.
     '''
+    def __init__(self, stackup):
+        super().__init__()
+        self.set_name(f"interposer_{stackup}")
 
-    foundry = 'virtual'
-    process = 'interposer'
-
-    libtype = 'none'
-
-    node = 130
-    # TODO: dummy numbers, only matter for cost estimation
-    wafersize = 300
-    hscribe = 0.1
-    vscribe = 0.1
-    edgemargin = 2
-
-    pdkdir = os.path.join('lambdapdk', 'interposer', 'base')
+        self.set_foundry("virtual")
+        self.set_version("v0.0.1")
+        self.set_stackup(stackup)
 
-    pdk = siliconcompiler.PDK(process, package='lambdapdk')
-    register_data_source(pdk)
+        pdk_path = Path("lambdapdk", "interposer", "base")
 
-    # process name
-    pdk.set('pdk', process, 'foundry', foundry)
-    pdk.set('pdk', process, 'node', node)
-    pdk.set('pdk', process, 'version', 'v0.0.1')
-    pdk.set('pdk', process, 'stackup', stackups)
-    pdk.set('pdk', process, 'wafersize', wafersize)
-    pdk.set('pdk', process, 'edgemargin', edgemargin)
-    pdk.set('pdk', process, 'scribe', (hscribe, vscribe))
+        with self.active_dataroot("lambdapdk"):
+            # APR Setup
+            with self.active_fileset("views.lef"):
+                self.add_file(pdk_path / "apr" / f"{stackup}.lef")
+                for tool in ('openroad', 'klayout', 'magic'):
+                    self.add_aprtechfileset(tool)
 
-    # APR Setup
-    for stackup in stackups:
-        for tool in ('openroad', 'klayout', 'magic'):
-            pdk.set('pdk', process, 'aprtech', tool, stackup, libtype, 'lef',
-                    pdkdir + f'/apr/{stackup}.lef')
+            with self.active_fileset("layermap"):
+                self.add_file(pdk_path / "apr" / f"{stackup}.layermap", filetype="layermap")
 
-        pdk.set('pdk', process, 'minlayer', stackup, 'metal1')
-        pdk.set('pdk', process, 'maxlayer', stackup, 'topmetal')
+        self.set_aprroutinglayers(min="metal1", max="topmetal")
 
-        # DRC Runsets
-        pdk.set('pdk', process, 'drc', 'runset', 'klayout', stackup, 'drc',
-                pdkdir + f'/setup/klayout/{stackup}.drc')
+        # KLayout Setup
+        with self.active_dataroot("lambdapdk"):
+            # Klayout setup file
+            with self.active_fileset("klayout.techmap"):
+                self.add_file(pdk_path / "setup" / "klayout" / f"{stackup}.lyp", filetype="display")
+                self.add_displayfileset("klayout")
+            self.add_layermapfileset("klayout", "def", "gds", fileset="layermap")
 
-        key = 'drc_params:drc'
-        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'input=<input>')
-        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'topcell=<topcell>')
-        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'report=<report>')
-        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'threads=<threads>')
-
-        # Layer map and display file
-        pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'gds', stackup,
-                pdkdir + f'/apr/{stackup}.layermap')
-        pdk.set('pdk', process, 'display', 'klayout', stackup,
-                pdkdir + f'/setup/klayout/{stackup}.lyp')
-
-        pdk.set('pdk', process, 'aprtech', 'openroad', stackup, libtype, 'fill',
-                pdkdir + f'/dfm/openroad/{stackup}.fill.json')
+        # OpenROAD Setup
 
         # Openroad global routing grid derating
         openroad_layer_adjustments = {
@@ -88,24 +56,92 @@ def setup():
         for layer, adj in openroad_layer_adjustments.items():
             if layer != 'topmetal' and int(layer[-1]) >= int(stackup[0]):
                 continue
-            pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, adj)
+            self.set_openroad_globalroutingderating(layer, adj)
+
+        self.set_openroad_rclayers(signal="metal2", clock="metal2")
+        self.add_openroad_pinlayers(vertical="metal2", horizontal="metal3")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("openroad.fill"):
+                self.add_file(pdk_path / "dfm" / "openroad" / f"{stackup}.fill.json",
+                              filetype="fill")
+                self.add_aprtechfileset("openroad")
+
+            # PEX
+            for corner in ["minimum", "typical", "maximum"]:
+                with self.active_fileset(f"openroad.pex.{corner}"):
+                    self.add_file(pdk_path / "pex" / "openroad" / f"{stackup}.{corner}.tcl",
+                                  filetype="tcl")
+
+                    self.add_pexmodelfileset("openroad", corner)
+
+        # DRC
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("klayout.drc"):
+                self.add_file(pdk_path / "setup" / "klayout" / f"{stackup}.drc", filetype="drc")
+                self.add_runsetfileset("drc", "klayout", "drc")
+
+            self.add_klayout_drcparam("drc", "in_gds=<input>")
+            self.add_klayout_drcparam("drc", "topcell=<topcell>")
+            self.add_klayout_drcparam("drc", "report=<report>")
+            self.add_klayout_drcparam("drc", "threads=<threads>")
+
+
+class Interposer_3ML_0400(_Interposer):
+    def __init__(self):
+        super().__init__("3ML_0400")
+
+
+class Interposer_3ML_0800(_Interposer):
+    def __init__(self):
+        super().__init__("3ML_0800")
+
+
+class Interposer_3ML_2000(_Interposer):
+    def __init__(self):
+        super().__init__("3ML_2000")
+
+
+class Interposer_3ML_0400_2000(_Interposer):
+    def __init__(self):
+        super().__init__("3ML_0400_2000")
+
+
+class Interposer_4ML_0400(_Interposer):
+    def __init__(self):
+        super().__init__("4ML_0400")
+
+
+class Interposer_4ML_0800(_Interposer):
+    def __init__(self):
+        super().__init__("4ML_0800")
+
+
+class Interposer_4ML_2000(_Interposer):
+    def __init__(self):
+        super().__init__("4ML_2000")
+
+
+class Interposer_4ML_0400_2000(_Interposer):
+    def __init__(self):
+        super().__init__("4ML_0400_2000")
+
+
+class Interposer_5ML_0400(_Interposer):
+    def __init__(self):
+        super().__init__("5ML_0400")
 
-        pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'metal2')
-        pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'metal2')
 
-        pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'metal2')
-        pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'metal3')
+class Interposer_5ML_0800(_Interposer):
+    def __init__(self):
+        super().__init__("5ML_0800")
 
-        # PEX
-        for corner in ["minimum", "typical", "maximum"]:
-            pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, corner,
-                    pdkdir + '/pex/openroad/' + stackup + '.' + corner + '.tcl')
 
-    return pdk
+class Interposer_5ML_2000(_Interposer):
+    def __init__(self):
+        super().__init__("5ML_2000")
 
 
-#########################
-if __name__ == "__main__":
-    pdk = setup()
-    pdk.write_manifest(f'{pdk.top()}.json')
-    pdk.check_filepaths()
+class Interposer_5ML_0400_2000(_Interposer):
+    def __init__(self):
+        super().__init__("5ML_0400_2000")

lambdapdk/interposer/libs/bumps.py

@@ -1,31 +1,46 @@
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
-from lambdapdk.interposer import stackups
+from pathlib import Path
 
+from lambdapdk import LambdaLibrary
 
-def setup():
+from lambdapdk.interposer import Interposer_3ML_0400, \
+    Interposer_3ML_0800, \
+    Interposer_3ML_2000, \
+    Interposer_3ML_0400_2000, \
+    Interposer_4ML_0400, \
+    Interposer_4ML_0800, \
+    Interposer_4ML_2000, \
+    Interposer_4ML_0400_2000, \
+    Interposer_5ML_0400, \
+    Interposer_5ML_0800, \
+    Interposer_5ML_2000, \
+    Interposer_5ML_0400_2000
+
+
+class BumpLibrary(LambdaLibrary):
     '''
     Interposer bump library
     '''
-    libdir = "lambdapdk/interposer/libs/bumps/"
-
-    lib = siliconcompiler.Library('interposer_bumps', package='lambdapdk')
-    register_data_source(lib)
-
-    # pdk
-    lib.set('option', 'pdk', 'interposer')
-
-    for stackup in stackups:
-        lib.set('output', stackup, 'lef',
-                os.path.join(libdir, 'lef/bumps.lef'))
-        lib.add('output', stackup, 'gds',
-                os.path.join(libdir, 'gds/bumps.gds'))
-
-    return lib
-
-
-#########################
-if __name__ == "__main__":
-    lib = setup(siliconcompiler.Chip('<lib>'))
-    lib.write_manifest(f'{lib.top()}.json')
+    def __init__(self):
+        super().__init__()
+        self.set_name("interposer_bumps")
+
+        path_base = Path("lambdapdk", "interposer", "libs", 'bumps')
+
+        self.add_asic_pdk(Interposer_3ML_0400(), default=False)
+        self.add_asic_pdk(Interposer_3ML_0800(), default=False)
+        self.add_asic_pdk(Interposer_3ML_2000(), default=False)
+        self.add_asic_pdk(Interposer_3ML_0400_2000(), default=False)
+        self.add_asic_pdk(Interposer_4ML_0400(), default=False)
+        self.add_asic_pdk(Interposer_4ML_0800(), default=False)
+        self.add_asic_pdk(Interposer_4ML_2000(), default=False)
+        self.add_asic_pdk(Interposer_4ML_0400_2000(), default=False)
+        self.add_asic_pdk(Interposer_5ML_0400(), default=False)
+        self.add_asic_pdk(Interposer_5ML_0800(), default=False)
+        self.add_asic_pdk(Interposer_5ML_2000(), default=False)
+        self.add_asic_pdk(Interposer_5ML_0400_2000(), default=False)
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(path_base / "lef" / "bumps.lef")
+                self.add_file(path_base / "gds" / "bumps.gds")
+                self.add_asic_aprfileset()