lambdapdk 0.1.56__py3-none-any.whl → 0.2.0rc1__py3-none-any.whl

lambdapdk/gf180/__init__.py

@@ -1,12 +1,9 @@
+from pathlib import Path
 
-import siliconcompiler
-from lambdapdk import register_data_source
+from lambdapdk import LambdaPDK
 
 
-####################################################
-# PDK Setup
-####################################################
-def setup():
+class _GF180PDK(LambdaPDK):
     '''
     The 'gf180' Open Source PDK is a collaboration between Google and
     Global Foundries to provide a fully open source Process
@@ -32,60 +29,104 @@ def setup():
 
     * https://github.com/google/gf180mcu-pdk
     '''
+    def __init__(self, stackup, libtype):
+        super().__init__()
+        self.set_name(f"GF180_{stackup}_{libtype}")
+
+        self.set_foundry("globalfoundries")
+        self.set_node(180)
+        self.set_stackup(stackup)
+        self.set_wafersize(200)
+
+        pdk_path = Path("lambdapdk", "gf180", "base")
 
-    foundry = 'globalfoundries'
-    process = 'gf180'
-
-    node = 180
-
-    pdkdir = "lambdapdk/gf180/base/"
-
-    pdk = siliconcompiler.PDK(process, package='lambdapdk')
-    register_data_source(pdk)
-
-    # process name
-    pdk.set('pdk', process, 'foundry', foundry)
-    pdk.set('pdk', process, 'node', node)
-    pdk.set('pdk', process, 'wafersize', 200)
-
-    for stackup in ("3LM_1TM_6K",
-                    "3LM_1TM_9K",
-                    "3LM_1TM_11K",
-                    "3LM_1TM_30K",
-                    "4LM_1TM_6K",
-                    "4LM_1TM_9K",
-                    "4LM_1TM_11K",
-                    "4LM_1TM_30K",
-                    "5LM_1TM_9K",
-                    "5LM_1TM_11K",
-                    "6LM_1TM_9K"):
-        pdk.add('pdk', process, 'stackup', stackup)
-        for libtype in ("7t", "9t"):
-            # APR Setup
-            for tool in ('openroad', 'klayout', 'magic'):
-                pdk.set('pdk', process, 'aprtech', tool, stackup, libtype, 'lef',
-                        pdkdir + f'/apr/gf180mcu_{stackup}_{libtype}_tech.lef')
-        if stackup in ('6LM_1TM_9K', '5LM_1TM_9K'):
-            pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'gds', stackup,
-                    pdkdir + f'/apr/gf180mcu_{stackup}_9t_edi2gds.layermap')
         max_layer = int(stackup[0])
 
-        pdk.set('pdk', process, 'minlayer', stackup, 'Metal1')
-        pdk.set('pdk', process, 'maxlayer', stackup, f'Metal{max_layer}')
+        with self.active_dataroot("lambdapdk"):
+            # APR Setup
+            with self.active_fileset("views.lef"):
+                self.add_file(pdk_path / "apr" / f"gf180mcu_{stackup}_{libtype}_tech.lef")
+                for tool in ('openroad', 'klayout', 'magic'):
+                    self.add_aprtechfileset(tool)
+
+            self.set_aprroutinglayers(min="metal2", max="metal7")
+
+            if stackup in ('6LM_1TM_9K', '5LM_1TM_9K'):
+                with self.active_fileset("layermap"):
+                    self.add_file(pdk_path / "apr" / f"gf180mcu_{stackup}_9t_edi2gds.layermap",
+                                  filetype="layermap")
+                    self.add_layermapfileset("klayout", "def", "gds")
+
+            with self.active_fileset("models.spice"):
+                self.add_file(pdk_path / "spice" / "xyce" / "design.xyce", filetype="xyce")
+                self.add_file(pdk_path / "spice" / "xyce" / "sm141064.xyce", filetype="xyce")
+                self.add_file(pdk_path / "spice" / "xyce" / "smbb000149.xyce", filetype="xyce")
+                self.add_devmodelfileset("xyce", "spice")
+
+        self.set_aprroutinglayers(min="Metal1", max=f"Metal{max_layer}")
+
+        # Klayout setup
+        with self.active_dataroot("lambdapdk"), self.active_fileset("klayout.techmap"):
+            self.add_file(pdk_path / "setup" / "klayout" / "tech" / "gf180mcu.lyt",
+                          filetype="layermap")
+            self.add_file(pdk_path / "setup" / "klayout" / "tech" / "gf180mcu.lyp",
+                          filetype="display")
+            self.add_layermapfileset("klayout", "def", "klayout")
+            self.add_displayfileset("klayout")
+
+        # KLayout DRC
+        metal_level, _, metal_top = stackup.split('_')
+        drcs = {
+            "drc": pdk_path / "setup" / "klayout" / "drc" / "gf180mcu.drc",
+            "drc_feol": pdk_path / "setup" / "klayout" / "drc" / "gf180mcu.drc",
+            "drc_beol": pdk_path / "setup" / "klayout" / "drc" / "gf180mcu.drc",
+            "antenna": pdk_path / "setup" / "klayout" / "drc" / "gf180mcu_antenna.drc",
+            "density": pdk_path / "setup" / "klayout" / "drc" / "gf180mcu_density.drc"
+        }
+        for drc, runset in drcs.items():
+            with self.active_dataroot("lambdapdk"), self.active_fileset(f"klayout.drc.{drc}"):
+                self.add_file(runset, filetype="drc")
+                self.add_runsetfileset("drc", "klayout", drc)
+
+            self.add_klayout_drcparam(drc, "input=<input>")
+            self.add_klayout_drcparam(drc, "topcell=<topcell>")
+            self.add_klayout_drcparam(drc, "thr=<threads>")
+            self.add_klayout_drcparam(drc, "run_mode=flat")
+            self.add_klayout_drcparam(drc, "offgrid=true")
+
+            if drc in ("drc", "drc_feol", "drc_beol"):
+                feol = "true"
+                beol = "true"
+                if drc == "drc_feol":
+                    beol = "false"
+                if drc == "drc_beol":
+                    feol = "false"
+
+                self.add_klayout_drcparam(drc, f"feol={feol}")
+                self.add_klayout_drcparam(drc, f"beol={beol}")
+
+            self.add_klayout_drcparam(drc, f"metal_top={metal_top}")
+            self.add_klayout_drcparam(drc, f"metal_level={metal_level}")
+            if max_layer == 3:
+                self.add_klayout_drcparam(drc, "mim_option=A")
+            elif max_layer == 4 or max_layer == 5:
+                self.add_klayout_drcparam(drc, "mim_option=B")
+
+        self.add_klayout_hidelayers('Dualgate')
+        self.add_klayout_hidelayers('V5_XTOR')
+        self.add_klayout_hidelayers('PR_bndry')
 
-        # Layer map and display file
-        pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup,
-                pdkdir + '/setup/klayout/tech/gf180mcu.lyt')
-        pdk.set('pdk', process, 'display', 'klayout', stackup,
-                pdkdir + '/setup/klayout/tech/gf180mcu.lyp')
+        # OpenROAD setup
 
-        # Device models
-        pdk.add('pdk', process, 'devmodel', 'xyce', 'spice', stackup,
-                pdkdir + '/spice/xyce/design.xyce')
-        pdk.add('pdk', process, 'devmodel', 'xyce', 'spice', stackup,
-                pdkdir + '/spice/xyce/sm141064.xyce')
-        pdk.add('pdk', process, 'devmodel', 'xyce', 'spice', stackup,
-                pdkdir + '/spice/xyce/smbb000149.xyce')
+        if max_layer == 3:
+            self.set_openroad_rclayers(signal="Metal2", clock="Metal2")
+            self.add_openroad_pinlayers(vertical="Metal2", horizontal="Metal3")
+        elif max_layer == 4:
+            self.set_openroad_rclayers(signal="Metal2", clock="Metal3")
+            self.add_openroad_pinlayers(vertical="Metal4", horizontal="Metal3")
+        elif max_layer >= 5:
+            self.set_openroad_rclayers(signal="Metal3", clock="Metal4")
+            self.add_openroad_pinlayers(vertical="Metal4", horizontal="Metal3")
 
         # Openroad global routing grid derating
         openroad_layer_adjustments = {
@@ -98,89 +139,134 @@ def setup():
                 'MetalTop': 1.0
         }
         for layer, adj in openroad_layer_adjustments.items():
-            pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj))
-            if layer == pdk.get('pdk', process, 'maxlayer', stackup):
+            self.set_openroad_globalroutingderating(layer, adj)
+            if layer == f"Metal{max_layer}":
                 break
 
-        if max_layer == 3:
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2')
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal2')
+        # PEX
+        with self.active_dataroot("lambdapdk"):
+            for corner in ["bst", "typ", "wst"]:
+                if stackup in ('3LM_1TM_6K', '3LM_1TM_9K', '3LM_1TM_11K', '3LM_1TM_30K',
+                               '4LM_1TM_6K'):
+                    continue
 
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal2')
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal3')
-        elif max_layer == 4:
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2')
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal3')
+                base_name = f'gf180mcu_1p{stackup.replace("L", "").lower()}_sp_smim_OPTB_{corner}'
 
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal4')
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal3')
-        elif max_layer >= 5:
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal3')
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal4')
+                with self.active_fileset(f"openroad.pex.{corner}"):
+                    self.add_file(pdk_path / "pex" / "openroad" / f"{base_name}.tcl",
+                                  filetype="tcl")
+                    self.add_file(pdk_path / "pex" / "openroad" / f"{base_name}.rules",
+                                  filetype="openrcx")
 
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal4')
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal3')
+                    self.add_pexmodelfileset("openroad", "typical")
+                    self.add_pexmodelfileset("openroad-openrcx", "typical")
 
-        # PEX
-        for corner in ["bst", "typ", "wst"]:
-            if stackup in ('3LM_1TM_6K', '3LM_1TM_9K', '3LM_1TM_11K', '3LM_1TM_30K', '4LM_1TM_6K'):
-                continue
-            base_name = f'gf180mcu_1p{stackup.replace("L", "").lower()}_sp_smim_OPTB_{corner}'
-            pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, corner,
-                    pdkdir + '/pex/openroad/' + base_name + '.tcl')
-            pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, corner,
-                    pdkdir + '/pex/openroad/' + base_name + '.rules')
-
-        # DRC
-        metal_level, _, metal_top = stackup.split('_')
-        drcs = {
-            "drc": pdkdir + '/setup/klayout/drc/gf180mcu.drc',
-            "drc_feol": pdkdir + '/setup/klayout/drc/gf180mcu.drc',
-            "drc_beol": pdkdir + '/setup/klayout/drc/gf180mcu.drc',
-            "antenna": pdkdir + '/setup/klayout/drc/gf180mcu_antenna.drc',
-            "density": pdkdir + '/setup/klayout/drc/gf180mcu_density.drc'
-        }
-        for drc, runset in drcs.items():
-            pdk.set('pdk', process, 'drc', 'runset', 'klayout', stackup, drc, runset)
-
-            key = f'drc_params:{drc}'
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'input=<input>')
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'topcell=<topcell>')
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'report=<report>')
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'thr=<threads>')
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'run_mode=flat')
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'offgrid=true')
-
-            if drc in ('drc', 'drc_feol', 'drc_beol'):
-                feol = 'true'
-                beol = 'true'
-                if drc == 'drc_feol':
-                    beol = 'false'
-                if drc == 'drc_beol':
-                    feol = 'false'
-                pdk.add('pdk', process, 'var', 'klayout', stackup, key,
-                        f'feol={feol}')
-                pdk.add('pdk', process, 'var', 'klayout', stackup, key,
-                        f'beol={beol}')
-
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key,
-                    f'metal_top={metal_top}')
-            pdk.add('pdk', process, 'var', 'klayout', stackup, key,
-                    f'metal_level={metal_level}')
-            if max_layer == 3:
-                pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'mim_option=A')
-            elif max_layer == 4 or max_layer == 5:
-                pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'mim_option=B')
 
-        pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, 'Dualgate')
-        pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, 'V5_XTOR')
-        pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, 'PR_bndry')
+class GF180_3LM_1TM_6K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_6K", "7t")
+
+
+class GF180_3LM_1TM_6K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_6K", "9t")
+
+
+class GF180_3LM_1TM_9K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_9K", "7t")
+
+
+class GF180_3LM_1TM_9K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_9K", "9t")
+
+
+class GF180_3LM_1TM_11K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_11K", "7t")
+
+
+class GF180_3LM_1TM_11K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_11K", "9t")
+
+
+class GF180_3LM_1TM_30K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_30K", "7t")
+
+
+class GF180_3LM_1TM_30K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("3LM_1TM_30K", "9t")
+
+
+class GF180_4LM_1TM_6K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_6K", "7t")
+
+
+class GF180_4LM_1TM_6K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_6K", "9t")
+
+
+class GF180_4LM_1TM_9K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_9K", "7t")
+
+
+class GF180_4LM_1TM_9K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_9K", "9t")
+
+
+class GF180_4LM_1TM_11K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_11K", "7t")
+
+
+class GF180_4LM_1TM_11K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_11K", "9t")
+
+
+class GF180_4LM_1TM_30K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_30K", "7t")
+
+
+class GF180_4LM_1TM_30K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("4LM_1TM_30K", "9t")
+
+
+class GF180_5LM_1TM_9K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("5LM_1TM_9K", "7t")
+
+
+class GF180_5LM_1TM_9K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("5LM_1TM_9K", "9t")
+
+
+class GF180_5LM_1TM_11K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("5LM_1TM_11K", "7t")
+
+
+class GF180_5LM_1TM_11K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("5LM_1TM_11K", "9t")
+
 
-    return pdk
+class GF180_6LM_1TM_9K_7t(_GF180PDK):
+    def __init__(self):
+        super().__init__("6LM_1TM_9K", "7t")
 
 
-#########################
-if __name__ == "__main__":
-    pdk = setup()
-    pdk.write_manifest(f'{pdk.top()}.json')
-    pdk.check_filepaths()
+class GF180_6LM_1TM_9K_9t(_GF180PDK):
+    def __init__(self):
+        super().__init__("6LM_1TM_9K", "9t")

lambdapdk/gf180/libs/gf180io.py

@@ -1,73 +1,108 @@
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
+from pathlib import Path
 
+from lambdapdk import LambdaLibrary
+from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
+    GF180_3LM_1TM_6K_9t, \
+    GF180_3LM_1TM_9K_7t, \
+    GF180_3LM_1TM_9K_9t, \
+    GF180_3LM_1TM_11K_7t, \
+    GF180_3LM_1TM_11K_9t, \
+    GF180_3LM_1TM_30K_7t, \
+    GF180_3LM_1TM_30K_9t, \
+    GF180_4LM_1TM_6K_7t, \
+    GF180_4LM_1TM_6K_9t, \
+    GF180_4LM_1TM_9K_7t, \
+    GF180_4LM_1TM_9K_9t, \
+    GF180_4LM_1TM_11K_7t, \
+    GF180_4LM_1TM_11K_9t, \
+    GF180_4LM_1TM_30K_7t, \
+    GF180_4LM_1TM_30K_9t, \
+    GF180_5LM_1TM_9K_7t, \
+    GF180_5LM_1TM_9K_9t, \
+    GF180_5LM_1TM_11K_7t, \
+    GF180_5LM_1TM_11K_9t
 
-def setup():
+
+class _GF180IOLibrary(LambdaLibrary):
     '''
     GloabalFoundries 180 I/O library.
     '''
-    libdir = "lambdapdk/gf180/libs/gf180mcu_fd_io/"
-
-    libs = []
-    for substack in ("3LM", "4LM", "5LM"):
-        lib = siliconcompiler.Library(f'gf180mcu_fd_io_{substack}', package='lambdapdk')
-        register_data_source(lib)
-
-        # pdk
-        lib.set('option', 'pdk', 'gf180')
-
-        lib.set('output', 'slow', 'nldm',
-                os.path.join(libdir, 'nldm/gf180mcu_fd_io__ss_125C_2v97.lib.gz'))
-        lib.set('output', 'typical', 'nldm',
-                os.path.join(libdir, 'nldm/gf180mcu_fd_io__tt_025C_3v30.lib.gz'))
-        lib.set('output', 'fast', 'nldm',
-                os.path.join(libdir, 'nldm/gf180mcu_fd_io__ff_125C_3v63.lib.gz'))
-
-        for corner in ('slow', 'typical', 'fast'):
-            lib.set('output', corner, 'spice',
-                    os.path.join(libdir, f'spice/{substack}/gf180mcu_fd_io.spice'))
-
-        for stackup in ("3LM_1TM_6K",
-                        "3LM_1TM_9K",
-                        "3LM_1TM_11K",
-                        "3LM_1TM_30K",
-                        "4LM_1TM_6K",
-                        "4LM_1TM_9K",
-                        "4LM_1TM_11K",
-                        "4LM_1TM_30K",
-                        "5LM_1TM_9K",
-                        "5LM_1TM_11K"):
-            stackup_start = stackup[0:3]
-            if substack != stackup_start:
-                continue
-            lib.set('output', stackup, 'lef',
-                    os.path.join(libdir, f'lef/{stackup_start}/gf180mcu_fd_io.lef'))
-            lib.set('output', stackup, 'cdl', os.path.join(libdir, 'cdl/gf180mcu_fd_io.cdl'))
-
-            lib.add('output', stackup, 'gds',
-                    os.path.join(libdir, f'gds/{stackup_start}/gf180mcu_fd_io.gds.gz'))
-
-        lib.set('asic', 'cells', 'filler', ['gf180mcu_fd_io__fill1',
-                                            'gf180mcu_fd_io__fill5',
-                                            'gf180mcu_fd_io__fill10',
-                                            'gf180mcu_fd_io__fillnc'])
-
-        lib.set('output', 'blackbox', 'verilog',
-                os.path.join(libdir, 'blackbox', f'{stackup_start}.v'))
-
-        libs.append(lib)
-
-    lambda_lib = siliconcompiler.Library('lambdalib_gf180mcu_fd_io', package='lambdapdk')
-    register_data_source(lambda_lib)
-    lambda_lib.add('option', 'ydir', 'lambdapdk/gf180/libs/gf180mcu_fd_io/lambda')
-    lambda_lib.use(lib)
-    lambda_lib.set('asic', 'macrolib', lib.design)
-
-    return [*libs, lambda_lib]
-
-
-#########################
-if __name__ == "__main__":
-    for lib in setup(siliconcompiler.Chip('<lib>')):
-        lib.write_manifest(f'{lib.top()}.json')
+    def __init__(self, stackup):
+        super().__init__()
+        self.set_name(f"gf180mcu_fd_io_{stackup}")
+
+        path_base = Path("lambdapdk", "gf180", "libs", "gf180mcu_fd_io")
+
+        if stackup == "3LM":
+            self.add_asic_pdk(GF180_3LM_1TM_6K_7t(), default=False)
+            self.add_asic_pdk(GF180_3LM_1TM_6K_9t(), default=False)
+            self.add_asic_pdk(GF180_3LM_1TM_9K_7t(), default=False)
+            self.add_asic_pdk(GF180_3LM_1TM_9K_9t(), default=False)
+            self.add_asic_pdk(GF180_3LM_1TM_11K_7t(), default=False)
+            self.add_asic_pdk(GF180_3LM_1TM_11K_9t(), default=False)
+            self.add_asic_pdk(GF180_3LM_1TM_30K_7t(), default=False)
+            self.add_asic_pdk(GF180_3LM_1TM_30K_9t(), default=False)
+        elif stackup == "4LM":
+            self.add_asic_pdk(GF180_4LM_1TM_6K_7t(), default=False)
+            self.add_asic_pdk(GF180_4LM_1TM_6K_9t(), default=False)
+            self.add_asic_pdk(GF180_4LM_1TM_9K_7t(), default=False)
+            self.add_asic_pdk(GF180_4LM_1TM_9K_9t(), default=False)
+            self.add_asic_pdk(GF180_4LM_1TM_11K_7t(), default=False)
+            self.add_asic_pdk(GF180_4LM_1TM_11K_9t(), default=False)
+            self.add_asic_pdk(GF180_4LM_1TM_30K_7t(), default=False)
+            self.add_asic_pdk(GF180_4LM_1TM_30K_9t(), default=False)
+        elif stackup == "5LM":
+            self.add_asic_pdk(GF180_5LM_1TM_9K_7t(), default=False)
+            self.add_asic_pdk(GF180_5LM_1TM_9K_9t(), default=False)
+            self.add_asic_pdk(GF180_5LM_1TM_11K_7t(), default=False)
+            self.add_asic_pdk(GF180_5LM_1TM_11K_9t(), default=False)
+        else:
+            raise ValueError(f"{stackup} is not supported")
+
+        with self.active_dataroot("lambdapdk"):
+            for corner_name, filename in [
+                    ('slow', 'gf180mcu_fd_io__ss_125C_2v97.lib.gz'),
+                    ('typical', 'gf180mcu_fd_io__tt_025C_3v30.lib.gz'),
+                    ('fast', 'gf180mcu_fd_io__ff_125C_3v63.lib.gz')]:
+                with self.active_fileset(f"models.timing.{corner_name}.nldm"):
+                    self.add_file(path_base / "nldm" / filename)
+                    self.add_asic_libcornerfileset(corner_name, "nldm")
+
+            with self.active_fileset("models.spice"):
+                self.add_file(path_base / "spice" / stackup / "gf180mcu_fd_io.spice")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(path_base / "lef" / stackup / "gf180mcu_fd_io.lef")
+                self.add_file(path_base / "gds" / stackup / "gf180mcu_fd_io.gds.gz")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file(path_base / "cdl" / "gf180mcu_fd_io.cdl")
+                self.add_asic_aprfileset()
+
+        self.add_asic_celllist("filler", [
+            'gf180mcu_fd_io__fill1',
+            'gf180mcu_fd_io__fill5',
+            'gf180mcu_fd_io__fill10',
+            'gf180mcu_fd_io__fillnc'])
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.blackbox"):
+                self.add_file(path_base / "blackbox" / f"{stackup}.v")
+            self.add_yosys_blackbox_fileset("models.blackbox")
+
+
+class GF180_IO_3LM(_GF180IOLibrary):
+    def __init__(self):
+        super().__init__("3LM")
+
+
+class GF180_IO_4LM(_GF180IOLibrary):
+    def __init__(self):
+        super().__init__("4LM")
+
+
+class GF180_IO_5LM(_GF180IOLibrary):
+    def __init__(self):
+        super().__init__("5LM")