lambdapdk 0.1.56__py3-none-any.whl → 0.2.0rc1__py3-none-any.whl

lambdapdk/freepdk45/__init__.py

@@ -1,13 +1,9 @@
+from pathlib import Path
 
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
+from lambdapdk import LambdaPDK
 
 
-####################################################
-# PDK Setup
-####################################################
-def setup():
+class FreePDK45PDK(LambdaPDK):
     '''
     The freepdk45 PDK is a virtual PDK derived from the work done at
     NCSU (NCSU_TechLib_FreePDK45.)  It supplies techfiles, display
@@ -24,85 +20,59 @@ def setup():
 
     * https://eda.ncsu.edu/freepdk/freepdk45/
     '''
-
-    ###############################################
-    # Process
-    ###############################################
-
-    foundry = 'virtual'
-    process = 'freepdk45'
-    rev = 'r1p0'
-    stackup = '10M'
-    libtype = '10t'
-    node = 45
-    wafersize = 300
-    hscribe = 0.1
-    vscribe = 0.1
-    edgemargin = 2
-    d0 = 1.25
-
-    pdkdir = os.path.join('lambdapdk', 'freepdk45', 'base')
-
-    pdk = siliconcompiler.PDK(process, package='lambdapdk')
-    register_data_source(pdk)
-
-    # process name
-    pdk.set('pdk', process, 'foundry', foundry)
-    pdk.set('pdk', process, 'node', node)
-    pdk.set('pdk', process, 'version', rev)
-    pdk.set('pdk', process, 'stackup', stackup)
-    pdk.set('pdk', process, 'wafersize', wafersize)
-    pdk.set('pdk', process, 'edgemargin', edgemargin)
-    pdk.set('pdk', process, 'scribe', (hscribe, vscribe))
-    pdk.set('pdk', process, 'd0', d0)
-
-    # APR Setup
-    for tool in ('openroad', 'klayout', 'magic'):
-        pdk.set('pdk', process, 'aprtech', tool, stackup, libtype, 'lef',
-                pdkdir + '/apr/freepdk45.tech.lef')
-
-    pdk.set('pdk', process, 'minlayer', stackup, 'metal2')
-    pdk.set('pdk', process, 'maxlayer', stackup, 'metal7')
-
-    # Klayout setup file
-    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup,
-            pdkdir + '/setup/klayout/freepdk45.lyt')
-
-    pdk.set('pdk', process, 'display', 'klayout', stackup, pdkdir + '/setup/klayout/freepdk45.lyp')
-
-    # Openroad global routing grid derating
-    openroad_layer_adjustments = {
-        'metal1': 1.0,
-        'metal2': 0.5,
-        'metal3': 0.5,
-        'metal4': 0.25,
-        'metal5': 0.25,
-        'metal6': 0.25,
-        'metal7': 0.25,
-        'metal8': 0.25,
-        'metal9': 0.25,
-        'metal10': 0.25
-    }
-    for layer, adj in openroad_layer_adjustments.items():
-        pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj))
-
-    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'metal3')
-    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'metal5')
-
-    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'metal6')
-    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'metal5')
-
-    # PEX
-    pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, 'typical',
-            pdkdir + '/pex/openroad/typical.tcl')
-    pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, 'typical',
-            pdkdir + '/pex/openroad/typical.rules')
-
-    return pdk
-
-
-#########################
-if __name__ == "__main__":
-    pdk = setup()
-    register_data_source(pdk)
-    pdk.check_filepaths()
+    def __init__(self):
+        super().__init__()
+        self.set_name("freepdk45")
+
+        pdk_path = Path("lambdapdk", "freepdk45", "base")
+
+        self.set_foundry("virtual")
+        self.set_version("r1p0")
+        self.set_node(45)
+        self.set_stackup("10M")
+        self.set_wafersize(300)
+        self.set_scribewidth(0.1, 0.1)
+        self.set_edgemargin(2)
+        self.set_defectdensity(1.25)
+
+        with self.active_dataroot("lambdapdk"):
+            # APR Setup
+            with self.active_fileset("views.lef"):
+                self.add_file(pdk_path / "apr" / "freepdk45.tech.lef")
+                for tool in ('openroad', 'klayout', 'magic'):
+                    self.add_aprtechfileset(tool)
+
+            self.set_aprroutinglayers(min="metal2", max="metal7")
+
+            # Klayout setup file
+            with self.active_fileset("klayout.techmap"):
+                self.add_file(pdk_path / "setup" / "klayout" / "freepdk45.lyt", filetype="layermap")
+                self.add_file(pdk_path / "setup" / "klayout" / "freepdk45.lyp", filetype="display")
+                self.add_layermapfileset("klayout", "def", "klayout")
+                self.add_displayfileset("klayout")
+
+            self.set_openroad_rclayers(signal="metal3", clock="metal5")
+
+            # Openroad global routing grid derating
+            for layer, derate in [
+                    ('metal1', 1.0),
+                    ('metal2', 0.5),
+                    ('metal3', 0.5),
+                    ('metal4', 0.25),
+                    ('metal5', 0.25),
+                    ('metal6', 0.25),
+                    ('metal7', 0.25),
+                    ('metal8', 0.25),
+                    ('metal9', 0.25),
+                    ('metal10', 0.25)]:
+                self.set_openroad_globalroutingderating(layer, derate)
+
+            self.add_openroad_pinlayers(vertical="metal6", horizontal="metal5")
+
+            # PEX
+            with self.active_fileset("openroad.pex"):
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.tcl", filetype="tcl")
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.rules", filetype="openrcx")
+
+                self.add_pexmodelfileset("openroad", "typical")
+                self.add_pexmodelfileset("openroad-openrcx", "typical")

lambdapdk/freepdk45/libs/fakeram45.py

@@ -1,36 +1,81 @@
-from siliconcompiler import Library
-from lambdapdk import register_data_source
+from pathlib import Path
 
+from lambdalib import LambalibTechLibrary
+from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdapdk.freepdk45 import FreePDK45PDK
 
-def setup():
-    libs = []
-    stackup = '10M'
-    corner = 'typical'
 
-    for config in ('64x32', '128x32', '256x32', '256x64', '512x32', '512x64'):
-        mem_name = f'fakeram45_{config}'
-        lib = Library(mem_name, package='lambdapdk')
-        register_data_source(lib)
-        path_base = 'lambdapdk/freepdk45/libs/fakeram45'
-        lib.add('output', stackup, 'lef', f'{path_base}/lef/{mem_name}.lef')
-        lib.add('output', corner, 'nldm', f'{path_base}/nldm/{mem_name}.lib')
+class _FakeRAM45Library(LambdaLibrary):
+    def __init__(self, config):
+        super().__init__()
+        self.set_name(f"fakeram45_{config}")
 
-        lib.set('option', 'file', 'openroad_pdngen',
-                f'{path_base}/apr/openroad/pdngen.tcl')
-        lib.set('option', 'file', 'openroad_global_connect',
-                f'{path_base}/apr/openroad/global_connect.tcl')
+        self.add_asic_pdk(FreePDK45PDK())
 
-        lib.set('option', 'var', 'klayout_allow_missing_cell', mem_name)
+        path_base = Path("lambdapdk", "freepdk45", "libs", "fakeram45")
 
-        libs.append(lib)
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(path_base / "lef" / f"{self.name}.lef")
+                self.add_asic_aprfileset()
 
-    lambda_lib = Library('lambdalib_fakeram45', package='lambdapdk')
-    register_data_source(lambda_lib)
-    lambda_lib.add('option', 'ydir', 'lambdapdk/freepdk45/libs/fakeram45/lambda')
-    for lib in libs:
-        lambda_lib.use(lib)
-        lambda_lib.add('asic', 'macrolib', lib.design)
+                with self.active_fileset("models.timing.nldm"):
+                    self.add_file(path_base / "nldm" / f"{self.name}.lib")
+                    self.add_asic_libcornerfileset("typical", "nldm")
 
-    libs.append(lambda_lib)
+            self.add_openroad_power_grid_file(path_base / "apr" / "openroad" / "pdngen.tcl")
+            self.add_openroad_global_connect_file(
+                path_base / "apr" / "openroad" / "global_connect.tcl")
 
-    return libs
+            self.add_klayout_allowmissingcell(self.name)
+
+
+class FakeRAM45_64x32(_FakeRAM45Library):
+    def __init__(self):
+        super().__init__("64x32")
+
+
+class FakeRAM45_128x32(_FakeRAM45Library):
+    def __init__(self):
+        super().__init__("128x32")
+
+
+class FakeRAM45_256x32(_FakeRAM45Library):
+    def __init__(self):
+        super().__init__("256x32")
+
+
+class FakeRAM45_256x64(_FakeRAM45Library):
+    def __init__(self):
+        super().__init__("256x64")
+
+
+class FakeRAM45_512x32(_FakeRAM45Library):
+    def __init__(self):
+        super().__init__("512x32")
+
+
+class FakeRAM45_512x64(_FakeRAM45Library):
+    def __init__(self):
+        super().__init__("512x64")
+
+
+class FakeRAM45Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
+    def __init__(self):
+        super().__init__("la_spram", [
+            FakeRAM45_64x32,
+            FakeRAM45_128x32,
+            FakeRAM45_256x32,
+            FakeRAM45_256x64,
+            FakeRAM45_512x32,
+            FakeRAM45_512x64])
+        self.set_name("fakeram45_la_spram")
+
+        # version
+        self.set_version("v1")
+
+        lib_path = Path("lambdapdk", "freepdk45", "libs", "fakeram45")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("rtl"):
+                self.add_file(lib_path / "lambda" / "la_spram.v")

lambdapdk/freepdk45/libs/nangate45.py

@@ -1,130 +1,91 @@
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
+from pathlib import Path
 
+from lambdapdk import LambdaLibrary
 
-def setup():
+from lambdapdk.freepdk45 import FreePDK45PDK
+
+
+class Nangate45(LambdaLibrary):
     '''
     Nangate open standard cell library for FreePDK45.
     '''
-    libname = 'nangate45'
-    process = 'freepdk45'
-    stackup = '10M'
-    libtype = '10t'
-    version = 'r1p0'
-    corner = 'typical'
-
-    lib = siliconcompiler.Library(libname, package='lambdapdk')
-    register_data_source(lib)
-
-    libdir = os.path.join('lambdapdk', process, 'libs', libname)
-
-    # version
-    lib.set('package', 'version', version)
-
-    # list of stackups supported
-    lib.set('option', 'stackup', stackup)
-
-    # list of pdks supported
-    lib.set('option', 'pdk', process)
-
-    # footprint/type/sites
-    lib.set('asic', 'libarch', libtype)
-    lib.set('asic', 'site', libtype, 'FreePDK45_38x28_10R_NP_162NW_34O')
-
-    # timing
-    lib.add('output', corner, 'nldm', libdir + '/nldm/NangateOpenCellLibrary_typical.lib')
-
-    # lef
-    lib.add('output', stackup, 'lef', libdir + '/lef/NangateOpenCellLibrary.macro.mod.lef')
-
-    # gds
-    lib.add('output', stackup, 'gds', libdir + '/gds/NangateOpenCellLibrary.gds')
-
-    # cdl
-    lib.add('output', stackup, 'cdl', libdir + '/cdl/NangateOpenCellLibrary.cdl')
-
-    # clock buffers
-    lib.set('asic', 'cells', 'clkbuf', ["CLKBUF_X1",
-                                        "CLKBUF_X2",
-                                        "CLKBUF_X3"])
-
-    # tie cells
-    lib.add('asic', 'cells', 'tie', ["LOGIC1_X1",
-                                     "LOGIC0_X1"])
-
-    # filler
-    lib.add('asic', 'cells', 'filler', ["FILLCELL_X1",
-                                        "FILLCELL_X2",
-                                        "FILLCELL_X4",
-                                        "FILLCELL_X8",
-                                        "FILLCELL_X16",
-                                        "FILLCELL_X32"])
-
-    # Stupid small cells
-    lib.add('asic', 'cells', 'dontuse', ["OAI211_X1"])
-
-    # Tapcell
-    lib.add('asic', 'cells', 'tap', "TAPCELL_X1")
-
-    # Endcap
-    lib.add('asic', 'cells', 'endcap', "TAPCELL_X1")
-
-    # Techmap
-    lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
-    lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
-    lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
-
-    # Defaults for OpenROAD tool variables
-    lib.set('option', 'var', 'openroad_place_density', '0.50')
-    lib.set('option', 'var', 'openroad_pad_global_place', '0')
-    lib.set('option', 'var', 'openroad_pad_detail_place', '0')
-    lib.set('option', 'var', 'openroad_macro_place_halo', ['22.4', '15.12'])
-    lib.set('option', 'var', 'openroad_macro_place_channel', ['18.8', '19.95'])
-
-    lib.set('option', 'file', 'openroad_tapcells', libdir + '/apr/openroad/tapcell.tcl')
-    lib.set('option', 'file', 'openroad_pdngen', libdir + '/apr/openroad/pdngen.tcl')
-    lib.set('option', 'file', 'openroad_global_connect',
-            libdir + '/apr/openroad/global_connect.tcl')
-
-    lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
-    lib.set('option', 'var', 'yosys_abc_constraint_load', "3.899fF")  # BUF_X1 = 0.974659 x 4
-    lib.set('option', 'var', 'yosys_driver_cell', "BUF_X4")
-    lib.set('option', 'var', 'yosys_buffer_cell', "BUF_X1")
-    lib.set('option', 'var', 'yosys_buffer_input', "A")
-    lib.set('option', 'var', 'yosys_buffer_output', "Z")
-    for tool in ('yosys', 'openroad'):
-        lib.set('option', 'var', f'{tool}_tiehigh_cell', "LOGIC1_X1")
-        lib.set('option', 'var', f'{tool}_tiehigh_port', "Z")
-        lib.set('option', 'var', f'{tool}_tielow_cell', "LOGIC0_X1")
-        lib.set('option', 'var', f'{tool}_tielow_port', "Z")
-
-    # Bambu setup
-    lib.set('option', 'var', 'bambu_device', 'nangate45')
-    lib.set('option', 'var', 'bambu_clock_multiplier', 1)  # convert from ns -> ns
-
-    libs = [lib]
-    std_lambda_lib = siliconcompiler.Library(f'lambdalib_stdlib_{libname}',
-                                             package='lambdapdk')
-    register_data_source(std_lambda_lib)
-    std_lambda_lib.add('option', 'ydir', libdir + '/lambda/stdlib')
-    std_lambda_lib.use(lib)
-    std_lambda_lib.set('asic', 'logiclib', lib.design)
-    libs.append(std_lambda_lib)
-    aux_lambda_lib = siliconcompiler.Library(f'lambdalib_auxlib_{libname}',
-                                             package='lambdapdk')
-    register_data_source(aux_lambda_lib)
-    aux_lambda_lib.add('option', 'ydir', libdir + '/lambda/auxlib')
-    aux_lambda_lib.use(std_lambda_lib)
-    aux_lambda_lib.use(lib)
-    aux_lambda_lib.set('asic', 'logiclib', lib.design)
-    aux_lambda_lib.set('option', 'library', std_lambda_lib.design)
-    libs.append(aux_lambda_lib)
-
-    return libs
-
-
-#########################
-if __name__ == "__main__":
-    lib = setup()
-    lib.write_manifest(f'{lib.top()}.json')
+    def __init__(self):
+        super().__init__()
+        self.set_name("nangate45")
+
+        # version
+        self.set_version("r1p0")
+
+        self.add_asic_pdk(FreePDK45PDK())
+
+        self.add_asic_site("FreePDK45_38x28_10R_NP_162NW_34O")
+
+        # clock buffers
+        self.add_asic_celllist("clkbuf", ["CLKBUF_X1",
+                                          "CLKBUF_X2",
+                                          "CLKBUF_X3"])
+
+        # tie cells
+        self.add_asic_celllist("tie", ["LOGIC0_X1",
+                                       "LOGIC1_X1"])
+
+        # filler
+        self.add_asic_celllist("filler", ["FILLCELL_X1",
+                                          "FILLCELL_X2",
+                                          "FILLCELL_X4",
+                                          "FILLCELL_X8",
+                                          "FILLCELL_X16",
+                                          "FILLCELL_X32"])
+
+        # Dont use for synthesis
+        self.add_asic_celllist("dontuse", "OAI211_X1")
+
+        # Tapcell
+        self.add_asic_celllist("tap", "TAPCELL_X1")
+
+        # Endcap
+        self.add_asic_celllist("endcap", "TAPCELL_X1")
+
+        lib_path = Path("lambdapdk", "freepdk45", "libs", "nangate45")
+
+        # General filelists
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.timing.nldm"):
+                self.add_file(lib_path / "nldm" / "NangateOpenCellLibrary_typical.lib")
+                self.add_asic_libcornerfileset("typical", "nldm")
+
+            with self.active_fileset("models.physical"):
+                self.add_file(lib_path / "lef" / "NangateOpenCellLibrary.macro.mod.lef")
+                self.add_file(lib_path / "gds" / "NangateOpenCellLibrary.gds")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file(lib_path / "cdl" / "NangateOpenCellLibrary.cdl")
+                self.add_asic_aprfileset()
+
+        # Setup for yosys
+        with self.active_dataroot("lambdapdk"):
+            self.set_yosys_driver_cell("BUF_X4")
+            self.set_yosys_buffer_cell("BUF_X1", "A", "Z")
+            self.set_yosys_tielow_cell("LOGIC0_X1", "Z")
+            self.set_yosys_tiehigh_cell("LOGIC1_X1", "Z")
+            self.set_yosys_abc(1000, 3.899)
+            self.set_yosys_tristatebuffer_map(
+                lib_path / "techmap" / "yosys" / "cells_tristatebuf.v")
+            self.set_yosys_adder_map(lib_path / "techmap" / "yosys" / "cells_adders.v")
+            self.add_yosys_tech_map(lib_path / "techmap" / "yosys" / "cells_latch.v")
+
+        # Setup for openroad
+        with self.active_dataroot("lambdapdk"):
+            self.set_openroad_placement_density(0.50)
+            self.set_openroad_tielow_cell("LOGIC0_X1", "Z")
+            self.set_openroad_tiehigh_cell("LOGIC1_X1", "Z")
+            self.set_openroad_macro_placement_halo(22.4, 15.12)
+            self.set_openroad_tapcells_file(lib_path / "apr" / "openroad" / "tapcell.tcl")
+            self.add_openroad_global_connect_file(
+                lib_path / "apr" / "openroad" / "global_connect.tcl")
+            self.add_openroad_power_grid_file(lib_path / "apr" / "openroad" / "pdngen.tcl")
+
+        # Setup for bambu
+        self.set_bambu_device_name("nangate45")
+        self.set_bambu_clock_multiplier(1)