accelforge 0.0.1__py3-none-any.whl

examples/arches/compute_in_memory/components/misc.py

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+from numbers import Number
+from typing import Optional, List
+from hwcomponents.scaling import tech_node_area
+from util.bit_functions import rescale_sum_to_1
+from hwcomponents import ComponentModel, action
+
+
+class Capacitor(ComponentModel):
+    """
+    A capacitor.
+
+    Parameters
+    ----------
+    capacitance: float
+        The capacitance of this capacitor in Farads.
+    tech_node: int
+        The tech_node node in meters.
+    voltage: float
+        The supply voltage in volts.
+    cap_per_m2: float
+        The capacitance per square meter in Farads per square meter.
+    border_area: float
+        The border area around the capacitor in square meters.
+    voltage_raise_threshold: float
+        Latency is calculated as the time it takes to raise voltage to this proportion
+        of the target voltage.
+    supply_resistance: float
+        The supply resistance in ohms. If 0, then voltage is assumed to converge
+        instantly.
+
+    Attributes
+    ----------
+    capacitance: float
+        The capacitance of this capacitor in Farads.
+    tech_node: int
+        The tech_node node in meters.
+    voltage: float
+        The supply voltage in volts.
+    cap_per_m2: float
+        The capacitance per square meter in Farads per square meter.
+    border_area: float
+        The border area around the capacitor in square meters.
+    voltage_raise_threshold: float
+        Latency is calculated as the time it takes to raise voltage to this proportion
+        of the target voltage.
+    supply_resistance: float
+        The supply resistance in ohms. If 0, then voltage is assumed to converge
+        instantly.
+    """
+
+    priority = 0.5
+    """
+    Priority determines which model is used when multiple models are available for a
+    given component. Higher priority models are used first. Must be a number between 0
+    and 1.
+    """
+
+    def __init__(
+        self,
+        capacitance: Number,
+        tech_node: float,
+        voltage: Number = 0.7,
+        cap_per_m2: Optional[Number] = "1e-3 scaled by tech node",
+        border_area: Optional[Number] = "1e-12 scaled by tech node",
+    ):
+        self.capacitance = capacitance
+        self.voltage = voltage
+
+        if cap_per_m2 == "1e-3 scaled by tech node":
+            cap_per_m2 = 2.3e-3 * tech_node_area(tech_node, 22e-9)
+        if border_area == "1e-12 scaled by tech node":
+            border_area = 1e-12 * tech_node_area(tech_node, 22e-9)
+
+        self.cap_per_m2 = cap_per_m2
+        self.border_area = border_area
+
+        super().__init__(
+            area=self.capacitance / self.cap_per_m2 + self.border_area, leak_power=0
+        )
+
+    @action
+    def raise_voltage_to(
+        self,
+        target_voltage: float,
+        supply_voltage: float = None,
+    ) -> float:
+        """
+        Raise the voltage to the target voltage using the supply voltage as a supply.
+
+        Parameters
+        ----------
+        target_voltage: float
+            The target voltage to raise the voltage to.
+        supply_voltage: float
+            The supply voltage to use as a supply. If None, then the supply voltage is
+            assumed to be the voltage set in the attributes of this capacitor.
+
+        Returns
+        -------
+        energy, latency: tuple
+            The energy required to raise the voltage to the target voltage. Latency is
+            0.
+        """
+        if supply_voltage is None:
+            supply_voltage = self.voltage
+        assert target_voltage <= supply_voltage, (
+            f"Can not raise voltage to {target_voltage} when supply voltage "
+            f"is {supply_voltage}."
+        )
+        return self.capacitance * target_voltage * supply_voltage, 0
+
+    @action
+    def switch(
+        self,
+        value_probabilities: List[Number],
+        zero_between_values: bool = True,
+        supply_voltage: float = None,
+    ) -> float:
+        """
+        Calculates the expected energy to switch voltage to the values in
+        value_probabilities.
+
+        Parameters
+        ----------
+        value_probabilities: List[Number]
+            The probabilities of the values to switch to. This is a histogram, assumed
+            to be spaced between 0 and supply_voltage, inclusive.
+        zero_between_values: bool
+            Whether to zero the voltage between values.
+        supply_voltage: float
+            The supply voltage to use as a supply. If None, then the supply voltage is
+            assumed to be the voltage set in the attributes of this capacitor.
+
+        Returns
+        -------
+        energy, latency: tuple
+            The energy required to switch the voltage to the values in
+            value_probabilities. Latency is 0.
+        """
+        supply_voltage = self.voltage if supply_voltage is None else supply_voltage
+        expected_energy = 0
+        value_probabilities = rescale_sum_to_1(value_probabilities)
+        for v0, p0 in enumerate(value_probabilities):
+            for v1, p1 in enumerate(value_probabilities):
+                v0 = 0 if zero_between_values else v0
+                if v1 < v0:
+                    continue
+                e0 = self.raise_voltage_to(
+                    v0 / (len(value_probabilities) - 1) * self.voltage, supply_voltage
+                )[0]
+                e1 = self.raise_voltage_to(
+                    v1 / (len(value_probabilities) - 1) * self.voltage, supply_voltage
+                )[0]
+                expected_energy += (e1 - e0) * p0 * p1
+        return expected_energy, 0
+
+
+class Wire(Capacitor):
+    """
+    A wire.
+
+    Parameters
+    ----------
+    length: Number
+        The length of the wire in meters.
+    capacitance_per_m: Number
+        The capacitance per meter in Farads per meter.
+    voltage: Number
+        The supply voltage of the wire in volts.
+
+    Attributes
+    ----------
+    length: Number
+        The length of the wire in meters.
+    capacitance_per_m: Number
+        The capacitance per meter in Farads per meter.
+    voltage: Number
+        The supply voltage of the wire in volts.
+    """
+
+    def __init__(
+        self,
+        length: Number,
+        capacitance_per_m: Number = 2e-10,
+        voltage: Number = 0.7,
+        **kwargs,
+    ):
+        super().__init__(
+            capacitance=length * capacitance_per_m,
+            voltage=voltage,
+        )
+        self.length = length
+        self.capacitance_per_m = capacitance_per_m
+        self.voltage = voltage
+        self.area_scale = 0

examples/arches/compute_in_memory/components/util/bit_functions.py

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+import math
+from typing import List
+
+
+def rescale_sum_to_1(array: List[float], do_not_change_index: int = -1) -> List[float]:
+    """Rescales all list elements such that the sum is 1."""
+    sum_array = sum([a for i, a in enumerate(array) if i != do_not_change_index])
+    target_sum = 1 - array[do_not_change_index] if do_not_change_index >= 0 else 1
+    scaleby = target_sum / sum_array
+    return [a * scaleby if i != do_not_change_index else a for i, a in enumerate(array)]
+
+
+def set_element_rescale_sum_to_1(array: List[float], index: int, value: float):
+    """
+    Sets an element of a list, then rescales all list elements such that the sum is 1.
+    """
+    array[index] = value
+    return rescale_sum_to_1(array, index)
+
+
+def value2bits(value: int, resolution: int) -> List[int]:
+    """Converts a value to a list of bits."""
+    return [int(i) for i in bin(value)[2:].zfill(resolution)]
+
+
+def bit_distribution_2_hist(
+    bit_distribution: List[float], zero_prob: float = None
+) -> List[float]:
+    """Converts a bit distribution to a value distribution."""
+    hist = [1] * 2 ** len(bit_distribution)
+    for value in range(2 ** len(bit_distribution)):
+        bits = value2bits(value, len(bit_distribution))
+        for i, prob in enumerate(bit_distribution):
+            hist[value] *= prob if bits[i] else 1 - prob
+
+    if zero_prob is not None:
+        set_element_rescale_sum_to_1(hist, 0, zero_prob)
+    return rescale_sum_to_1(hist)
+
+
+def hist_2_bit_distribution(hist: List[float]) -> List[float]:
+    """Converts a value distribution to a bit distribution."""
+    sum_hist = sum(hist)
+    hist = [i / sum_hist for i in hist]
+
+    bit_distribution = [0] * math.ceil(math.log(len(hist), 2))
+    for value in range(len(hist)):
+        for i, bit in enumerate(value2bits(value, len(bit_distribution))):
+            bit_distribution[i] += hist[value] * bit
+
+    return bit_distribution

examples/arches/compute_in_memory/components/zero_comparator.py

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+from math import ceil, log2
+from hwcomponents import ComponentModel, action
+from hwcomponents.scaling import linear, quadratic, reciprocal
+from hwcomponents_library.library.aladdin import AladdinComparator, AladdinCounter
+from hwcomponents_neurosim import FlipFlop
+
+
+class ZeroComparator(ComponentModel):
+    """
+    Counts the number of zeros in a list of values. Includes a flag for each zero.
+
+    Based on the zero gating logic in the paper: A Programmable Heterogeneous
+    Microprocessor Based on Bit-Scalable In-Memory Computing, by Hongyang Jia, Hossein
+    Valavi, Yinqi Tang, Jintao Zhang, and Naveen Verma, JSSC 2020
+    10.1109/JSSC.2020.2987714
+
+    Parameters
+    ----------
+    n_comparators: int
+        The number of comparators to include.
+    n_bits: int
+        The number of bits of each comparator.
+    tech_node: str
+        The technology node of the comparators.
+    voltage: float
+        The voltage of the comparators.
+    """
+
+    priority = 0.5
+
+    def __init__(
+        self,
+        n_comparators: int,
+        n_bits: int,
+        tech_node: str,
+        voltage: float = 0.85
+    ):
+        self.n_comparators = n_comparators
+        self.n_bits = n_bits
+
+        # Scale up the comparator to handle all the comparators
+        self.comparator = AladdinComparator(
+            n_bits=n_bits,
+            tech_node=tech_node,
+        )
+        self.comparator.energy_scale *= n_comparators
+        self.comparator.area_scale *= n_comparators
+
+        # Flip flops are used one bit at a time, so we only make one bit and scale the
+        # energy and latency
+        self.flip_flop = FlipFlop(
+            n_bits=1,
+            tech_node=tech_node,
+        )
+        self.flip_flop.energy_scale *= n_bits
+        self.flip_flop.latency_scale *= n_bits
+
+        # Zero counter is shared between all the comparators, so scale the energy and
+        # latency to activate with each one
+        self.zeros_counter = AladdinCounter(
+            n_bits=ceil(log2(n_comparators)),
+            tech_node=tech_node,
+        )
+        self.zeros_counter.energy_scale *= n_comparators
+        self.zeros_counter.latency_scale *= n_comparators
+
+        super().__init__(
+            subcomponents=[
+                self.comparator,
+                self.flip_flop,
+                self.zeros_counter,
+            ],
+        )
+
+        for subcomponent in self.subcomponents:
+            subcomponent.scale(
+                "voltage",
+                voltage,
+                0.85,
+                area_scale_function=linear,
+                energy_scale_function=quadratic,
+                latency_scale_function=reciprocal,
+                leak_power_scale_function=linear,
+
+            )
+            subcomponent.leak_power_scale *= 0.02  # Low-leakage technology
+
+    @action
+    def read(self) -> tuple[float, float]:
+        self.comparator.read()
+        self.flip_flop.read()
+        self.zeros_counter.read()

examples/arches/compute_in_memory/isaac.yaml

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+# @inproceedings{10.1109/ISCA.2016.12,
+# author = {Shafiee, Ali and Nag, Anirban and Muralimanohar, Naveen and Balasubramonian, Rajeev and Strachan, John Paul and Hu, Miao and Williams, R. Stanley and Srikumar, Vivek},
+# title = {ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars},
+# year = {2016},
+# isbn = {9781467389471},
+# publisher = {IEEE Press},
+# url = {https://doi.org/10.1109/ISCA.2016.12},
+# doi = {10.1109/ISCA.2016.12},
+# abstract = {A number of recent efforts have attempted to design accelerators for popular machine learning algorithms, such as those involving convolutional and deep neural networks (CNNs and DNNs). These algorithms typically involve a large number of multiply-accumulate (dot-product) operations. A recent project, DaDianNao, adopts a near data processing approach, where a specialized neural functional unit performs all the digital arithmetic operations and receives input weights from adjacent eDRAM banks.This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner. While the use of crossbar memory as an analog dot-product engine is well known, no prior work has designed or characterized a full-fledged accelerator based on crossbars. In particular, our work makes the following contributions: (i) We design a pipelined architecture, with some crossbars dedicated for each neural network layer, and eDRAM buffers that aggregate data between pipeline stages. (ii) We define new data encoding techniques that are amenable to analog computations and that can reduce the high overheads of analog-to-digital conversion (ADC). (iii) We define the many supporting digital components required in an analog CNN accelerator and carry out a design space exploration to identify the best balance of memristor storage/compute, ADCs, and eDRAM storage on a chip. On a suite of CNN and DNN workloads, the proposed ISAAC architecture yields improvements of 14.8\texttimes{}, 5.5\texttimes{}, and 7.5\texttimes{} in throughput, energy, and computational density (respectively), relative to the state-of-the-art DaDianNao architecture.},
+# booktitle = {Proceedings of the 43rd International Symposium on Computer Architecture},
+# pages = {14–26},
+# numpages = {13},
+# keywords = {CNN, DNN, accelerator, analog, memristor, neural},
+# location = {Seoul, Republic of Korea},
+# series = {ISCA '16}
+# }
+
+{{include_text('_include.yaml')}}
+{{add_to_path('./memory_cells')}}
+
+arch:
+  arch_globals_dependent_on_workload:
+    <<: *variables_global
+    # ===========================================================================
+    # Encoding-dependent parameters
+    # ===========================================================================
+    encoded_input_bits:  input_bits
+    encoded_weight_bits: weight_bits
+    encoded_output_bits: output_bits
+
+    input_encoding_func: offset_encode_hist
+    weight_encoding_func: offset_encode_hist
+
+    # For accuracy model. Can in-array accumulation include signed values?
+    # Signed accumulation not compatible with offset encoding (since offset
+    # encoding makes values non-negative).
+    signed_sum_across_inputs: False
+    signed_sum_across_weights: False
+
+    # ===========================================================================
+    # Architecture & CiM Array Structure
+    # ===========================================================================
+    # DEFINITIONS:
+    # - Cell: Smallest structure capable of storing memory. Note that a cell may
+    #         store more than one bit. For example, a cell consisting of a RRAM
+    #         device may store >1 bits, while a cell consisting of an SRAM
+    #         bitcell may store only 1 bit.
+    # - CiM Unit: Smallest structure capable of computing an analog MAC.
+    # - CiM Unit Width Cells:
+    #     Number of CiM unit cells that are accessed as one. These cells receive
+    #     one analog input and compute one analog MAC per timestep.
+    # - CiM Unit Depth Cells:
+    #     Number of independent groups of "CiM Unit Width" cells that form a CiM
+    #     unit. Each of these groups is indepently addressible and operates in
+    #     must be activated in a different timestep than the others.
+    cim_unit_width_cells:  1
+    cim_unit_depth_cells:  1
+    bits_per_cell:         2
+
+    # ===========================================================================
+    # Data Converters
+    # ===========================================================================
+    adc_resolution: 8
+    voltage_dac_resolution: 1
+    temporal_dac_resolution: 1
+
+    n_adc_per_bank: 1
+
+    # ===========================================================================
+    # Hardware
+    # ===========================================================================
+    cycle_period: 1e-9
+    read_pulse_width: 1e-9
+
+  extra_attributes_for_all_component_models:
+    <<: *cim_component_attributes
+    tech_node: tech_node
+    cycle_period: cycle_period
+
+  nodes:
+  - !Memory # Input buffer
+    name: InputBuffer
+    tensors: {keep: input}
+    size: MultiArrayFanout.get_fanout() * array_parallel_inputs * supported_input_bits
+    component_class: SmartBufferSRAM
+
+  - !Memory # Output buffer
+    name: OutputBuffer
+    tensors: {keep: output}
+    size: MultiArrayFanout.get_fanout() * array_parallel_outputs // min_weight_slices * supported_output_bits * 2
+    component_class: SmartBufferSRAM
+
+  - !ProcessingStage # Shift+add sums outputs from multiple slices
+    name: ShiftAdd
+    tensors: {keep: output}
+    direction: up
+    n_parallel_instances: MultiArrayFanout.get_fanout() # Match throughput with arrays
+    bits_per_action: output_bits / n_sliced_psums # n_sliced_psums reads to get an output
+    component_class: ISAACShiftAdd
+    extra_attributes_for_component_model:
+      n_bits: supported_output_bits
+      shift_register_n_bits: supported_output_bits * 2
+
+  - !Fanout # array: Independent array with memory elements and peripherals.
+    name: MultiArrayFanout
+    spatial:
+     - name: array
+       fanout: 8
+
+  - !ProcessingStage # ADC
+    name: ADC
+    tensors: {keep: output}
+    direction: up
+    bits_per_action: output_bits / n_sliced_psums # n_sliced_psums reads to get an output
+    component_class: ADC
+    energy_scale: adc_energy_scale
+    area_scale: adc_area_scale
+    extra_attributes_for_component_model:
+      throughput_scale: 1 / 100 # 100 cycles to process all outputs
+      throughput: 1 / cycle_period * cols_active_at_once * throughput_scale
+      n_bits: adc_resolution
+
+  - !ProcessingStage # Row drivers feed inputs onto the rows of the array
+    name: RowDrivers
+    tensors: {keep: input}
+    direction: down
+    bits_per_action: input_bits / n_input_slices # n_input_slices reads to send an input
+    component_class: ArrayRowDrivers
+
+  - !ProcessingStage # Column drivers precharge the array columns
+    name: ColumnDrivers
+    tensors: {keep: output}
+    direction: up
+    bits_per_action: output_bits / n_sliced_psums # n_sliced_psums reads to get an output
+    component_class: ArrayColumnDrivers
+
+  - !Fanout
+    name: ArrayFanout
+    spatial:
+    - name: array_reuse_input # Special name that determines array size
+      fanout: 128
+      may_reuse: input
+      reuse: input
+      min_usage: 1
+      usage_scale: n_weight_slices
+    - name: array_reuse_output # Special name that determines array size
+      fanout: 128
+      may_reuse: output
+      reuse: output
+      min_usage: 1
+
+  # This is the CiM unit that stores weights and computes MACs. Each CiM unit stores a
+  # different weight slice of up to cim_unit_width_cells bits. It may also store up to
+  # cim_unit_depth_cells independently-addressable weight slices, but may only compute
+  # MACs on one slice at a time. One of these components represents a collection of CiM
+  # units, that together hold one weight.
+  - !Memory
+    name: CimUnit
+    tensors: {keep: weight, no_refetch_from_above: weight, force_memory_hierarchy_order: False}
+    size: cim_unit_width_cells * cim_unit_depth_cells * bits_per_cell * n_weight_slices
+    # Requires (n_weight_slices * n_input_slices) = n_sliced_psums reads to fully use
+    # one weight
+    bits_per_action: weight.bits_per_value / n_sliced_psums
+    # Bind together n_weight_slices instances to hold one weight
+    n_parallel_instances: n_weight_slices
+    component_class: MemoryCell
+    extra_attributes_for_component_model:
+      n_instances: cim_unit_width_cells * cim_unit_depth_cells
+
+  # We account for compute energy in the CimUnit reads
+  - !Compute
+    name: FreeCompute
+    component_class: Dummy
+    enabled: len(All) == 3
+
+# These variables pertain to the workload, microarch, and circuits. They should
+# be matched between architectures when comparing for a fair comparison.
+# Furthermore, this file should follow the same format for all architectures
+# such that we can mix and match architectures with different iso files.
+variables:
+  # ===========================================================================
+  # Workload, microarch, circuits. Things that should be matched
+  # between architectures when comparing.
+  # ===========================================================================
+  # Set by CiM processor if these values are available in the workload.
+  # Otherwise, use the defaults here.
+  inputs_hist: [0, 0, 0, 3, 1, 0, 0]
+  weights_hist: [0, 1, 3, 4, 3, 1, 0]
+  outputs_hist: inputs_hist
+
+  ## Microarch ----------------------------------------------------------------
+  supported_input_bits: 8        # Maximum input bits supported by the arch.
+  supported_weight_bits: 8       # Maximum weight bits supported by the arch.
+  supported_output_bits: 8       # Maximum output bits supported by the arch.
+  min_supported_input_bits: 1    # Minimum input bits supported by the arch.
+  min_supported_weight_bits: 2   # Minimum weight bits supported by the arch.
+  min_supported_output_bits: 1   # Minimum output bits supported by the arch.
+
+  # Circuits ------------------------------------------------------------------
+  voltage: 1
+  tech_node: 32e-9 # nm
+  cell_config: "{{find_path('rram_isaac_isca_2016.yaml')}}"
+  voltage_energy_scale: voltage ** 2
+  voltage_latency_scale: voltage
+
+  # Calibration ---------------------------------------------------------------
+  adc_energy_scale: 1
+  adc_area_scale: 1
+  row_col_drivers_area_scale: 1
+
+
+# This workload is sized to get peak throughput & energy efficiency.
+workload:
+  rank_sizes:
+    M: 1
+    N: 16 * 8
+    K: 128
+
+  einsums:
+  - name: Matmul
+    tensor_accesses:
+    - {name: input, projection: [m, k], bits_per_value: 16}
+    - {name: weight, projection: [k, n], bits_per_value: 16}
+    - {name: output, projection: [m, n], output: True, bits_per_value: 16}
+
+  - name: Matmul2
+    tensor_accesses:
+    - {name: input2, projection: [m, k], bits_per_value: 32}
+    - {name: weight2, projection: [k, n], bits_per_value: 32}
+    - {name: output2, projection: [m, n], output: True, bits_per_value: 32}
+    renames: {input: input2, weight: weight2, output: output2}
+
+renames: {} # Not needed for this workload

examples/arches/compute_in_memory/memory_cells/ecram_demo.yaml

@@ -0,0 +1,63 @@
+# -----------------------------------------------------------------------------
+# Device type and top-level parameters
+
+# Device type
+-MemCellType: SRAM  # SRAM or RRAM
+# -ReadMode: current  # Comment this line for voltage
+-DeviceRoadmap -1LP 1HP 2LSTP:  2
+
+# Device size
+-CellArea (F^2):  24
+-CellAspectRatio: 1.25 # Width/Height
+
+# Calibration parameters
+-CellReadLeakEnergyMultiplier: 1
+-CellWriteEnergyMultiplier: 1
+-CellCapacitanceMultiplier: 0
+-CellCapacitanceAdjust (F): 0.174e-15 # Capacitance = (Nominal Capacitance) * Multiplier + Adjust
+
+# Used for RRAM with access transistors or SRAM
+-AccessCMOSWidth (F): 0
+
+# Affects NeuroSim-realized ADCs. NOTE: Most models use ADC plug-in ADCs and
+# this has little to no effect.
+-ReadMode: voltage # voltage or current
+
+# -----------------------------------------------------------------------------
+# SRAM-only parameters
+# SRAM configuration. Only used if MemCellType is SRAM
+-SRAMCellNMOSWidth (F): 2
+-SRAMCellPMOSWidth (F): 2
+-MinSenseVoltage (mV): 20
+
+# -----------------------------------------------------------------------------
+# RRAM-only parameters
+# RRAM configuration. Only used if MemCellType is RRAM
+-ResistanceOn (ohm): 625000
+-ResistanceOff (ohm): 10000000
+
+# Set parameters
+-SetVoltage (V): 2 # From PRIME
+-SetPulse (ns): 40
+# -SetCurrent (uA): 400 # OVERWRITES PREVIOUS LINES IF UNCOMMENTED
+# -SetEnergy (pJ): 8  # OVERWRITES PREVIOUS LINES IF UNCOMMENTED
+# -SetPower (uW): 800   # OVERWRITES PREVIOUS LINES IF UNCOMMENTED
+
+# Read parameters
+-ReadVoltage (V): 0.5 # From PRIME
+-ReadPulse (ns): 5
+# -ReadCurrent (uA): 40 # OVERWRITES PREVIOUS LINES IF UNCOMMENTED
+# -ReadEnergy (pJ): 0.008  # OVERWRITES PREVIOUS LINES IF UNCOMMENTED
+# -ReadPower (uW): 8   # OVERWRITES PREVIOUS LINES IF UNCOMMENTED
+
+# Access transistor parameters
+-AccessType: None   # CMOS or None
+-AccessTransistorResistance (ohm): 1000
+-AccessVoltage (V): 0.1 # Access transistor voltage
+
+# -----------------------------------------------------------------------------
+# Other parameters that can be set via cell component attributes:
+
+# "voltage" is the global supply voltage
+# "threshold_voltage" is the global threshold voltage
+# "read_pulse_width" is the read pulse width