PyNerva 0.0.7__py3-none-any.whl

nervapy/__init__.py

@@ -0,0 +1,50 @@
+# This file is part of NervaPy package and is licensed under the Simplified BSD license.
+#    See license.rst for the full text of the license.
+
+__version_info__ = (0, 2, 0)
+__version__ = ".".join(map(str, __version_info__))
+
+from nervapy.c.types import (Float16, Float32, Float64, Type, Yep8s, Yep8u,
+                             Yep16f, Yep16s, Yep16u, Yep32f, Yep32s, Yep32u,
+                             Yep64f, Yep64s, Yep64u, YepSize, char, const_char,
+                             const_double_, const_Float16, const_Float32,
+                             const_Float64, const_float_, const_int8_t,
+                             const_int16_t, const_int32_t, const_int64_t,
+                             const_intptr_t, const_ptr, const_ptrdiff_t,
+                             const_signed_char, const_signed_int,
+                             const_signed_long, const_signed_long_long,
+                             const_signed_short, const_size_t, const_uint8_t,
+                             const_uint16_t, const_uint32_t, const_uint64_t,
+                             const_uintptr_t, const_unsigned_char,
+                             const_unsigned_int, const_unsigned_long,
+                             const_unsigned_long_long, const_unsigned_short,
+                             const_wchar_t, const_Yep8s, const_Yep8u,
+                             const_Yep16f, const_Yep16s, const_Yep16u,
+                             const_Yep32f, const_Yep32s, const_Yep32u,
+                             const_Yep64f, const_Yep64s, const_Yep64u,
+                             const_YepSize, double_, float_, int8_t, int16_t,
+                             int32_t, int64_t, intptr_t, ptr, ptrdiff_t,
+                             signed_char, signed_int, signed_long,
+                             signed_long_long, signed_short, size_t, uint8_t,
+                             uint16_t, uint32_t, uint64_t, uintptr_t,
+                             unsigned_char, unsigned_int, unsigned_long,
+                             unsigned_long_long, unsigned_short, wchar_t)
+from nervapy.function import Argument
+from nervapy.literal import Constant
+from nervapy.stream import InstructionStream
+
+
+class ConstantBucket:
+    def __init__(self, capacity):
+        self.capacity = capacity
+        self.constants = []
+
+    def add(self, constant):
+        self.constants.append(constant)
+
+    def is_full(self):
+        return False  # Simple implementation for now
+
+
+class RegisterAllocationError(Exception):
+    pass

nervapy/abi.py

@@ -0,0 +1,91 @@
+# This file is part of PeachPy package and is licensed under the Simplified BSD license.
+#    See license.rst for the full text of the license.
+
+
+class Endianness:
+    Big, Little = "Big-Endian", "Little-Endian"
+
+
+class ABI(object):
+    def __init__(
+        self,
+        name,
+        endianness,
+        bool_size,
+        wchar_size,
+        short_size,
+        int_size,
+        long_size,
+        longlong_size,
+        pointer_size,
+        index_size,
+        stack_alignment,
+        red_zone,
+        callee_save_registers,
+        argument_registers,
+        volatile_registers,
+        restricted_registers=[],
+        elf_class=None,
+        elf_data_encoding=None,
+        elf_machine_type=None,
+        mscoff_machine_type=None,
+    ):
+        super(ABI, self).__init__()
+        self.name = name
+        self.endianness = endianness
+        self.bool_size = bool_size
+        self.wchar_size = wchar_size
+        self.short_size = short_size
+        self.int_size = int_size
+        self.long_size = long_size
+        self.longlong_size = longlong_size
+        self.pointer_size = pointer_size
+        self.index_size = index_size
+        self.stack_alignment = stack_alignment
+        self.red_zone = red_zone
+        self.callee_save_registers = callee_save_registers
+        self.argument_registers = argument_registers
+        self.volatile_registers = volatile_registers
+        self.restricted_registers = restricted_registers
+        self.elf_class = elf_class
+        self.elf_data_encoding = elf_data_encoding
+        self.elf_machine_type = elf_machine_type
+        self.mscoff_machine_type = mscoff_machine_type
+
+    def __eq__(self, other):
+        return isinstance(other, ABI) and self.name == other.name
+
+    def __ne__(self, other):
+        return not isinstance(other, ABI) or self.name != other.name
+
+    def __hash__(self):
+        return hash(self.name)
+
+    def __str__(self):
+        return self.name
+
+    def __repr__(self):
+        return str(self)
+
+    @property
+    def is_elf_compatible(self):
+        return (
+            self.elf_class is not None
+            and self.elf_data_encoding is not None
+            and self.elf_machine_type is not None
+        )
+
+    @property
+    def is_mscoff_compatible(self):
+        return self.mscoff_machine_type is not None
+
+    @property
+    def is_macho_compatible(self):
+        return False
+
+    @property
+    def elf_bitness(self):
+        if self.elf_class is not None:
+            from nervapy.formats.elf.file import ElfClass
+
+            return {ElfClass.class32: 32, ElfClass.class64: 64}[self.elf_class]

nervapy/arm/__init__.py

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+# This file is part of PeachPy package and is licensed under the Simplified BSD license.
+#    See license.rst for the full text of the license.
+
+import nervapy
+import nervapy.arm.abi
+import nervapy.arm.isa
+from nervapy.arm.formats import AssemblyFormat, HighRegisterStrategy
+from nervapy.arm.function import Function, print_live_registers
+from nervapy.arm.generic import (ADC, ADCCC, ADCCS, ADCEQ, ADCGE, ADCGT, ADCHI,
+                                 ADCHS, ADCLE, ADCLO, ADCLS, ADCLT, ADCMI,
+                                 ADCNE, ADCPL, ADCS, ADCSCC, ADCSCS, ADCSEQ,
+                                 ADCSGE, ADCSGT, ADCSHI, ADCSHS, ADCSLE,
+                                 ADCSLO, ADCSLS, ADCSLT, ADCSMI, ADCSNE,
+                                 ADCSPL, ADCSVC, ADCSVS, ADCVC, ADCVS, ADD,
+                                 ADDCC, ADDCS, ADDEQ, ADDGE, ADDGT, ADDHI,
+                                 ADDHS, ADDLE, ADDLO, ADDLS, ADDLT, ADDMI,
+                                 ADDNE, ADDPL, ADDS, ADDSCC, ADDSCS, ADDSEQ,
+                                 ADDSGE, ADDSGT, ADDSHI, ADDSHS, ADDSLE,
+                                 ADDSLO, ADDSLS, ADDSLT, ADDSMI, ADDSNE,
+                                 ADDSPL, ADDSVC, ADDSVS, ADDVC, ADDVS, ADR,
+                                 AND, AND_W, ANDCC, ANDCS, ANDEQ, ANDGE, ANDGT,
+                                 ANDHI, ANDHS, ANDLE, ANDLO, ANDLS, ANDLT,
+                                 ANDMI, ANDNE, ANDPL, ANDS, ANDSCC, ANDSCS,
+                                 ANDSEQ, ANDSGE, ANDSGT, ANDSHI, ANDSHS,
+                                 ANDSLE, ANDSLO, ANDSLS, ANDSLT, ANDSMI,
+                                 ANDSNE, ANDSPL, ANDSVC, ANDSVS, ANDVC, ANDVS,
+                                 ASR, BCC, BCS, BEQ, BFC, BFI, BGE, BGT, BHI,
+                                 BHS, BIC, BICCC, BICCS, BICEQ, BICGE, BICGT,
+                                 BICHI, BICHS, BICLE, BICLO, BICLS, BICLT,
+                                 BICMI, BICNE, BICPL, BICS, BICSCC, BICSCS,
+                                 BICSEQ, BICSGE, BICSGT, BICSHI, BICSHS,
+                                 BICSLE, BICSLO, BICSLS, BICSLT, BICSMI,
+                                 BICSNE, BICSPL, BICSVC, BICSVS, BICVC, BICVS,
+                                 BKPT, BL, BLE, BLO, BLS, BLT, BLX, BLXNS, BMI,
+                                 BNE, BPL, BVC, BVS, BX, BXNS, CBNZ, CBZ, CMP,
+                                 CMPCC, CMPCS, CMPEQ, CMPGE, CMPGT, CMPHI,
+                                 CMPHS, CMPLE, CMPLO, CMPLS, CMPLT, CMPMI,
+                                 CMPNE, CMPPL, CMPVC, CMPVS, EOR, EOR_W, EORCC,
+                                 EORCS, EOREQ, EORGE, EORGT, EORHI, EORHS,
+                                 EORLE, EORLO, EORLS, EORLT, EORMI, EORNE,
+                                 EORPL, EORS, EORSCC, EORSCS, EORSEQ, EORSGE,
+                                 EORSGT, EORSHI, EORSHS, EORSLE, EORSLO,
+                                 EORSLS, EORSLT, EORSMI, EORSNE, EORSPL,
+                                 EORSVC, EORSVS, EORVC, EORVS, LDMDB, LDMIA,
+                                 LDR, LDR_W, LDRB, LDRB_W, LDRD, LDRH, LDRH_W,
+                                 LDRSB, LDRSB_W, LDRSH, LDRSH_W, LSL, LSR, MIA,
+                                 MIAPH, MLA, MLS, MOV, MOV_W, MOVCC, MOVCS,
+                                 MOVEQ, MOVGE, MOVGT, MOVHI, MOVHS, MOVLE,
+                                 MOVLO, MOVLS, MOVLT, MOVMI, MOVNE, MOVPL,
+                                 MOVS, MOVSCC, MOVSCS, MOVSEQ, MOVSGE, MOVSGT,
+                                 MOVSHI, MOVSHS, MOVSLE, MOVSLO, MOVSLS,
+                                 MOVSLT, MOVSMI, MOVSNE, MOVSPL, MOVSVC,
+                                 MOVSVS, MOVT, MOVVC, MOVVS, MUL, MVN, ORR,
+                                 ORRCC, ORRCS, ORREQ, ORRGE, ORRGT, ORRHI,
+                                 ORRHS, ORRLE, ORRLO, ORRLS, ORRLT, ORRMI,
+                                 ORRNE, ORRPL, ORRS, ORRSCC, ORRSCS, ORRSEQ,
+                                 ORRSGE, ORRSGT, ORRSHI, ORRSHS, ORRSLE,
+                                 ORRSLO, ORRSLS, ORRSLT, ORRSMI, ORRSNE,
+                                 ORRSPL, ORRSVC, ORRSVS, ORRVC, ORRVS, POP,
+                                 POP_W, PUSH, PUSH_W, ROR, RSB, RSBCC, RSBCS,
+                                 RSBEQ, RSBGE, RSBGT, RSBHI, RSBHS, RSBLE,
+                                 RSBLO, RSBLS, RSBLT, RSBMI, RSBNE, RSBPL,
+                                 RSBS, RSBSCC, RSBSCS, RSBSEQ, RSBSGE, RSBSGT,
+                                 RSBSHI, RSBSHS, RSBSLE, RSBSLO, RSBSLS,
+                                 RSBSLT, RSBSMI, RSBSNE, RSBSPL, RSBSVC,
+                                 RSBSVS, RSBVC, RSBVS, RSC, RSCCC, RSCCS,
+                                 RSCEQ, RSCGE, RSCGT, RSCHI, RSCHS, RSCLE,
+                                 RSCLO, RSCLS, RSCLT, RSCMI, RSCNE, RSCPL,
+                                 RSCS, RSCSCC, RSCSCS, RSCSEQ, RSCSGE, RSCSGT,
+                                 RSCSHI, RSCSHS, RSCSLE, RSCSLO, RSCSLS,
+                                 RSCSLT, RSCSMI, RSCSNE, RSCSPL, RSCSVC,
+                                 RSCSVS, RSCVC, RSCVS, SBC, SBCCC, SBCCS,
+                                 SBCEQ, SBCGE, SBCGT, SBCHI, SBCHS, SBCLE,
+                                 SBCLO, SBCLS, SBCLT, SBCMI, SBCNE, SBCPL,
+                                 SBCS, SBCSCC, SBCSCS, SBCSEQ, SBCSGE, SBCSGT,
+                                 SBCSHI, SBCSHS, SBCSLE, SBCSLO, SBCSLS,
+                                 SBCSLT, SBCSMI, SBCSNE, SBCSPL, SBCSVC,
+                                 SBCSVS, SBCVC, SBCVS, SG, SMLABBNE, SMLABT,
+                                 SMLAD, SMLAL, SMLALBB, SMLALBT, SMLALD,
+                                 SMLALTB, SMLALTT, SMLAWB, SMLAWT, SMLSD,
+                                 SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULL,
+                                 SMULTBEQ, SMULWB, SMULWT, SMUSD, SMUSDXNE,
+                                 STMDB, STMIA, STR, STR_W, STRB, STRB_W, STRD,
+                                 STRH, STRH_W, SUB, SUBCC, SUBCS, SUBEQ, SUBGE,
+                                 SUBGT, SUBHI, SUBHS, SUBLE, SUBLO, SUBLS,
+                                 SUBLT, SUBMI, SUBNE, SUBPL, SUBS, SUBSCC,
+                                 SUBSCS, SUBSEQ, SUBSGE, SUBSGT, SUBSHI,
+                                 SUBSHS, SUBSLE, SUBSLO, SUBSLS, SUBSLT,
+                                 SUBSMI, SUBSNE, SUBSPL, SUBSVC, SUBSVS, SUBVC,
+                                 SUBVS, TEQ, TEQCC, TEQCS, TEQEQ, TEQGE, TEQGT,
+                                 TEQHI, TEQHS, TEQLE, TEQLO, TEQLS, TEQLT,
+                                 TEQMI, TEQNE, TEQPL, TEQVC, TEQVS, TST, TSTCC,
+                                 TSTCS, TSTEQ, TSTGE, TSTGT, TSTHI, TSTHS,
+                                 TSTLE, TSTLO, TSTLS, TSTLT, TSTMI, TSTNE,
+                                 TSTPL, TSTVC, TSTVS, TT, TTA, TTAT, TTT,
+                                 UMAAL, UMAALGE, UMLAL, UMULL, B)
+from nervapy.arm.literal_pool import LDR_LITERAL, LDRL
+from nervapy.arm.microarchitecture import Microarchitecture
+from nervapy.arm.pseudo import (ALIGN, ASSUME, IMPORT, INIT, LABEL, LOAD,
+                                REDUCE, RETURN, STORE, SWAP, ExternalFunction,
+                                Label, Loop)
+from nervapy.arm.registers import (DRegister, GeneralPurposeRegister,
+                                   PRegister, QRegister, SRegister,
+                                   VPRRegister, WMMXRegister, d0, d1, d2, d3,
+                                   d4, d5, d6, d7, d8, d9, d10, d11, d12, d13,
+                                   d14, d15, lr, p0, p1, p2, p3, p4, p5, p6,
+                                   p7, pc, q0, q1, q2, q3, q4, q5, q6, q7, r0,
+                                   r1, r2, r3, r4, r5, r6, r7, r8, r9, r10,
+                                   r11, r12, s0, s1, s2, s3, s4, s5, s6, s7,
+                                   s8, s9, s10, s11, s12, s13, s14, s15, s16,
+                                   s17, s18, s19, s20, s21, s22, s23, s24, s25,
+                                   s26, s27, s28, s29, s30, s31, vpr, wr0, wr1,
+                                   wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9,
+                                   wr10, wr11, wr12, wr13, wr14, wr15)
+from nervapy.arm.vfpneon import (VABD, VABS, VACGE, VACGT, VACLE, VACLT, VADD,
+                                 VADDL, VAND, VBIC, VDIV, VEOR, VFMA, VFMS,
+                                 VFNMA, VFNMS, VHADD, VHSUB, VLD1, VLDM,
+                                 VLDMDB, VLDMIA, VLDR, VMAX, VMIN, VMLA, VMLS,
+                                 VMOV, VMUL, VMULL, VNEG, VNMLA, VNMLS, VNMUL,
+                                 VORN, VORR, VPADD, VPMAX, VPMIN, VQADD, VQSUB,
+                                 VRECPS, VRHADD, VRSQRTS, VSQRT, VST1, VSTM,
+                                 VSTMDB, VSTMIA, VSTR, VSUB, VSUBL, VTST)
+
+__m64 = nervapy.Type("__m64", size=8, is_vector=True, header="mmintrin.h")

nervapy/arm/abi.py

@@ -0,0 +1,138 @@
+# This file is part of PeachPy package and is licensed under the Simplified BSD license.
+#    See license.rst for the full text of the license.
+
+from nervapy.abi import ABI, Endianness
+from nervapy.arm.registers import (d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
+                                   d11, d12, d13, d14, d15, d16, d17, d18, d19,
+                                   d20, d21, d22, d23, d24, d25, d26, d27, d28,
+                                   d29, d30, d31, r0, r1, r2, r3, r4, r5, r6,
+                                   r7, r8, r9, r10, r11, r12)
+from nervapy.formats.elf.file import DataEncoding, ElfClass, MachineType
+
+arm_gnueabi = ABI(
+    "GNU Soft-Float ARM EABI",
+    endianness=Endianness.Little,
+    bool_size=1,
+    wchar_size=2,
+    short_size=2,
+    int_size=4,
+    long_size=4,
+    longlong_size=8,
+    pointer_size=4,
+    index_size=4,
+    stack_alignment=8,
+    red_zone=0,
+    callee_save_registers=[
+        r4,
+        r5,
+        r6,
+        r7,
+        r8,
+        r9,
+        r10,
+        r11,
+        d8,
+        d9,
+        d10,
+        d11,
+        d12,
+        d13,
+        d14,
+        d15,
+    ],
+    argument_registers=[r0, r1, r2, r3],
+    volatile_registers=[
+        r12,
+        d0,
+        d1,
+        d2,
+        d3,
+        d4,
+        d5,
+        d6,
+        d7,
+        d16,
+        d17,
+        d18,
+        d19,
+        d20,
+        d21,
+        d22,
+        d23,
+        d24,
+        d25,
+        d26,
+        d27,
+        d28,
+        d29,
+        d30,
+        d31,
+    ],
+    elf_class=ElfClass.class32,
+    elf_data_encoding=DataEncoding.little_endian,
+    elf_machine_type=MachineType.arm,
+)
+
+arm_gnueabihf = ABI(
+    "GNU Hard-Float ARM EABI",
+    endianness=Endianness.Little,
+    bool_size=1,
+    wchar_size=2,
+    short_size=2,
+    int_size=4,
+    long_size=4,
+    longlong_size=8,
+    pointer_size=4,
+    index_size=4,
+    stack_alignment=8,
+    red_zone=0,
+    callee_save_registers=[
+        r4,
+        r5,
+        r6,
+        r7,
+        r8,
+        r9,
+        r10,
+        r11,
+        d8,
+        d9,
+        d10,
+        d11,
+        d12,
+        d13,
+        d14,
+        d15,
+    ],
+    argument_registers=[r0, r1, r2, r3],
+    volatile_registers=[
+        r12,
+        d0,
+        d1,
+        d2,
+        d3,
+        d4,
+        d5,
+        d6,
+        d7,
+        d16,
+        d17,
+        d18,
+        d19,
+        d20,
+        d21,
+        d22,
+        d23,
+        d24,
+        d25,
+        d26,
+        d27,
+        d28,
+        d29,
+        d30,
+        d31,
+    ],
+    elf_class=ElfClass.class32,
+    elf_data_encoding=DataEncoding.little_endian,
+    elf_machine_type=MachineType.arm,
+)

nervapy/arm/formats.py

@@ -0,0 +1,49 @@
+# This file is part of PeachPy package and is licensed under the Simplified BSD license.
+#    See license.rst for the full text of the license.
+
+from typing import Optional
+
+
+class AssemblyFormat:
+    """Defines different assembly output formats for ARM processors."""
+
+    def __init__(self, name):
+        self.name = name
+
+    def __str__(self):
+        return self.name
+
+    def __eq__(self, other):
+        return self.name == other.name
+
+    # Assembly format constants
+    GAS: Optional["AssemblyFormat"] = None  # GNU Assembler (default)
+    ARMCC: Optional["AssemblyFormat"] = None  # ARM Compiler armasm
+
+
+class HighRegisterStrategy:
+    """Defines strategies for handling high registers (r8-r15) in ARMv7-M."""
+
+    def __init__(self, name):
+        self.name = name
+
+    def __str__(self):
+        return self.name
+
+    def __eq__(self, other):
+        return self.name == other.name
+
+    # High register handling strategies
+    PUSH_W: Optional["HighRegisterStrategy"] = None  # Use PUSH.W/POP.W for high registers (modern, efficient)
+    STMDB: Optional["HighRegisterStrategy"] = None  # Use STMDB sp!/LDMIA sp! for high registers (compatible)
+    AUTO: Optional["HighRegisterStrategy"] = None  # Automatically choose based on target and assembler
+
+
+# Initialize format constants
+AssemblyFormat.GAS = AssemblyFormat("GAS")
+AssemblyFormat.ARMCC = AssemblyFormat("ARMCC")
+
+# Initialize strategy constants
+HighRegisterStrategy.PUSH_W = HighRegisterStrategy("PUSH_W")
+HighRegisterStrategy.STMDB = HighRegisterStrategy("STMDB")
+HighRegisterStrategy.AUTO = HighRegisterStrategy("AUTO")