webserial-flasher 1.0.0

package/dist/protocol/updi/constants.js

@@ -0,0 +1,130 @@
+// UPDI (Unified Program and Debug Interface) protocol constants.
+// Covers tinyAVR 0/1/2 series, megaAVR 0 series (ATmega4809).
+// Reference: AVR® DA/DB Device Series Datasheet (Microchip Technology)
+//            Atmel ATtiny1614/16/17 datasheet — UPDI chapter
+// ── Physical layer ───────────────────────────────────────────────────────────
+/** UPDI synchronisation byte — sent before every instruction */
+export const UPDI_SYNC = 0x55;
+/** ACK byte returned by device for write operations */
+export const UPDI_ACK = 0x40;
+// ── Instruction opcodes (bits 7:5) ────────────────────────────────────────────
+/** LDS — Load from Data Space (followed by address + returns data) */
+export const UPDI_LDS = 0x00;
+/** STS — Store to Data Space (followed by address + data) */
+export const UPDI_STS = 0x40;
+/** LD  — Load indirect (uses pointer register) */
+export const UPDI_LD = 0x20;
+/** ST  — Store indirect (uses pointer register) */
+export const UPDI_ST = 0x60;
+/** LDCS — Load from Control/Status Space */
+export const UPDI_LDCS = 0x80;
+/** STCS — Store to Control/Status Space */
+export const UPDI_STCS = 0xC0;
+/** REPEAT — Repeat the next instruction N+1 times */
+export const UPDI_REPEAT = 0xA0;
+/** KEY  — Key broadcast (8 or 16 bytes) */
+export const UPDI_KEY = 0xE0;
+// ── Address/data size operands ────────────────────────────────────────────────
+/** Address operand: 1-byte address */
+export const UPDI_ADDRESS_8 = 0;
+/** Address operand: 2-byte address (default for all AVR NVM access) */
+export const UPDI_ADDRESS_16 = 1;
+/** Address operand: 3-byte address (AVR DA/DB extended addressing) */
+export const UPDI_ADDRESS_24 = 2;
+/** Data operand: 1-byte data */
+export const UPDI_DATA_8 = 0;
+/** Data operand: 2-byte data */
+export const UPDI_DATA_16 = 1;
+// ── Pointer modes (bits 4:2 for LD/ST instructions) ──────────────────────────
+/** Pointer mode: access *(ptr) */
+export const UPDI_PTR = 0;
+/** Pointer mode: access *(ptr++) — post-increment */
+export const UPDI_PTR_INC = 1;
+/** Pointer mode: access *(--ptr) — pre-decrement */
+export const UPDI_PTR_DEC = 2;
+// ── Key sizes (bits 1:0 of KEY instruction) ──────────────────────────────────
+/** 8-byte (64-bit) key */
+export const UPDI_KEY_SIZE_64 = 0;
+/** 16-byte (128-bit) key */
+export const UPDI_KEY_SIZE_128 = 1;
+// ── Control/Status register addresses ────────────────────────────────────────
+export const UPDI_CS_STATUSA = 0x00;
+export const UPDI_CS_STATUSB = 0x01;
+export const UPDI_CS_CTRLA = 0x02;
+export const UPDI_CS_CTRLB = 0x03;
+/** ASI_KEY_STATUS — shows which key is currently active */
+export const UPDI_CS_ASI_KEY_STATUS = 0x07;
+/** ASI_RESET_REQ  — write 0x59 to assert reset, 0x00 to deassert */
+export const UPDI_CS_ASI_RESET_REQ = 0x08;
+export const UPDI_CS_ASI_CTRL_A = 0x09;
+export const UPDI_CS_ASI_SYS_CTRLA = 0x0A;
+/** ASI_SYS_STATUS — NVMPROG / LOCKSTATUS / UROWPROG bits */
+export const UPDI_CS_ASI_SYS_STATUS = 0x0B;
+// ── CTRLA bits ───────────────────────────────────────────────────────────────
+/** Guard-time insertion delay (IBDLY) */
+export const UPDI_CTRLA_IBDLY = 0x80;
+/** Guard-time value: 2-cycle inter-byte delay (minimises wait between bytes) */
+export const UPDI_CTRLA_GT_2 = 0x06;
+// ── ASI_KEY_STATUS bits ───────────────────────────────────────────────────────
+export const UPDI_KEY_CHIPERASE = 0x08;
+export const UPDI_KEY_NVMPROG = 0x10;
+export const UPDI_KEY_UROWWRITE = 0x20;
+// ── ASI_SYS_STATUS bits ───────────────────────────────────────────────────────
+export const UPDI_SYS_RSTSYS = 0x20;
+export const UPDI_SYS_INSLEEP = 0x10;
+export const UPDI_SYS_NVMPROG = 0x08;
+export const UPDI_SYS_UROWPROG = 0x04;
+export const UPDI_SYS_LOCKSTATUS = 0x01;
+// ── Reset request byte ────────────────────────────────────────────────────────
+export const UPDI_RESET_REQ_ASSERT = 0x59;
+export const UPDI_RESET_REQ_DEASSERT = 0x00;
+// ── NVM Controller (NVMv0 — tinyAVR 0/1/2, megaAVR 0) ───────────────────────
+export const NVM_BASE = 0x1000;
+export const NVM_CTRLA = 0x1000;
+export const NVM_CTRLB = 0x1001;
+export const NVM_STATUS = 0x1002;
+export const NVM_INTCTRL = 0x1003;
+export const NVM_INTFLAGS = 0x1004;
+export const NVM_DATA = 0x1006;
+export const NVM_ADDR = 0x1008; // 16-bit address register
+// ── NVM status bits ───────────────────────────────────────────────────────────
+/** Flash busy — poll until cleared after write/erase */
+export const NVM_FBUSY = 0x01;
+/** EEPROM busy */
+export const NVM_EEBUSY = 0x02;
+/** Write error */
+export const NVM_WRERR = 0x04;
+// ── NVM commands (write to NVM_CTRLA) ────────────────────────────────────────
+export const NVM_CMD_NOP = 0x00; // No operation (clear previous command)
+export const NVM_CMD_WP = 0x01; // Write page (from buffer)
+export const NVM_CMD_ER = 0x02; // Erase page
+export const NVM_CMD_ERWP = 0x03; // Erase and write page (most common for flash)
+export const NVM_CMD_PBC = 0x04; // Page buffer clear
+export const NVM_CMD_CHER = 0x05; // Chip erase (clears flash + EEPROM + fuses to reset values)
+export const NVM_CMD_EEER = 0x06; // EEPROM only erase
+export const NVM_CMD_WFU = 0x07; // Write fuse
+// ── SIGROW (signature row) ────────────────────────────────────────────────────
+/** Default SIGROW base address — contains 3-byte device ID at offset 0 */
+export const SIGROW_BASE = 0x1100;
+/** EEPROM base address (tinyAVR 0/1/2 and megaAVR 0) */
+export const EEPROM_BASE = 0x1400;
+/** Fuse register base (tinyAVR 0/1/2) */
+export const FUSE_BASE = 0x1280;
+/** Number of fuse registers */
+export const FUSE_COUNT = 6;
+// ── Authentication keys (8 bytes, LSB-first as sent on the wire) ─────────────
+/**
+ * NVMProg key — grants access to NVM controller for flash/EEPROM/fuse writes.
+ * ASCII: "NVMProg " reversed to [0x20, 0x67, 0x6F, 0x72, 0x50, 0x4D, 0x56, 0x4E]
+ */
+export const UPDI_KEY_NVM_PROG = new Uint8Array([
+    0x20, 0x67, 0x6F, 0x72, 0x50, 0x4D, 0x56, 0x4E,
+]);
+/**
+ * ChipErase key — grants a single chip erase operation even on a locked device.
+ * ASCII: "NVMErase" reversed
+ */
+export const UPDI_KEY_CHIP_ERASE_REQ = new Uint8Array([
+    0x65, 0x73, 0x61, 0x72, 0x45, 0x4D, 0x56, 0x4E,
+]);
+//# sourceMappingURL=constants.js.map

package/dist/protocol/updi/constants.js.map

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package/dist/protocol/updi/link.d.ts

@@ -0,0 +1,82 @@
+import type { ISTKTransport } from '../../transport/ITransport.js';
+import type { Board, Logger } from '../../core/types.js';
+export declare class UPDILink {
+    private readonly transport;
+    private readonly board;
+    private readonly log;
+    constructor(transport: ISTKTransport, board: Board, log: Logger);
+    /**
+     * Write bytes and discard the echo (TX loopback).
+     * After this returns the transport's receive buffer contains only device
+     * responses, not echo bytes.
+     */
+    send(bytes: number[]): Promise<void>;
+    /**
+     * Receive exactly `count` bytes from the transport.
+     * Accumulates chunks until the total reaches `count`, then resolves.
+     * Rejects with STK500TimeoutError if the deadline expires.
+     */
+    receiveExact(count: number): Promise<Uint8Array>;
+    /**
+     * Read one byte from a UPDI Control/Status register.
+     * LDCS sequence: SYNC + (0x80 | addr) → echo 2 bytes → read 1 byte
+     */
+    ldcs(addr: number): Promise<number>;
+    /**
+     * Write one byte to a UPDI Control/Status register.
+     * STCS sequence: SYNC + (0xC0 | addr) + val → echo 3 bytes → read 1 ACK
+     */
+    stcs(addr: number, val: number): Promise<void>;
+    /**
+     * Read one byte from a 16-bit data-space address.
+     * LDS sequence: SYNC + 0x04 + addrL + addrH → echo 4 bytes → read 1 byte
+     */
+    lds(addr: number): Promise<number>;
+    /**
+     * Write one byte to a 16-bit data-space address.
+     * STS sequence:
+     *   → SYNC + 0x44 + addrL + addrH → echo 4 bytes → read 1 ACK
+     *   → val                           → echo 1 byte  → read 1 ACK
+     */
+    sts(addr: number, val: number): Promise<void>;
+    /**
+     * Load a 16-bit address into the UPDI pointer register.
+     * ST(ptr, 16-bit) sequence: SYNC + 0x61 + addrL + addrH → echo 4 bytes → read 1 ACK
+     */
+    setPtr(addr: number): Promise<void>;
+    /**
+     * Write a block of bytes to memory using ST ptr++ (with optional REPEAT).
+     *
+     * For count > 1, a REPEAT instruction is sent first so the device auto-advances
+     * the pointer.  Each byte requires: send byte → discard echo → read ACK.
+     */
+    stPtrInc(data: Uint8Array): Promise<void>;
+    /**
+     * Read a block of bytes using LD ptr++ (with optional REPEAT).
+     *
+     * For count > 1, a REPEAT is sent first.  The device streams back `count`
+     * data bytes directly — no echoes for reads.
+     */
+    ldPtrInc(count: number): Promise<Uint8Array>;
+    /**
+     * Broadcast an 8-byte key to unlock NVM or chip-erase operations.
+     * KEY sequence: SYNC + 0xE0 + 8 key bytes → echo 10 bytes → no ACK
+     */
+    sendKey(key: Uint8Array): Promise<void>;
+    /**
+     * Configure guard time to minimum (2 cycles) for faster communication.
+     * Called once after establishing the link.
+     */
+    configureGuardTime(): Promise<void>;
+    /**
+     * Read a contiguous memory region.
+     * Internally uses setPtr + ldPtrInc.
+     */
+    readMemory(addr: number, size: number): Promise<Uint8Array>;
+    /**
+     * Write a contiguous memory region.
+     * Internally uses setPtr + stPtrInc.
+     */
+    writeMemory(addr: number, data: Uint8Array): Promise<void>;
+}
+//# sourceMappingURL=link.d.ts.map

package/dist/protocol/updi/link.d.ts.map

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package/dist/protocol/updi/link.js

@@ -0,0 +1,241 @@
+// UPDI Link Layer — low-level byte I/O over a half-duplex single-wire interface.
+//
+// UPDI uses a single GPIO for both TX and RX (the UPDI pin).  When bytes are
+// transmitted, the same bytes are physically looped back to the RX line
+// (half-duplex UART echo).  The link layer must:
+//
+//   1. Write bytes to the transport.
+//   2. Read and discard the same N bytes (the TX echo).
+//   3. Then read the actual device response.
+//
+// All public methods handle echo cancellation internally — callers see a clean
+// request/response interface.
+//
+// Reference: Microchip AVR® UPDI Programming Interface Application Note (DS40002312)
+import { UPDI_SYNC, UPDI_ACK, UPDI_LDCS, UPDI_STCS, UPDI_LDS, UPDI_STS, UPDI_LD, UPDI_ST, UPDI_REPEAT, UPDI_KEY, UPDI_ADDRESS_16, UPDI_DATA_8, UPDI_DATA_16, UPDI_PTR, UPDI_PTR_INC, UPDI_KEY_SIZE_64, UPDI_CTRLA_GT_2, UPDI_CS_CTRLA, } from './constants.js';
+import { STK500TimeoutError, STK500ProtocolError } from '../../core/errors.js';
+// Pre-computed instruction byte constants
+const INSTR_LDCS_BASE = UPDI_LDCS; // 0x80
+const INSTR_STCS_BASE = UPDI_STCS; // 0xC0
+const INSTR_LDS_16_8 = UPDI_LDS | (UPDI_ADDRESS_16 << 2) | UPDI_DATA_8; // 0x04
+const INSTR_STS_16_8 = UPDI_STS | (UPDI_ADDRESS_16 << 2) | UPDI_DATA_8; // 0x44
+const INSTR_ST_PTR_16 = UPDI_ST | (UPDI_PTR << 2) | UPDI_DATA_16; // 0x61 (set pointer)
+const INSTR_ST_PTR_INC = UPDI_ST | (UPDI_PTR_INC << 2) | UPDI_DATA_8; // 0x64
+const INSTR_LD_PTR_INC = UPDI_LD | (UPDI_PTR_INC << 2) | UPDI_DATA_8; // 0x24
+const INSTR_REPEAT_8 = UPDI_REPEAT | UPDI_DATA_8; // 0xA0
+const INSTR_KEY_64 = UPDI_KEY | UPDI_KEY_SIZE_64; // 0xE0
+export class UPDILink {
+    constructor(transport, board, log) {
+        this.transport = transport;
+        this.board = board;
+        this.log = log;
+    }
+    // ── Private primitives ────────────────────────────────────────────────────
+    /**
+     * Write bytes and discard the echo (TX loopback).
+     * After this returns the transport's receive buffer contains only device
+     * responses, not echo bytes.
+     */
+    async send(bytes) {
+        const data = new Uint8Array(bytes);
+        await this.transport.write(data);
+        // Discard echo bytes
+        await this.receiveExact(data.length);
+    }
+    /**
+     * Receive exactly `count` bytes from the transport.
+     * Accumulates chunks until the total reaches `count`, then resolves.
+     * Rejects with STK500TimeoutError if the deadline expires.
+     */
+    receiveExact(count) {
+        if (count === 0)
+            return Promise.resolve(new Uint8Array(0));
+        return new Promise((resolve, reject) => {
+            let settled = false;
+            const chunks = [];
+            let received = 0;
+            const timer = setTimeout(() => {
+                if (settled)
+                    return;
+                settled = true;
+                this.transport.off('data', onData);
+                reject(new STK500TimeoutError(this.board.timeout, `UPDI: waiting for ${count} bytes`));
+            }, this.board.timeout);
+            const onData = (chunk) => {
+                if (settled)
+                    return;
+                chunks.push(chunk.slice());
+                received += chunk.length;
+                if (received >= count) {
+                    settled = true;
+                    clearTimeout(timer);
+                    this.transport.off('data', onData);
+                    const buf = new Uint8Array(received);
+                    let off = 0;
+                    for (const c of chunks) {
+                        buf.set(c, off);
+                        off += c.length;
+                    }
+                    resolve(buf.subarray(0, count));
+                }
+            };
+            this.transport.on('data', onData);
+        });
+    }
+    // ── CS register access (LDCS / STCS) ─────────────────────────────────────
+    /**
+     * Read one byte from a UPDI Control/Status register.
+     * LDCS sequence: SYNC + (0x80 | addr) → echo 2 bytes → read 1 byte
+     */
+    async ldcs(addr) {
+        await this.send([UPDI_SYNC, INSTR_LDCS_BASE | (addr & 0x0F)]);
+        const resp = await this.receiveExact(1);
+        this.log('debug', `LDCS[0x${addr.toString(16)}] = 0x${resp[0].toString(16).padStart(2, '0')}`);
+        return resp[0];
+    }
+    /**
+     * Write one byte to a UPDI Control/Status register.
+     * STCS sequence: SYNC + (0xC0 | addr) + val → echo 3 bytes → read 1 ACK
+     */
+    async stcs(addr, val) {
+        await this.send([UPDI_SYNC, INSTR_STCS_BASE | (addr & 0x0F), val]);
+        const ack = await this.receiveExact(1);
+        if (ack[0] !== UPDI_ACK) {
+            throw new STK500ProtocolError(`UPDI STCS[0x${addr.toString(16)}]: expected ACK 0x40, ` +
+                `got 0x${ack[0].toString(16).padStart(2, '0')}`);
+        }
+        this.log('debug', `STCS[0x${addr.toString(16)}] = 0x${val.toString(16).padStart(2, '0')}`);
+    }
+    // ── Data-space access (LDS / STS — 16-bit address, 8-bit data) ───────────
+    /**
+     * Read one byte from a 16-bit data-space address.
+     * LDS sequence: SYNC + 0x04 + addrL + addrH → echo 4 bytes → read 1 byte
+     */
+    async lds(addr) {
+        await this.send([UPDI_SYNC, INSTR_LDS_16_8, addr & 0xFF, (addr >> 8) & 0xFF]);
+        const resp = await this.receiveExact(1);
+        this.log('debug', `LDS[0x${addr.toString(16).padStart(4, '0')}] = 0x${resp[0].toString(16).padStart(2, '0')}`);
+        return resp[0];
+    }
+    /**
+     * Write one byte to a 16-bit data-space address.
+     * STS sequence:
+     *   → SYNC + 0x44 + addrL + addrH → echo 4 bytes → read 1 ACK
+     *   → val                           → echo 1 byte  → read 1 ACK
+     */
+    async sts(addr, val) {
+        // Phase 1: send address
+        await this.send([UPDI_SYNC, INSTR_STS_16_8, addr & 0xFF, (addr >> 8) & 0xFF]);
+        const ack1 = await this.receiveExact(1);
+        if (ack1[0] !== UPDI_ACK) {
+            throw new STK500ProtocolError(`UPDI STS[0x${addr.toString(16)}] addr ACK: ` +
+                `got 0x${ack1[0].toString(16).padStart(2, '0')}`);
+        }
+        // Phase 2: send data (also echoed!)
+        await this.send([val]);
+        const ack2 = await this.receiveExact(1);
+        if (ack2[0] !== UPDI_ACK) {
+            throw new STK500ProtocolError(`UPDI STS[0x${addr.toString(16)}] data ACK: ` +
+                `got 0x${ack2[0].toString(16).padStart(2, '0')}`);
+        }
+        this.log('debug', `STS[0x${addr.toString(16).padStart(4, '0')}] = 0x${val.toString(16).padStart(2, '0')}`);
+    }
+    // ── Pointer register operations ───────────────────────────────────────────
+    /**
+     * Load a 16-bit address into the UPDI pointer register.
+     * ST(ptr, 16-bit) sequence: SYNC + 0x61 + addrL + addrH → echo 4 bytes → read 1 ACK
+     */
+    async setPtr(addr) {
+        await this.send([UPDI_SYNC, INSTR_ST_PTR_16, addr & 0xFF, (addr >> 8) & 0xFF]);
+        const ack = await this.receiveExact(1);
+        if (ack[0] !== UPDI_ACK) {
+            throw new STK500ProtocolError(`UPDI SET_PTR(0x${addr.toString(16)}): no ACK ` +
+                `(got 0x${ack[0].toString(16).padStart(2, '0')})`);
+        }
+        this.log('debug', `SET_PTR(0x${addr.toString(16).padStart(4, '0')})`);
+    }
+    /**
+     * Write a block of bytes to memory using ST ptr++ (with optional REPEAT).
+     *
+     * For count > 1, a REPEAT instruction is sent first so the device auto-advances
+     * the pointer.  Each byte requires: send byte → discard echo → read ACK.
+     */
+    async stPtrInc(data) {
+        if (data.length === 0)
+            return;
+        // Send REPEAT if more than one byte
+        if (data.length > 1) {
+            await this.send([UPDI_SYNC, INSTR_REPEAT_8, data.length - 1]);
+        }
+        // Send ST_PTR_INC instruction
+        await this.send([UPDI_SYNC, INSTR_ST_PTR_INC]);
+        // Send each data byte — each triggers echo + ACK
+        for (let i = 0; i < data.length; i++) {
+            await this.send([data[i]]);
+            const ack = await this.receiveExact(1);
+            if (ack[0] !== UPDI_ACK) {
+                throw new STK500ProtocolError(`UPDI ST_PTR_INC byte[${i}]: no ACK ` +
+                    `(got 0x${ack[0].toString(16).padStart(2, '0')})`);
+            }
+        }
+        this.log('debug', `ST_PTR_INC(${data.length} bytes)`);
+    }
+    /**
+     * Read a block of bytes using LD ptr++ (with optional REPEAT).
+     *
+     * For count > 1, a REPEAT is sent first.  The device streams back `count`
+     * data bytes directly — no echoes for reads.
+     */
+    async ldPtrInc(count) {
+        if (count === 0)
+            return new Uint8Array(0);
+        // Send REPEAT if more than one byte
+        if (count > 1) {
+            await this.send([UPDI_SYNC, INSTR_REPEAT_8, count - 1]);
+        }
+        // Send LD_PTR_INC instruction
+        await this.send([UPDI_SYNC, INSTR_LD_PTR_INC]);
+        // Device streams back `count` bytes (no echo for device→host direction)
+        const result = await this.receiveExact(count);
+        this.log('debug', `LD_PTR_INC(${count} bytes)`);
+        return result;
+    }
+    // ── KEY instruction ───────────────────────────────────────────────────────
+    /**
+     * Broadcast an 8-byte key to unlock NVM or chip-erase operations.
+     * KEY sequence: SYNC + 0xE0 + 8 key bytes → echo 10 bytes → no ACK
+     */
+    async sendKey(key) {
+        if (key.length !== 8) {
+            throw new STK500ProtocolError(`UPDI KEY: expected 8-byte key, got ${key.length}`);
+        }
+        await this.send([UPDI_SYNC, INSTR_KEY_64, ...key]);
+        // No ACK for KEY — device just latches the key state
+        this.log('debug', `KEY sent (${Array.from(key).map(b => b.toString(16).padStart(2, '0')).join(' ')})`);
+    }
+    // ── Convenience ───────────────────────────────────────────────────────────
+    /**
+     * Configure guard time to minimum (2 cycles) for faster communication.
+     * Called once after establishing the link.
+     */
+    async configureGuardTime() {
+        await this.stcs(UPDI_CS_CTRLA, UPDI_CTRLA_GT_2);
+    }
+    /**
+     * Read a contiguous memory region.
+     * Internally uses setPtr + ldPtrInc.
+     */
+    async readMemory(addr, size) {
+        await this.setPtr(addr);
+        return this.ldPtrInc(size);
+    }
+    /**
+     * Write a contiguous memory region.
+     * Internally uses setPtr + stPtrInc.
+     */
+    async writeMemory(addr, data) {
+        await this.setPtr(addr);
+        await this.stPtrInc(data);
+    }
+}
+//# sourceMappingURL=link.js.map

package/dist/protocol/updi/link.js.map

@@ -0,0 +1 @@
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package/dist/protocol/updi/programmer.d.ts

@@ -0,0 +1,89 @@
+import type { Board, STK500Options, BootloadProgressCallback } from '../../core/types.js';
+import type { ISTKTransport } from '../../transport/ITransport.js';
+/**
+ * Fuse register dump for tinyAVR 0/1/2 and megaAVR 0 series.
+ * Note: fuse3 does not exist on these devices. Indices match NVM fuse layout.
+ */
+export interface UPDIFuses {
+    fuse0: number;
+    fuse1: number;
+    fuse2: number;
+    /** fuse3 does not exist — index 3 is reserved and returns 0xFF */
+    fuse4: number;
+    fuse5: number;
+}
+export declare class UPDI {
+    private readonly transport;
+    private readonly board;
+    private readonly link;
+    private readonly log;
+    private readonly syncAttempts;
+    constructor(transport: ISTKTransport, board: Board, opts?: STK500Options);
+    /**
+     * Send a BREAK condition to reset the UPDI state machine.
+     * Requires transport.sendBreak() — throws if not available.
+     */
+    sendBreak(): Promise<void>;
+    /**
+     * Verify the UPDI link is active by reading STATUSA.
+     * Returns the STATUSA value on success, throws STK500SyncError on failure.
+     */
+    sync(attempts: number): Promise<void>;
+    /**
+     * Send the NVMProg key and wait until the device acknowledges NVMPROG mode.
+     */
+    enterProgMode(): Promise<void>;
+    /**
+     * Check if the device is locked (LOCKSTATUS bit in ASI_SYS_STATUS).
+     */
+    isLocked(): Promise<boolean>;
+    /**
+     * Erase the entire chip (flash + EEPROM + fuses reset to defaults).
+     * Must be in NVMPROG mode first — OR use the CHIPERASE key for locked devices.
+     */
+    chipErase(): Promise<void>;
+    /**
+     * Chip erase using the CHIPERASE key — works even on locked devices.
+     * Sends BREAK + key, then waits for erase to complete.
+     */
+    chipEraseKey(): Promise<void>;
+    /** Wait until NVM_STATUS.FBUSY clears (flash write/erase completed) */
+    waitNvmReady(): Promise<void>;
+    /**
+     * Read the 3-byte device ID from SIGROW (address 0x1100).
+     */
+    getSignature(): Promise<Uint8Array>;
+    verifySignature(): Promise<void>;
+    /**
+     * Write one page of flash.
+     * @param byteAddr  Absolute byte address in flash (e.g. 0x8000 for tinyAVR start)
+     * @param data      Page data (length = board.pageSize)
+     */
+    programPage(byteAddr: number, data: Uint8Array): Promise<void>;
+    /** Read `size` bytes from flash starting at `byteAddr` */
+    readFlash(byteAddr: number, size: number): Promise<Uint8Array>;
+    /**
+     * Write EEPROM bytes.
+     * @param offset  Byte offset within EEPROM (0-based)
+     * @param data    Data to write
+     */
+    writeEeprom(offset: number, data: Uint8Array): Promise<void>;
+    /** Read `size` EEPROM bytes starting at `offset` */
+    readEeprom(offset: number, size: number): Promise<Uint8Array>;
+    /**
+     * Read all fuse bytes (6 fuses for tinyAVR/megaAVR 0).
+     */
+    readFuses(): Promise<UPDIFuses>;
+    /**
+     * Write a single fuse byte.
+     * @param fuseNum  0–5 (fuse register index)
+     * @param val      New fuse value
+     */
+    writeFuse(fuseNum: number, val: number): Promise<void>;
+    /** Exit programming mode and reset the device to run user firmware. */
+    leaveProgMode(): Promise<void>;
+    upload(hexData: string | Uint8Array, progressCallback?: (pct: number) => void): Promise<void>;
+    verify(hexData: string | Uint8Array, progressCallback?: (pct: number) => void): Promise<void>;
+    bootload(hexData: string | Uint8Array, progressCallback?: BootloadProgressCallback): Promise<void>;
+}
+//# sourceMappingURL=programmer.d.ts.map

package/dist/protocol/updi/programmer.d.ts.map

@@ -0,0 +1 @@
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