webgpu-bench 0.1.1 → 0.3.0

package/dist/benchmarks/flopsMath.js

@@ -6,7 +6,6 @@ import { flopsF32RsqrtWgsl } from "../shaders/flopsF32Rsqrt.js";
 import { flopsF32PowWgsl } from "../shaders/flopsF32Pow.js";
 import { flopsF32SincosWgsl } from "../shaders/flopsF32Sincos.js";
 import { flopsF32LogWgsl } from "../shaders/flopsF32Log.js";
-import { OPS_METRIC } from "./common.js";
 /**
  * "Real" ALU ops beyond multiply-add: division and the transcendentals
  * (sqrt, pow, sin/cos, log) that 3D math leans on constantly (normalize,
@@ -21,8 +20,6 @@ import { OPS_METRIC } from "./common.js";
 export function prepareFlopsF32Div(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-div',
-        label: 'fp32 div FLOPS',
-        description: 'Eight independent scalar f32 divide-add chains per thread, unrolled 4x — the fp32 scalar FMA test with divide in place of multiply, so the gap between the two isolates the cost of division.',
         wgsl: flopsF32DivWgsl,
         flopsPerIteration: 64,
         defaultIterations: 256,
@@ -32,10 +29,7 @@ export function prepareFlopsF32Div(ctx, harness = {}) {
 export function prepareFlopsI32Div(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i32-div',
-        label: 'i32 div FLOPS',
-        description: 'Eight independent scalar i32 divide-add chains per thread, unrolled 4x — the int8-range scalar test with divide in place of multiply. Integer division is typically the slowest basic ALU op on a GPU.',
         wgsl: flopsI32DivWgsl,
-        metric: OPS_METRIC,
         flopsPerIteration: 64,
         defaultIterations: 256,
     }, harness);
@@ -44,8 +38,6 @@ export function prepareFlopsI32Div(ctx, harness = {}) {
 export function prepareFlopsF32Sqrt(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-sqrt',
-        label: 'fp32 sqrt FLOPS',
-        description: 'Eight independent scalar f32 sqrt-add chains per thread, unrolled 4x. sqrt is a common special-function-unit instruction; this measures its throughput in isolation.',
         wgsl: flopsF32SqrtWgsl,
         flopsPerIteration: 64,
         defaultIterations: 256,
@@ -55,8 +47,6 @@ export function prepareFlopsF32Sqrt(ctx, harness = {}) {
 export function prepareFlopsF32Rsqrt(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-rsqrt',
-        label: 'fp32 rsqrt FLOPS',
-        description: 'Eight independent scalar f32 inverseSqrt-add chains per thread, unrolled 4x. The op behind every normalize(); most GPUs have a dedicated fast-rsqrt path, so compare against flops-f32-sqrt to see the gap.',
         wgsl: flopsF32RsqrtWgsl,
         flopsPerIteration: 64,
         defaultIterations: 256,
@@ -66,8 +56,6 @@ export function prepareFlopsF32Rsqrt(ctx, harness = {}) {
 export function prepareFlopsF32Pow(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-pow',
-        label: 'fp32 pow FLOPS',
-        description: 'Eight independent scalar f32 pow-add chains per thread, unrolled 4x. pow(x, e) for a non-integer e is usually exp2(e * log2(x)) under the hood — several instructions — so expect this well below sqrt/div throughput.',
         wgsl: flopsF32PowWgsl,
         flopsPerIteration: 64,
         defaultIterations: 128,
@@ -77,8 +65,6 @@ export function prepareFlopsF32Pow(ctx, harness = {}) {
 export function prepareFlopsF32Sincos(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-sincos',
-        label: 'fp32 sin/cos FLOPS',
-        description: 'Eight independent scalar f32 cos(sin(x)) chains per thread, unrolled 4x. Naturally bounded to [-1, 1], so no stabilization term is needed. Measures combined sin+cos throughput.',
         wgsl: flopsF32SincosWgsl,
         flopsPerIteration: 64,
         defaultIterations: 128,
@@ -88,8 +74,6 @@ export function prepareFlopsF32Sincos(ctx, harness = {}) {
 export function prepareFlopsF32Log(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-log',
-        label: 'fp32 ln FLOPS',
-        description: 'Eight independent scalar f32 ln-add chains per thread, unrolled 4x. log(x) is usually log2(x) * ln(2) under the hood, so expect throughput close to a raw log2 special-function call.',
         wgsl: flopsF32LogWgsl,
         flopsPerIteration: 64,
         defaultIterations: 256,

package/dist/benchmarks/flopsMath.js.map

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package/dist/benchmarks/streamBandwidth.d.ts

@@ -3,15 +3,16 @@ import type { GeneratedData } from '../data/generate.ts';
 import { type HarnessConfig, type PreparedBenchmark } from './common.ts';
 /**
  * Read-bandwidth test: streams the (already-allocated, matrix-sized) input
- * buffer through each thread with nothing but addition, writing back a
- * single scalar per thread. Reads vastly outweigh writes, so `gbps` here is
- * a read-bandwidth-bound number close to the device's peak.
+ * buffer through a coalesced grid-stride loop with nothing but addition,
+ * writing back a single scalar per thread. Reads vastly outweigh writes, so
+ * `gbps` here is a read-bandwidth-bound number close to the device's peak.
  */
 export declare function prepareReadBandwidth(ctx: GpuContext, data: GeneratedData, harness?: HarnessConfig): Promise<PreparedBenchmark>;
 /**
  * Write-bandwidth test: streams computed values out into a matrix-sized
- * output buffer. No buffer reads at all, so `gbps` here is a
- * write-bandwidth-bound number close to the device's peak.
+ * output buffer through the same coalesced grid-stride loop. No buffer reads
+ * at all, so `gbps` here is a write-bandwidth-bound number close to the
+ * device's peak.
  */
 export declare function prepareWriteBandwidth(ctx: GpuContext, data: GeneratedData, harness?: HarnessConfig): Promise<PreparedBenchmark>;
 //# sourceMappingURL=streamBandwidth.d.ts.map

package/dist/benchmarks/streamBandwidth.d.ts.map

@@ -1 +1 @@
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package/dist/benchmarks/streamBandwidth.js

@@ -1,20 +1,36 @@
 import { createUniformBuffer, createStorageBuffer, createEmptyStorageBuffer } from "../gpu/buffers.js";
-import { createPipeline, prepareKernelBenchmark, BYTES_METRIC, } from "./common.js";
+import { createPipeline, prepareKernelBenchmark } from "./common.js";
 import { streamReadWgsl } from "../shaders/streamRead.js";
 import { streamWriteWgsl } from "../shaders/streamWrite.js";
+const WORKGROUP_SIZE = 256;
+/**
+ * vec4 loads/stores per thread. Threads are sized from the buffer, not the
+ * GPU: WebGPU limits say nothing about core count or memory bus, so instead
+ * every device gets a shape that's good everywhere — coalesced grid-stride
+ * access, a few independent accesses per thread to hide latency, and enough
+ * threads (256K for the default 64 MB buffer) to fill a wide discrete GPU,
+ * while a small mobile GPU just drains the same workgroups over more waves.
+ * On an M3 this is within a few percent of the best thread count in a sweep.
+ */
+const VEC4S_PER_THREAD = 16;
+function bandwidthShape(data) {
+    const count = data.matrix.length / 4;
+    const workgroups = Math.max(1, Math.ceil(count / VEC4S_PER_THREAD / WORKGROUP_SIZE));
+    return { count, threads: workgroups * WORKGROUP_SIZE, workgroups };
+}
 /**
  * Read-bandwidth test: streams the (already-allocated, matrix-sized) input
- * buffer through each thread with nothing but addition, writing back a
- * single scalar per thread. Reads vastly outweigh writes, so `gbps` here is
- * a read-bandwidth-bound number close to the device's peak.
+ * buffer through a coalesced grid-stride loop with nothing but addition,
+ * writing back a single scalar per thread. Reads vastly outweigh writes, so
+ * `gbps` here is a read-bandwidth-bound number close to the device's peak.
  */
 export async function prepareReadBandwidth(ctx, data, harness = {}) {
     const { device } = ctx;
-    const cols4 = data.cols / 4;
+    const { count, threads, workgroups } = bandwidthShape(data);
     const pipeline = await createPipeline(device, 'stream-read', streamReadWgsl);
-    const paramsBuf = createUniformBuffer(device, new Uint32Array([data.rows, cols4]), 'params');
+    const paramsBuf = createUniformBuffer(device, new Uint32Array([count, threads]), 'params');
     const dataBuf = createStorageBuffer(device, data.matrix, 'data');
-    const outBuf = createEmptyStorageBuffer(device, data.rows * 4, 'out');
+    const outBuf = createEmptyStorageBuffer(device, threads * 4, 'out');
     const bindGroup = device.createBindGroup({
         layout: pipeline.getBindGroupLayout(0),
         entries: [
@@ -25,16 +41,12 @@ export async function prepareReadBandwidth(ctx, data, harness = {}) {
     });
     return prepareKernelBenchmark({
         id: 'read-bandwidth',
-        label: 'Read bandwidth',
-        description: 'One thread per row; streams a large buffer in via vec4<f32> loads and addition only, writes one scalar. Read-bandwidth-bound.',
-        source: streamReadWgsl,
         category: 'bandwidth',
         ctx,
         rows: data.rows,
         cols: data.cols,
-        metric: BYTES_METRIC,
         amountPerOp: data.matrix.byteLength,
-        workgroupsPerIteration: [Math.ceil(data.rows / 64), 1, 1],
+        workgroupsPerIteration: [workgroups, 1, 1],
         pipeline,
         bindGroup,
         ...harness,
@@ -42,14 +54,15 @@ export async function prepareReadBandwidth(ctx, data, harness = {}) {
 }
 /**
  * Write-bandwidth test: streams computed values out into a matrix-sized
- * output buffer. No buffer reads at all, so `gbps` here is a
- * write-bandwidth-bound number close to the device's peak.
+ * output buffer through the same coalesced grid-stride loop. No buffer reads
+ * at all, so `gbps` here is a write-bandwidth-bound number close to the
+ * device's peak.
  */
 export async function prepareWriteBandwidth(ctx, data, harness = {}) {
     const { device } = ctx;
-    const cols4 = data.cols / 4;
+    const { count, threads, workgroups } = bandwidthShape(data);
     const pipeline = await createPipeline(device, 'stream-write', streamWriteWgsl);
-    const paramsBuf = createUniformBuffer(device, new Uint32Array([data.rows, cols4]), 'params');
+    const paramsBuf = createUniformBuffer(device, new Uint32Array([count, threads]), 'params');
     const outBuf = createEmptyStorageBuffer(device, data.matrix.byteLength, 'out');
     const bindGroup = device.createBindGroup({
         layout: pipeline.getBindGroupLayout(0),
@@ -60,16 +73,12 @@ export async function prepareWriteBandwidth(ctx, data, harness = {}) {
     });
     return prepareKernelBenchmark({
         id: 'write-bandwidth',
-        label: 'Write bandwidth',
-        description: 'One thread per row; stores computed vec4<f32> values into a large buffer with no buffer reads. Write-bandwidth-bound.',
-        source: streamWriteWgsl,
         category: 'bandwidth',
         ctx,
         rows: data.rows,
         cols: data.cols,
-        metric: BYTES_METRIC,
         amountPerOp: data.matrix.byteLength,
-        workgroupsPerIteration: [Math.ceil(data.rows / 64), 1, 1],
+        workgroupsPerIteration: [workgroups, 1, 1],
         pipeline,
         bindGroup,
         ...harness,

package/dist/benchmarks/streamBandwidth.js.map

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package/dist/catalog.d.ts

@@ -1,22 +1,33 @@
 import type { BenchmarkCategory, MetricDef } from './types.ts';
-/** Identity of one benchmark, known without touching the GPU. */
+/**
+ * Identity of one benchmark, known without touching the GPU: label,
+ * description and WGSL source for display, plus category/metric for
+ * formatting a result once one arrives. The sole source of truth for all
+ * of this — `runSuite`'s `BenchmarkResult` rows carry only what's known
+ * from actually running (status, timings, `metricValue`), keyed by `id`
+ * back onto this catalog rather than repeating it.
+ */
 export interface BenchmarkInfo {
     id: string;
     label: string;
+    description: string;
+    /** WGSL source of the kernel, for display alongside a result. */
+    source: string;
     category: BenchmarkCategory;
     metric: MetricDef;
 }
 /**
  * Every benchmark `runSuite` can yield a row for, in the same order it
  * schedules them — so a UI can render the full results table (id, label,
- * category, metric unit) before a device is even acquired, then fill in
- * throughput as `runSuite`'s rows arrive and merge onto these ids.
+ * category, metric unit, description, source) before a device is even
+ * acquired, then fill in throughput as `runSuite`'s rows arrive and merge
+ * onto these ids.
  *
  * Kept as a hand-written list, not derived from `suite.ts`'s benchmark
- * table, because each kernel's id/label/metric there is itself a literal
- * embedded next to its WGSL and `prepare*` call (real GPU setup) — nothing
- * to derive from without running it. `suite.browser.test.ts` asserts this
- * list's ids match `runSuite`'s one-to-one, so the two can't drift silently.
+ * table, because `suite.ts` only wires up *how* to run each kernel (its
+ * `prepare*` call) — it doesn't carry a duplicate copy of this metadata to
+ * derive from. `suite.browser.test.ts` asserts this list's ids match
+ * `runSuite`'s one-to-one, so the two can't drift silently.
  */
 export declare const BENCHMARK_CATALOG: readonly BenchmarkInfo[];
 //# sourceMappingURL=catalog.d.ts.map

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package/dist/catalog.js

@@ -1,48 +1,251 @@
 import { BYTES_METRIC, FLOPS_METRIC, OPS_METRIC } from "./benchmarks/common.js";
+import { streamReadWgsl } from "./shaders/streamRead.js";
+import { streamWriteWgsl } from "./shaders/streamWrite.js";
+import { flopsF32ScalarWgsl } from "./shaders/flopsF32Scalar.js";
+import { flopsF32Vec4Wgsl } from "./shaders/flopsF32Vec4.js";
+import { flopsF32Mat4Wgsl } from "./shaders/flopsF32Mat4.js";
+import { flopsF32MatvecWgsl } from "./shaders/flopsF32Matvec.js";
+import { flopsF16ScalarWgsl } from "./shaders/flopsF16Scalar.js";
+import { flopsF16Vec4Wgsl } from "./shaders/flopsF16Vec4.js";
+import { flopsF16Mat4Wgsl } from "./shaders/flopsF16Mat4.js";
+import { flopsF16MatvecWgsl } from "./shaders/flopsF16Matvec.js";
+import { flopsI8ScalarWgsl } from "./shaders/flopsI8Scalar.js";
+import { flopsI8Vec4Wgsl } from "./shaders/flopsI8Vec4.js";
+import { flopsI8Mat4Wgsl } from "./shaders/flopsI8Mat4.js";
+import { flopsI8MatvecWgsl } from "./shaders/flopsI8Matvec.js";
+import { flopsI8MatvecDp4aWgsl } from "./shaders/flopsI8MatvecDp4a.js";
+import { flopsI8Dp4aWgsl } from "./shaders/flopsI8Dp4a.js";
+import { flopsF32DivWgsl } from "./shaders/flopsF32Div.js";
+import { flopsI32DivWgsl } from "./shaders/flopsI32Div.js";
+import { flopsF32SqrtWgsl } from "./shaders/flopsF32Sqrt.js";
+import { flopsF32RsqrtWgsl } from "./shaders/flopsF32Rsqrt.js";
+import { flopsF32PowWgsl } from "./shaders/flopsF32Pow.js";
+import { flopsF32SincosWgsl } from "./shaders/flopsF32Sincos.js";
+import { flopsF32LogWgsl } from "./shaders/flopsF32Log.js";
+import { flopsU32PackUnpackWgsl } from "./shaders/flopsU32PackUnpack.js";
+import { flopsI32F32ConvertWgsl } from "./shaders/flopsI32F32Convert.js";
+import { flopsF32F16ConvertWgsl } from "./shaders/flopsF32F16Convert.js";
 /**
  * Every benchmark `runSuite` can yield a row for, in the same order it
  * schedules them — so a UI can render the full results table (id, label,
- * category, metric unit) before a device is even acquired, then fill in
- * throughput as `runSuite`'s rows arrive and merge onto these ids.
+ * category, metric unit, description, source) before a device is even
+ * acquired, then fill in throughput as `runSuite`'s rows arrive and merge
+ * onto these ids.
  *
  * Kept as a hand-written list, not derived from `suite.ts`'s benchmark
- * table, because each kernel's id/label/metric there is itself a literal
- * embedded next to its WGSL and `prepare*` call (real GPU setup) — nothing
- * to derive from without running it. `suite.browser.test.ts` asserts this
- * list's ids match `runSuite`'s one-to-one, so the two can't drift silently.
+ * table, because `suite.ts` only wires up *how* to run each kernel (its
+ * `prepare*` call) — it doesn't carry a duplicate copy of this metadata to
+ * derive from. `suite.browser.test.ts` asserts this list's ids match
+ * `runSuite`'s one-to-one, so the two can't drift silently.
  */
 export const BENCHMARK_CATALOG = [
-    { id: 'read-bandwidth', label: 'Read bandwidth', category: 'bandwidth', metric: BYTES_METRIC },
-    { id: 'write-bandwidth', label: 'Write bandwidth', category: 'bandwidth', metric: BYTES_METRIC },
-    { id: 'flops-f32-scalar', label: 'fp32 scalar FMA FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f32-vec4', label: 'fp32 vec4 FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f32-mat4', label: 'fp32 mat4 FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f32-matvec', label: 'fp32 matvec FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f16-scalar', label: 'fp16 scalar FMA FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f16-vec4', label: 'fp16 vec4 FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f16-mat4', label: 'fp16 mat4 FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f16-matvec', label: 'fp16 matvec FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-i8-scalar', label: 'int8-range scalar FMA FLOPS', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-i8-vec4', label: 'int8-range vec4 FLOPS', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-i8-mat4', label: 'int8-range mat4 FLOPS', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-i8-matvec', label: 'int8 matvec FLOPS (i32 dot)', category: 'compute', metric: OPS_METRIC },
+    {
+        id: 'read-bandwidth',
+        label: 'Read bandwidth',
+        description: 'Coalesced grid-stride loop: adjacent threads load adjacent vec4<f32>s from a large buffer, folded with addition only, one scalar written per thread. Read-bandwidth-bound.',
+        source: streamReadWgsl,
+        category: 'bandwidth',
+        metric: BYTES_METRIC,
+    },
+    {
+        id: 'write-bandwidth',
+        label: 'Write bandwidth',
+        description: 'Coalesced grid-stride loop: adjacent threads store adjacent computed vec4<f32>s into a large buffer with no buffer reads. Write-bandwidth-bound.',
+        source: streamWriteWgsl,
+        category: 'bandwidth',
+        metric: BYTES_METRIC,
+    },
+    {
+        id: 'flops-f32-scalar',
+        label: 'fp32 scalar FMA FLOPS',
+        description: 'Eight independent scalar f32 fused multiply-add chains per thread, unrolled 4x, so the ALU always has work in flight and the number reflects throughput rather than FMA latency. ~no memory traffic.',
+        source: flopsF32ScalarWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f32-vec4',
+        label: 'fp32 vec4 FLOPS',
+        description: 'Eight independent FMA chains held in vec4<f32> registers, unrolled 4x: the fp32 scalar test with every chain 4 lanes wide. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) each step is 4 scalar FMAs, so this should match the scalar number; a gap means vector ops cost extra.',
+        source: flopsF32Vec4Wgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f32-mat4',
+        label: 'fp32 mat4 FLOPS',
+        description: 'x = m * x + c chained in a register with a mat4x4<f32> (a bounded contraction so it stays numerically stable): 16 FMAs per step with plenty of independent work, exercising the full mat4 x vec4 multiply.',
+        source: flopsF32Mat4Wgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f32-matvec',
+        label: 'fp32 matvec FLOPS',
+        description: 'A 4-row x 8-column f32 weight tile held in registers, applied to an 8-wide input every iteration via dot() (outputs feed back as the next inputs). The dot-product-accumulate shape of a GEMV inner loop with zero buffer traffic: pure ALU.',
+        source: flopsF32MatvecWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f16-scalar',
+        label: 'fp16 scalar FMA FLOPS',
+        description: 'Same eight independent, 4x-unrolled FMA chains as the fp32 scalar test, but every operand and accumulator is f16, so the chains run entirely in half precision.',
+        source: flopsF16ScalarWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f16-vec4',
+        label: 'fp16 vec4 FLOPS',
+        description: 'Same eight 4x-unrolled vec4 FMA chains as the fp32 vec4 test, but in vec4<f16>. Only GPUs with packed-half ALUs run this faster than fp32.',
+        source: flopsF16Vec4Wgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f16-mat4',
+        label: 'fp16 mat4 FLOPS',
+        description: 'Same bounded x = m * x + c recurrence as the fp32 mat4 test, but m, c, and x are all f16, so the mat4x4 x vec4 multiply runs entirely in half precision.',
+        source: flopsF16Mat4Wgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f16-matvec',
+        label: 'fp16 matvec FLOPS',
+        description: 'Same register-resident 4x8 matvec tile as the fp32 matvec test, but weights, inputs, and dot() accumulation are all f16. Pure ALU: the fp16 win here comes only from the ALU, not from halved memory traffic.',
+        source: flopsF16MatvecWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-i8-scalar',
+        label: 'int8-range scalar FMA FLOPS',
+        description: 'Same eight independent, 4x-unrolled multiply-add chains as the fp32 scalar test, but on i32 (WGSL has no first-class i8 type). Measures integer multiply-add throughput; overflow wraps.',
+        source: flopsI8ScalarWgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-i8-vec4',
+        label: 'int8-range vec4 FLOPS',
+        description: 'Same eight 4x-unrolled vec4 multiply-add chains as the fp32 vec4 test, but in vec4<i32>.',
+        source: flopsI8Vec4Wgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-i8-mat4',
+        label: 'int8-range mat4 FLOPS',
+        description: 'x = m * x + c chained in a register, where m is a 4x4 integer matrix emulated as four vec4<i32> rows combined with dot() (WGSL has no mat4x4<i32>): the same 4 dot products a real int4x4 multiply compiles to.',
+        source: flopsI8Mat4Wgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-i8-matvec',
+        label: 'int8 matvec FLOPS (i32 dot)',
+        description: 'Same register-resident 4x8 matvec tile as the fp32 matvec test, with int8-range weights and inputs held unpacked as vec4<i32> and accumulated with integer dot(). The no-extension int8 path: what dot4I8Packed is competing against.',
+        source: flopsI8MatvecWgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
     {
         id: 'flops-i8-matvec-dp4a',
         label: 'int8 matvec FLOPS (dot4I8Packed)',
+        description: "Same 4x8 matvec tile, but weights and inputs stay packed four int8 lanes per u32 and each 4-wide dot product is one dot4I8Packed call from the packed_4x8_integer_dot_product extension. On GPUs without a native dp4a instruction this runs the extension's polyfill.",
+        source: flopsI8MatvecDp4aWgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-i8-dp4a',
+        label: 'int8 dot4I8Packed FLOPS',
+        description: "Eight independent accumulators per thread, each summing dot4I8Packed(a, b) — the packed_4x8_integer_dot_product extension's 4-wide int8 dot-product instruction — in a tight loop to measure its peak throughput in isolation.",
+        source: flopsI8Dp4aWgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-f32-div',
+        label: 'fp32 div FLOPS',
+        description: 'Eight independent scalar f32 chains of x = a / x + b per thread, unrolled 4x — the fp32 scalar FMA test with divide in place of multiply, so the gap between the two isolates the cost of division. The loop-carried value is the divisor, so the compiler cannot hoist a reciprocal and turn it back into an FMA.',
+        source: flopsF32DivWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-i32-div',
+        label: 'i32 div FLOPS',
+        description: 'Eight independent scalar i32 chains of x = a / x + b per thread, unrolled 4x — the int8-range scalar test with divide in place of multiply, divisor loop-carried. Integer division is typically the slowest basic ALU op on a GPU.',
+        source: flopsI32DivWgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-f32-sqrt',
+        label: 'fp32 sqrt FLOPS',
+        description: 'Eight independent scalar f32 sqrt-add chains per thread, unrolled 4x. sqrt is a common special-function-unit instruction; this measures its throughput in isolation.',
+        source: flopsF32SqrtWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f32-rsqrt',
+        label: 'fp32 rsqrt FLOPS',
+        description: 'Eight independent scalar f32 inverseSqrt-add chains per thread, unrolled 4x. The op behind every normalize(); most GPUs have a dedicated fast-rsqrt path, so compare against flops-f32-sqrt to see the gap.',
+        source: flopsF32RsqrtWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f32-pow',
+        label: 'fp32 pow FLOPS',
+        description: 'Eight independent scalar f32 pow-add chains per thread, unrolled 4x. pow(x, e) for a non-integer e is usually exp2(e * log2(x)) under the hood — several instructions — so expect this well below sqrt/div throughput.',
+        source: flopsF32PowWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f32-sincos',
+        label: 'fp32 sin/cos FLOPS',
+        description: 'Eight independent scalar f32 cos(sin(x)) chains per thread, unrolled 4x. Naturally bounded to [-1, 1], so no stabilization term is needed. Measures combined sin+cos throughput.',
+        source: flopsF32SincosWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-f32-log',
+        label: 'fp32 ln FLOPS',
+        description: 'Eight independent scalar f32 ln-add chains per thread, unrolled 4x. log(x) is usually log2(x) * ln(2) under the hood, so expect throughput close to a raw log2 special-function call.',
+        source: flopsF32LogWgsl,
+        category: 'compute',
+        metric: FLOPS_METRIC,
+    },
+    {
+        id: 'flops-u32-packunpack',
+        label: 'u32 byte pack/unpack',
+        description: 'Eight independent u32 lanes, unrolled 4x, each step unpacking 4 bytes via shift+mask, incrementing them, and repacking — no pack4x8 (or unpack4x8) builtin, just the bit-twiddling those compile to. Counted as 2 ops per lane step (one unpack + one pack of a whole u32), since the compiler folds the individual shifts and masks.',
+        source: flopsU32PackUnpackWgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-i32-f32-convert',
+        label: 'i32<->f32 convert',
+        description: 'Eight independent chains per thread, unrolled 4x: xi -> f32(xi)*a+b -> back to i32 each step. Counted as 2 ops per lane step (one convert each way; the FMA is not counted).',
+        source: flopsI32F32ConvertWgsl,
+        category: 'compute',
+        metric: OPS_METRIC,
+    },
+    {
+        id: 'flops-f32-f16-convert',
+        label: 'f32<->f16 convert',
+        description: 'Eight independent vec2<f32> chains per thread, unrolled 4x: pack2x16float then unpack2x16float (round-trips through fp16 bits) plus a vec2 FMA to keep the chain moving. Counted as 2 ops per lane per step (one convert each way; the FMA is not counted). Unlike flops-f16-*, this needs no shader-f16 device feature — it measures the conversion, not f16 compute.',
+        source: flopsF32F16ConvertWgsl,
         category: 'compute',
         metric: OPS_METRIC,
     },
-    { id: 'flops-i8-dp4a', label: 'int8 dot4I8Packed FLOPS', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-f32-div', label: 'fp32 div FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-i32-div', label: 'i32 div FLOPS', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-f32-sqrt', label: 'fp32 sqrt FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f32-rsqrt', label: 'fp32 rsqrt FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f32-pow', label: 'fp32 pow FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f32-sincos', label: 'fp32 sin/cos FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-f32-log', label: 'fp32 ln FLOPS', category: 'compute', metric: FLOPS_METRIC },
-    { id: 'flops-u32-packunpack', label: 'u32 byte pack/unpack ops', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-i32-f32-convert', label: 'i32<->f32 convert FLOPS', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-f32-f16-convert', label: 'f32<->f16 convert FLOPS', category: 'compute', metric: OPS_METRIC },
-    { id: 'flops-i32-f16-convert', label: 'i32<->f16 convert FLOPS', category: 'compute', metric: OPS_METRIC },
 ];
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package/dist/catalog.js.map

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package/dist/index.d.ts

@@ -1,7 +1,7 @@
 export { runSuite } from './suite.ts';
 export { BENCHMARK_CATALOG } from './catalog.ts';
 export type { BenchmarkInfo } from './catalog.ts';
-export type { BenchmarkResult, SuiteOptions, SuiteProgressEvent, DeviceInfo, Stats, BenchmarkCategory, BenchmarkStatus, TimingMethod, SamplingStopReason, } from './types.ts';
+export type { BenchmarkResult, SuiteOptions, SuiteProgressEvent, DeviceInfo, Stats, BenchmarkCategory, BenchmarkStatus, TimingMethod, SamplingStopReason, MetricDef, } from './types.ts';
 export { computeStats, isBestStable, isThrottled, tQuantile975 } from './stats.ts';
 export type { BestStableOptions } from './stats.ts';
 export { DEFAULT_SAMPLING, runSampling, recordSample, roundIsThrottled, resolveSamplingConfig } from './sampling.ts';

package/dist/index.d.ts.map

@@ -1 +1 @@
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+{"version":3,"file":"index.d.ts","sourceRoot":"","sources":["../src/index.ts"],"names":[],"mappings":"AAAA,OAAO,EAAE,QAAQ,EAAE,MAAM,YAAY,CAAC;AACtC,OAAO,EAAE,iBAAiB,EAAE,MAAM,cAAc,CAAC;AACjD,YAAY,EAAE,aAAa,EAAE,MAAM,cAAc,CAAC;AAClD,YAAY,EACV,eAAe,EACf,YAAY,EACZ,kBAAkB,EAClB,UAAU,EACV,KAAK,EACL,iBAAiB,EACjB,eAAe,EACf,YAAY,EACZ,kBAAkB,EAClB,SAAS,GACV,MAAM,YAAY,CAAC;AACpB,OAAO,EAAE,YAAY,EAAE,YAAY,EAAE,WAAW,EAAE,YAAY,EAAE,MAAM,YAAY,CAAC;AACnF,YAAY,EAAE,iBAAiB,EAAE,MAAM,YAAY,CAAC;AACpD,OAAO,EAAE,gBAAgB,EAAE,WAAW,EAAE,YAAY,EAAE,gBAAgB,EAAE,qBAAqB,EAAE,MAAM,eAAe,CAAC;AACrH,YAAY,EAAE,cAAc,EAAE,UAAU,EAAE,WAAW,EAAE,mBAAmB,EAAE,kBAAkB,EAAE,MAAM,eAAe,CAAC;AACtH,OAAO,EAAE,mBAAmB,EAAE,aAAa,EAAE,MAAM,0BAA0B,CAAC;AAC9E,YAAY,EAAE,iBAAiB,EAAE,aAAa,EAAE,QAAQ,EAAE,MAAM,0BAA0B,CAAC;AAC3F,OAAO,EAAE,kBAAkB,EAAE,gBAAgB,EAAE,UAAU,EAAE,MAAM,oBAAoB,CAAC;AACtF,OAAO,EAAE,iBAAiB,EAAE,MAAM,kBAAkB,CAAC;AACrD,YAAY,EAAE,UAAU,EAAE,MAAM,kBAAkB,CAAC"}

package/dist/index.js.map

@@ -1 +1 @@
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