webgpu-bench 0.1.1 → 0.3.0

package/README.md

@@ -16,17 +16,17 @@ bandwidth/FLOPS specs.
 
 | Benchmark                                          | What it tests                                                                                                                                                                                                                                           |
 | -------------------------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
-| `read-bandwidth`                                   | Streams a large buffer in via `vec4<f32>` loads folded with addition only (no multiply, one scalar written per thread) — a read-bandwidth-bound probe of peak storage-buffer read throughput                                                            |
-| `write-bandwidth`                                  | Streams computed `vec4<f32>` values out into a large buffer with no buffer reads at all — a write-bandwidth-bound probe of peak storage-buffer write throughput                                                                                         |
+| `read-bandwidth`                                   | Coalesced grid-stride loop (adjacent threads load adjacent `vec4<f32>`s, ~256K threads) folded with addition only, one scalar written per thread — a read-bandwidth-bound probe of peak storage-buffer read throughput                                  |
+| `write-bandwidth`                                  | The same coalesced grid-stride loop storing computed `vec4<f32>` values with no buffer reads at all — a write-bandwidth-bound probe of peak storage-buffer write throughput                                                                            |
 | `flops-f32-scalar`                                 | Raw fp32 FLOPS: eight _independent_ scalar FMA chains per thread, unrolled 4x, so the ALU always has work in flight (a single dependent chain would measure FMA latency + loop overhead, not throughput)                                                |
-| `flops-f32-vec4`                                   | One FMA chain held in a `vec4<f32>` register. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) that is 4 independent scalar FMAs per step — it measures 4-wide instruction-level parallelism, not a wider ALU                                                   |
+| `flops-f32-vec4`                                   | The same eight 4x-unrolled chains held in `vec4<f32>` registers. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) each step is 4 scalar FMAs, so this should match the scalar number; a gap means vector ops cost extra                                        |
 | `flops-f32-mat4`                                   | `x = m * x + c` chained with a `mat4x4<f32>` (a bounded contraction, so it stays numerically stable over any iteration count)                                                                                                                           |
 | `flops-f32-matvec`                                 | Register-resident matvec tile: a 4x8 f32 weight tile held in registers, applied to an 8-wide input every iteration via `dot()`, outputs feeding back as the next inputs. The dot-product-accumulate shape of a GEMV inner loop with zero buffer traffic |
 | `flops-f16-scalar` / `-vec4` / `-mat4` / `-matvec` | The same four shapes, entirely in `f16` (skipped if the device lacks `shader-f16`)                                                                                                                                                                      |
 | `flops-i8-scalar` / `-vec4` / `-mat4`              | The scalar / vec4 shapes on `i32` (WGSL has no first-class `i8` type), and a 4x4 integer matvec emulated as four `vec4<i32>` rows combined with `dot()` (WGSL has no `mat4x4<i32>`)                                                                     |
 | `flops-i8-matvec`                                  | The register-resident matvec tile with int8-range weights/inputs held unpacked as `vec4<i32>` and integer `dot()` accumulation — the no-extension int8 path                                                                                             |
 | `flops-i8-matvec-dp4a`                             | The same tile with weights/inputs kept packed four int8 lanes per `u32`, each 4-wide dot product a single `dot4I8Packed` (skipped without `packed_4x8_integer_dot_product`)                                                                             |
-| `flops-i8-dp4a`                                    | `dot4I8Packed` accumulated in a tight loop to isolate the instruction's peak throughput (skipped without the feature)                                                                                                                                   |
+| `flops-i8-dp4a`                                    | `dot4I8Packed` accumulated into eight independent accumulators in a tight loop to isolate the instruction's peak throughput (skipped without the feature)                                                                                              |
 
 The two bandwidth benchmarks stream the same deterministically-generated buffer (default 4096 &times;
 4096 f32, padded to a multiple of 4). The raw-FLOPS kernels' loop trip count and per-lane operands are

package/dist/benchmarks/common.d.ts

@@ -24,19 +24,17 @@ export declare function createPipeline(device: GPUDevice, label: string, code: s
 export declare function metricPerSecond(amountPerOp: number, perOpMs: number): number;
 /** Per-measurement knobs (`targetMs`, `targetDispatchMs`, `warmups`) shared by every benchmark. */
 export type HarnessConfig = MeasurementConfig;
-/** Everything about a benchmark that's known before it's measured. */
+/**
+ * Everything about a benchmark that's known before it's measured. Identity/display
+ * fields (label, description, source, metric) live in `BENCHMARK_CATALOG` instead —
+ * this is just what a live run needs to size and account for the work.
+ */
 export interface BenchmarkMeta {
     id: string;
-    label: string;
-    description: string;
-    /** WGSL source of the kernel, for display alongside the result. */
-    source: string;
     category: BenchmarkCategory;
     rows: number;
     cols: number;
-    /** What this benchmark's throughput number counts. */
-    metric: MetricDef;
-    /** Amount of `metric.unit` moved/computed per op. */
+    /** Amount of `metric.unit` (per the catalog's `MetricDef` for this id) moved/computed per op. */
     amountPerOp: number;
 }
 /**

package/dist/benchmarks/common.d.ts.map

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package/dist/benchmarks/common.js

@@ -41,13 +41,9 @@ export function prepareKernelBenchmark(opts) {
         kind: 'kernel',
         meta: {
             id: opts.id,
-            label: opts.label,
-            description: opts.description,
-            source: opts.source,
             category: opts.category,
             rows: opts.rows,
             cols: opts.cols,
-            metric: opts.metric,
             amountPerOp: opts.amountPerOp,
         },
         metaAtWork: opts.metaAtWork,
@@ -87,9 +83,6 @@ export function errorResult(meta, error) {
 export function rowFromMeta(meta) {
     return {
         id: meta.id,
-        label: meta.label,
-        description: meta.description,
-        source: meta.source,
         category: meta.category,
         status: 'running',
         rows: meta.rows,
@@ -97,7 +90,6 @@ export function rowFromMeta(meta) {
         innerIterations: 0,
         timesMs: [],
         throttledMs: [],
-        metric: meta.metric,
         timingMethod: 'cpu-wallclock',
     };
 }

package/dist/benchmarks/common.js.map

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package/dist/benchmarks/flopsCommon.d.ts

@@ -1,17 +1,8 @@
 import type { GpuContext } from '../gpu/context.ts';
 import { type HarnessConfig, type PreparedBenchmark } from './common.ts';
-import type { MetricDef } from '../types.ts';
 export interface FlopsKernelSpec {
     id: string;
-    label: string;
-    description: string;
     wgsl: string;
-    /**
-     * What this kernel's per-iteration count represents. Defaults to
-     * `FLOPS_METRIC`; kernels doing integer or bit-twiddling work (not IEEE
-     * floating-point ops) should pass `OPS_METRIC` instead.
-     */
-    metric?: MetricDef;
     /** Amount of `metric.unit` (same MAC-as-2 convention throughout) performed per loop iteration by a single thread. */
     flopsPerIteration: number;
     /**

package/dist/benchmarks/flopsCommon.d.ts.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsCommon.js

@@ -1,5 +1,5 @@
 import { createUniformBuffer, createEmptyStorageBuffer } from "../gpu/buffers.js";
-import { createPipeline, prepareKernelBenchmark, skippedResult, FLOPS_METRIC, } from "./common.js";
+import { createPipeline, prepareKernelBenchmark, skippedResult, } from "./common.js";
 const DEFAULT_THREADS = 1024 * 1024;
 const DEFAULT_ITERATIONS = 1024;
 const DEFAULT_MIN_ITERATIONS = 16;
@@ -20,13 +20,9 @@ export async function prepareFlopsBenchmark(ctx, spec, harness = {}) {
     const maxIterations = harness.iterations ?? spec.defaultIterations ?? DEFAULT_ITERATIONS;
     const metaAtWork = (iterations) => ({
         id: spec.id,
-        label: spec.label,
-        description: spec.description,
-        source: spec.wgsl,
         category: 'compute',
         rows: threads,
         cols: iterations,
-        metric: spec.metric ?? FLOPS_METRIC,
         amountPerOp: threads * iterations * spec.flopsPerIteration,
     });
     const meta = metaAtWork(maxIterations);

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package/dist/benchmarks/flopsConvert.d.ts

@@ -5,14 +5,15 @@ import type { PreparedBenchmark } from './common.ts';
  * Bit-twiddling and type-conversion ops: what quantized/packed formats
  * actually cost to get in and out of, as opposed to the flops-i8-* kernels
  * (which measure compute once data is already unpacked into i32/u32
- * registers). "Ops/s" here again isn't IEEE FLOPs, same caveat as flopsMath.ts.
+ * registers). "Ops" here count only the conversions themselves, one per
+ * direction per lane (an unpack or pack of a whole u32 counts as one), not
+ * the FMA / shifts / masks around them: the compiler folds and fuses those,
+ * so a source-level op count would overstate what executes.
  */
-/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. */
+/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. 2 ops per lane step (unpack + pack). */
 export declare function prepareFlopsU32PackUnpack(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** i32<->f32 round-trip: convert, FMA, convert back — the delta against the fp32 scalar test isolates conversion cost. */
+/** i32<->f32 round-trip: convert, FMA, convert back — 2 ops per lane step (one convert each way). */
 export declare function prepareFlopsI32F32Convert(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. */
+/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. Counted as 2 ops per lane round-trip (one convert each way). */
 export declare function prepareFlopsF32F16Convert(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** i32<->f16 round-trip, chained through f32 (there's no native int<->f16 builtin). */
-export declare function prepareFlopsI32F16Convert(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 //# sourceMappingURL=flopsConvert.d.ts.map

package/dist/benchmarks/flopsConvert.d.ts.map

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package/dist/benchmarks/flopsConvert.js

@@ -2,59 +2,39 @@ import { prepareFlopsBenchmark } from "./flopsCommon.js";
 import { flopsU32PackUnpackWgsl } from "../shaders/flopsU32PackUnpack.js";
 import { flopsI32F32ConvertWgsl } from "../shaders/flopsI32F32Convert.js";
 import { flopsF32F16ConvertWgsl } from "../shaders/flopsF32F16Convert.js";
-import { flopsI32F16ConvertWgsl } from "../shaders/flopsI32F16Convert.js";
-import { OPS_METRIC } from "./common.js";
 /**
  * Bit-twiddling and type-conversion ops: what quantized/packed formats
  * actually cost to get in and out of, as opposed to the flops-i8-* kernels
  * (which measure compute once data is already unpacked into i32/u32
- * registers). "Ops/s" here again isn't IEEE FLOPs, same caveat as flopsMath.ts.
+ * registers). "Ops" here count only the conversions themselves, one per
+ * direction per lane (an unpack or pack of a whole u32 counts as one), not
+ * the FMA / shifts / masks around them: the compiler folds and fuses those,
+ * so a source-level op count would overstate what executes.
  */
-/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. */
+/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. 2 ops per lane step (unpack + pack). */
 export function prepareFlopsU32PackUnpack(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-u32-packunpack',
-        label: 'u32 byte pack/unpack ops',
-        description: 'Eight independent u32 lanes, each step unpacking 4 bytes via shift+mask, incrementing them, and repacking the same way — no pack4x8 (or unpack4x8) builtin, just the bit-twiddling those compile to. 25 ops/lane/step, no unrolling.',
         wgsl: flopsU32PackUnpackWgsl,
-        metric: OPS_METRIC,
-        flopsPerIteration: 200,
+        flopsPerIteration: 64,
         defaultIterations: 256,
     }, harness);
 }
-/** i32<->f32 round-trip: convert, FMA, convert back — the delta against the fp32 scalar test isolates conversion cost. */
+/** i32<->f32 round-trip: convert, FMA, convert back — 2 ops per lane step (one convert each way). */
 export function prepareFlopsI32F32Convert(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i32-f32-convert',
-        label: 'i32<->f32 convert FLOPS',
-        description: 'Eight independent chains per thread, unrolled 4x: xi -> f32(xi)*a+b -> back to i32 each step. Same FMA as the fp32 scalar test plus a convert on each side, so the gap against that test isolates int<->float conversion cost.',
         wgsl: flopsI32F32ConvertWgsl,
-        metric: OPS_METRIC,
-        flopsPerIteration: 128,
+        flopsPerIteration: 64,
         defaultIterations: 256,
     }, harness);
 }
-/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. */
+/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. Counted as 2 ops per lane round-trip (one convert each way). */
 export function prepareFlopsF32F16Convert(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-f16-convert',
-        label: 'f32<->f16 convert FLOPS',
-        description: 'Eight independent vec2<f32> chains per thread, unrolled 4x: pack2x16float then unpack2x16float (round-trips through fp16 bits) plus a vec2 FMA to keep the chain moving. Unlike flops-f16-*, this needs no shader-f16 device feature — it measures the conversion, not f16 compute.',
         wgsl: flopsF32F16ConvertWgsl,
-        metric: OPS_METRIC,
-        flopsPerIteration: 192,
-        defaultIterations: 256,
-    }, harness);
-}
-/** i32<->f16 round-trip, chained through f32 (there's no native int<->f16 builtin). */
-export function prepareFlopsI32F16Convert(ctx, harness = {}) {
-    return prepareFlopsBenchmark(ctx, {
-        id: 'flops-i32-f16-convert',
-        label: 'i32<->f16 convert FLOPS',
-        description: 'Eight independent i32 chains per thread, unrolled 4x: xi -> f32 -> pack2x16float -> unpack2x16float -> f32*a+b -> i32. There is no native int<->f16 conversion, so this is what the real path (through f32) costs.',
-        wgsl: flopsI32F16ConvertWgsl,
-        metric: OPS_METRIC,
-        flopsPerIteration: 192,
+        flopsPerIteration: 128,
         defaultIterations: 256,
     }, harness);
 }

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package/dist/benchmarks/flopsF16.d.ts

@@ -3,7 +3,7 @@ import { type FlopsHarnessConfig } from './flopsCommon.ts';
 import type { PreparedBenchmark } from './common.ts';
 /** Raw fp16 FLOPS: eight independent scalar f16 FMA chains per thread, unrolled 4x. */
 export declare function prepareFlopsF16Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** fp16 vec4 FLOPS: one f16 FMA chain on a vec4<f16> register (4 independent lanes). */
+/** fp16 vec4 FLOPS: eight independent vec4<f16> FMA chains, unrolled 4x (same shape as scalar). */
 export declare function prepareFlopsF16Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** fp16 mat4 FLOPS: x = m*x + c chained with a mat4x4<f16>. */
 export declare function prepareFlopsF16Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;

package/dist/benchmarks/flopsF16.d.ts.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsF16.js

@@ -7,23 +7,19 @@ import { flopsF16MatvecWgsl } from "../shaders/flopsF16Matvec.js";
 export function prepareFlopsF16Scalar(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f16-scalar',
-        label: 'fp16 scalar FMA FLOPS',
-        description: 'Same eight independent, 4x-unrolled FMA chains as the fp32 scalar test, but every operand and accumulator is f16, so the chains run entirely in half precision.',
         wgsl: flopsF16ScalarWgsl,
         flopsPerIteration: 64,
         defaultIterations: 256,
         requiresF16: true,
     }, harness);
 }
-/** fp16 vec4 FLOPS: one f16 FMA chain on a vec4<f16> register (4 independent lanes). */
+/** fp16 vec4 FLOPS: eight independent vec4<f16> FMA chains, unrolled 4x (same shape as scalar). */
 export function prepareFlopsF16Vec4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f16-vec4',
-        label: 'fp16 vec4 FLOPS',
-        description: 'Same single FMA chain as the fp32 vec4 test, but held in a vec4<f16> register: 4 independent half-precision lanes per step. Only GPUs with packed-half ALUs run this faster than fp32.',
         wgsl: flopsF16Vec4Wgsl,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 256,
+        defaultIterations: 256,
         requiresF16: true,
     }, harness);
 }
@@ -31,8 +27,6 @@ export function prepareFlopsF16Vec4(ctx, harness = {}) {
 export function prepareFlopsF16Mat4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f16-mat4',
-        label: 'fp16 mat4 FLOPS',
-        description: 'Same bounded x = m * x + c recurrence as the fp32 mat4 test, but m, c, and x are all f16, so the mat4x4 x vec4 multiply runs entirely in half precision.',
         wgsl: flopsF16Mat4Wgsl,
         flopsPerIteration: 32,
         defaultIterations: 1024,
@@ -43,8 +37,6 @@ export function prepareFlopsF16Mat4(ctx, harness = {}) {
 export function prepareFlopsF16Matvec(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f16-matvec',
-        label: 'fp16 matvec FLOPS',
-        description: 'Same register-resident 4x8 matvec tile as the fp32 matvec test, but weights, inputs, and dot() accumulation are all f16. Pure ALU: the fp16 win here comes only from the ALU, not from halved memory traffic.',
         wgsl: flopsF16MatvecWgsl,
         flopsPerIteration: 64,
         defaultIterations: 512,

package/dist/benchmarks/flopsF16.js.map

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package/dist/benchmarks/flopsF32.d.ts

@@ -3,7 +3,7 @@ import { type FlopsHarnessConfig } from './flopsCommon.ts';
 import type { PreparedBenchmark } from './common.ts';
 /** Raw fp32 FLOPS: eight independent scalar FMA chains per thread, unrolled 4x. */
 export declare function prepareFlopsF32Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** fp32 vec4 FLOPS: one FMA chain on a vec4<f32> register (4 independent lanes). */
+/** fp32 vec4 FLOPS: eight independent vec4<f32> FMA chains, unrolled 4x (same shape as scalar). */
 export declare function prepareFlopsF32Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** fp32 mat4 FLOPS: x = m*x + c chained with a mat4x4<f32>. */
 export declare function prepareFlopsF32Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;

package/dist/benchmarks/flopsF32.d.ts.map

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package/dist/benchmarks/flopsF32.js

@@ -7,30 +7,24 @@ import { flopsF32MatvecWgsl } from "../shaders/flopsF32Matvec.js";
 export function prepareFlopsF32Scalar(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-scalar',
-        label: 'fp32 scalar FMA FLOPS',
-        description: 'Eight independent scalar f32 fused multiply-add chains per thread, unrolled 4x, so the ALU always has work in flight and the number reflects throughput rather than FMA latency. ~no memory traffic.',
         wgsl: flopsF32ScalarWgsl,
         flopsPerIteration: 64,
         defaultIterations: 256,
     }, harness);
 }
-/** fp32 vec4 FLOPS: one FMA chain on a vec4<f32> register (4 independent lanes). */
+/** fp32 vec4 FLOPS: eight independent vec4<f32> FMA chains, unrolled 4x (same shape as scalar). */
 export function prepareFlopsF32Vec4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-vec4',
-        label: 'fp32 vec4 FLOPS',
-        description: 'A single FMA chain held in a vec4<f32> register. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) this compiles to 4 independent scalar FMAs per step, so it measures how well 4-wide instruction-level parallelism hides latency, not a wider ALU.',
         wgsl: flopsF32Vec4Wgsl,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 256,
+        defaultIterations: 256,
     }, harness);
 }
 /** fp32 mat4 FLOPS: x = m*x + c chained with a mat4x4<f32>. */
 export function prepareFlopsF32Mat4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-mat4',
-        label: 'fp32 mat4 FLOPS',
-        description: 'x = m * x + c chained in a register with a mat4x4<f32> (a bounded contraction so it stays numerically stable): 16 FMAs per step with plenty of independent work, exercising the full mat4 x vec4 multiply.',
         wgsl: flopsF32Mat4Wgsl,
         flopsPerIteration: 32,
         defaultIterations: 1024,
@@ -40,8 +34,6 @@ export function prepareFlopsF32Mat4(ctx, harness = {}) {
 export function prepareFlopsF32Matvec(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-matvec',
-        label: 'fp32 matvec FLOPS',
-        description: 'A 4-row x 8-column f32 weight tile held in registers, applied to an 8-wide input every iteration via dot() (outputs feed back as the next inputs). The dot-product-accumulate shape of a GEMV inner loop with zero buffer traffic: pure ALU.',
         wgsl: flopsF32MatvecWgsl,
         flopsPerIteration: 64,
         defaultIterations: 512,

package/dist/benchmarks/flopsF32.js.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsI8.d.ts

@@ -3,7 +3,7 @@ import { type FlopsHarnessConfig } from './flopsCommon.ts';
 import type { PreparedBenchmark } from './common.ts';
 /** Raw int8-range FLOPS: eight independent scalar i32 multiply-add chains per thread, unrolled 4x. */
 export declare function prepareFlopsI8Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** int8-range vec4 FLOPS: one integer FMA chain on a vec4<i32> register (4 independent lanes). */
+/** int8-range vec4 FLOPS: eight independent vec4<i32> multiply-add chains, unrolled 4x (same shape as scalar). */
 export declare function prepareFlopsI8Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** int8-range mat4 FLOPS: a 4x4 integer matvec emulated via four dot(vec4<i32>) calls (WGSL has no mat4x4<i32>). */
 export declare function prepareFlopsI8Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
@@ -11,6 +11,6 @@ export declare function prepareFlopsI8Mat4(ctx: GpuContext, harness?: FlopsHarne
 export declare function prepareFlopsI8Matvec(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** int8 register-resident matvec tile on packed u32 words, two dot4I8Packed calls per output row. */
 export declare function prepareFlopsI8MatvecDp4a(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop. */
+/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop over eight independent accumulators. */
 export declare function prepareFlopsI8Dp4a(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 //# sourceMappingURL=flopsI8.d.ts.map

package/dist/benchmarks/flopsI8.d.ts.map

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package/dist/benchmarks/flopsI8.js

@@ -1,5 +1,4 @@
 import { prepareFlopsBenchmark } from "./flopsCommon.js";
-import { OPS_METRIC } from "./common.js";
 import { flopsI8ScalarWgsl } from "../shaders/flopsI8Scalar.js";
 import { flopsI8Vec4Wgsl } from "../shaders/flopsI8Vec4.js";
 import { flopsI8Mat4Wgsl } from "../shaders/flopsI8Mat4.js";
@@ -10,34 +9,25 @@ import { flopsI8MatvecDp4aWgsl } from "../shaders/flopsI8MatvecDp4a.js";
 export function prepareFlopsI8Scalar(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-scalar',
-        label: 'int8-range scalar FMA FLOPS',
-        description: 'Same eight independent, 4x-unrolled multiply-add chains as the fp32 scalar test, but on i32 (WGSL has no first-class i8 type). Measures integer multiply-add throughput; overflow wraps.',
         wgsl: flopsI8ScalarWgsl,
-        metric: OPS_METRIC,
         flopsPerIteration: 64,
         defaultIterations: 256,
     }, harness);
 }
-/** int8-range vec4 FLOPS: one integer FMA chain on a vec4<i32> register (4 independent lanes). */
+/** int8-range vec4 FLOPS: eight independent vec4<i32> multiply-add chains, unrolled 4x (same shape as scalar). */
 export function prepareFlopsI8Vec4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-vec4',
-        label: 'int8-range vec4 FLOPS',
-        description: 'Same single multiply-add chain as the fp32 vec4 test, but held in a vec4<i32> register: 4 independent integer lanes per step.',
         wgsl: flopsI8Vec4Wgsl,
-        metric: OPS_METRIC,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 256,
+        defaultIterations: 256,
     }, harness);
 }
 /** int8-range mat4 FLOPS: a 4x4 integer matvec emulated via four dot(vec4<i32>) calls (WGSL has no mat4x4<i32>). */
 export function prepareFlopsI8Mat4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-mat4',
-        label: 'int8-range mat4 FLOPS',
-        description: 'x = m * x + c chained in a register, where m is a 4x4 integer matrix emulated as four vec4<i32> rows combined with dot() (WGSL has no mat4x4<i32>): the same 4 dot products a real int4x4 multiply compiles to.',
         wgsl: flopsI8Mat4Wgsl,
-        metric: OPS_METRIC,
         flopsPerIteration: 32,
         defaultIterations: 1024,
     }, harness);
@@ -46,10 +36,7 @@ export function prepareFlopsI8Mat4(ctx, harness = {}) {
 export function prepareFlopsI8Matvec(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-matvec',
-        label: 'int8 matvec FLOPS (i32 dot)',
-        description: 'Same register-resident 4x8 matvec tile as the fp32 matvec test, with int8-range weights and inputs held unpacked as vec4<i32> and accumulated with integer dot(). The no-extension int8 path: what dot4I8Packed is competing against.',
         wgsl: flopsI8MatvecWgsl,
-        metric: OPS_METRIC,
         flopsPerIteration: 64,
         defaultIterations: 512,
     }, harness);
@@ -58,25 +45,19 @@ export function prepareFlopsI8Matvec(ctx, harness = {}) {
 export function prepareFlopsI8MatvecDp4a(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-matvec-dp4a',
-        label: 'int8 matvec FLOPS (dot4I8Packed)',
-        description: "Same 4x8 matvec tile, but weights and inputs stay packed four int8 lanes per u32 and each 4-wide dot product is one dot4I8Packed call from the packed_4x8_integer_dot_product extension. On GPUs without a native dp4a instruction this runs the extension's polyfill.",
         wgsl: flopsI8MatvecDp4aWgsl,
-        metric: OPS_METRIC,
         flopsPerIteration: 64,
         defaultIterations: 512,
         requiresI8Dot: true,
     }, harness);
 }
-/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop. */
+/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop over eight independent accumulators. */
 export function prepareFlopsI8Dp4a(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-dp4a',
-        label: 'int8 dot4I8Packed FLOPS',
-        description: "One thread per lane, accumulating dot4I8Packed(a, b) — the packed_4x8_integer_dot_product extension's 4-wide int8 dot-product instruction — in a tight loop to measure its peak throughput in isolation.",
         wgsl: flopsI8Dp4aWgsl,
-        metric: OPS_METRIC,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
         requiresI8Dot: true,
     }, harness);
 }

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