webgpu-bench 0.1.0

package/dist/benchmarks/flopsF16.js

@@ -0,0 +1,54 @@
+import { prepareFlopsBenchmark } from "./flopsCommon.js";
+import { flopsF16ScalarWgsl } from "../shaders/flopsF16Scalar.js";
+import { flopsF16Vec4Wgsl } from "../shaders/flopsF16Vec4.js";
+import { flopsF16Mat4Wgsl } from "../shaders/flopsF16Mat4.js";
+import { flopsF16MatvecWgsl } from "../shaders/flopsF16Matvec.js";
+/** Raw fp16 FLOPS: eight independent scalar f16 FMA chains per thread, unrolled 4x. */
+export function prepareFlopsF16Scalar(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f16-scalar',
+        label: 'fp16 scalar FMA FLOPS',
+        description: 'Same eight independent, 4x-unrolled FMA chains as the fp32 scalar test, but every operand and accumulator is f16, so the chains run entirely in half precision.',
+        wgsl: flopsF16ScalarWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+        requiresF16: true,
+    }, harness);
+}
+/** fp16 vec4 FLOPS: one f16 FMA chain on a vec4<f16> register (4 independent lanes). */
+export function prepareFlopsF16Vec4(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f16-vec4',
+        label: 'fp16 vec4 FLOPS',
+        description: 'Same single FMA chain as the fp32 vec4 test, but held in a vec4<f16> register: 4 independent half-precision lanes per step. Only GPUs with packed-half ALUs run this faster than fp32.',
+        wgsl: flopsF16Vec4Wgsl,
+        flopsPerIteration: 8,
+        defaultIterations: 1024,
+        requiresF16: true,
+    }, harness);
+}
+/** fp16 mat4 FLOPS: x = m*x + c chained with a mat4x4<f16>. */
+export function prepareFlopsF16Mat4(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f16-mat4',
+        label: 'fp16 mat4 FLOPS',
+        description: 'Same bounded x = m * x + c recurrence as the fp32 mat4 test, but m, c, and x are all f16, so the mat4x4 x vec4 multiply runs entirely in half precision.',
+        wgsl: flopsF16Mat4Wgsl,
+        flopsPerIteration: 32,
+        defaultIterations: 1024,
+        requiresF16: true,
+    }, harness);
+}
+/** fp16 register-resident matvec tile: 4x8 f16 weights in registers, two dot() calls per output row. */
+export function prepareFlopsF16Matvec(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f16-matvec',
+        label: 'fp16 matvec FLOPS',
+        description: 'Same register-resident 4x8 matvec tile as the fp32 matvec test, but weights, inputs, and dot() accumulation are all f16. Pure ALU: the fp16 win here comes only from the ALU, not from halved memory traffic.',
+        wgsl: flopsF16MatvecWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 512,
+        requiresF16: true,
+    }, harness);
+}
+//# sourceMappingURL=flopsF16.js.map

package/dist/benchmarks/flopsF16.js.map

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package/dist/benchmarks/flopsF32.d.ts

@@ -0,0 +1,12 @@
+import type { GpuContext } from '../gpu/context.ts';
+import { type FlopsHarnessConfig } from './flopsCommon.ts';
+import type { PreparedBenchmark } from './common.ts';
+/** Raw fp32 FLOPS: eight independent scalar FMA chains per thread, unrolled 4x. */
+export declare function prepareFlopsF32Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 vec4 FLOPS: one FMA chain on a vec4<f32> register (4 independent lanes). */
+export declare function prepareFlopsF32Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 mat4 FLOPS: x = m*x + c chained with a mat4x4<f32>. */
+export declare function prepareFlopsF32Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 register-resident matvec tile: 4x8 weights in registers, two dot() calls per output row. */
+export declare function prepareFlopsF32Matvec(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+//# sourceMappingURL=flopsF32.d.ts.map

package/dist/benchmarks/flopsF32.d.ts.map

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package/dist/benchmarks/flopsF32.js

@@ -0,0 +1,50 @@
+import { prepareFlopsBenchmark } from "./flopsCommon.js";
+import { flopsF32ScalarWgsl } from "../shaders/flopsF32Scalar.js";
+import { flopsF32Vec4Wgsl } from "../shaders/flopsF32Vec4.js";
+import { flopsF32Mat4Wgsl } from "../shaders/flopsF32Mat4.js";
+import { flopsF32MatvecWgsl } from "../shaders/flopsF32Matvec.js";
+/** Raw fp32 FLOPS: eight independent scalar FMA chains per thread, unrolled 4x. */
+export function prepareFlopsF32Scalar(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-scalar',
+        label: 'fp32 scalar FMA FLOPS',
+        description: 'Eight independent scalar f32 fused multiply-add chains per thread, unrolled 4x, so the ALU always has work in flight and the number reflects throughput rather than FMA latency. ~no memory traffic.',
+        wgsl: flopsF32ScalarWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+    }, harness);
+}
+/** fp32 vec4 FLOPS: one FMA chain on a vec4<f32> register (4 independent lanes). */
+export function prepareFlopsF32Vec4(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-vec4',
+        label: 'fp32 vec4 FLOPS',
+        description: 'A single FMA chain held in a vec4<f32> register. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) this compiles to 4 independent scalar FMAs per step, so it measures how well 4-wide instruction-level parallelism hides latency, not a wider ALU.',
+        wgsl: flopsF32Vec4Wgsl,
+        flopsPerIteration: 8,
+        defaultIterations: 1024,
+    }, harness);
+}
+/** fp32 mat4 FLOPS: x = m*x + c chained with a mat4x4<f32>. */
+export function prepareFlopsF32Mat4(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-mat4',
+        label: 'fp32 mat4 FLOPS',
+        description: 'x = m * x + c chained in a register with a mat4x4<f32> (a bounded contraction so it stays numerically stable): 16 FMAs per step with plenty of independent work, exercising the full mat4 x vec4 multiply.',
+        wgsl: flopsF32Mat4Wgsl,
+        flopsPerIteration: 32,
+        defaultIterations: 1024,
+    }, harness);
+}
+/** fp32 register-resident matvec tile: 4x8 weights in registers, two dot() calls per output row. */
+export function prepareFlopsF32Matvec(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-matvec',
+        label: 'fp32 matvec FLOPS',
+        description: 'A 4-row x 8-column f32 weight tile held in registers, applied to an 8-wide input every iteration via dot() (outputs feed back as the next inputs). The dot-product-accumulate shape of a GEMV inner loop with zero buffer traffic: pure ALU.',
+        wgsl: flopsF32MatvecWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 512,
+    }, harness);
+}
+//# sourceMappingURL=flopsF32.js.map

package/dist/benchmarks/flopsF32.js.map

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package/dist/benchmarks/flopsI8.d.ts

@@ -0,0 +1,16 @@
+import type { GpuContext } from '../gpu/context.ts';
+import { type FlopsHarnessConfig } from './flopsCommon.ts';
+import type { PreparedBenchmark } from './common.ts';
+/** Raw int8-range FLOPS: eight independent scalar i32 multiply-add chains per thread, unrolled 4x. */
+export declare function prepareFlopsI8Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** int8-range vec4 FLOPS: one integer FMA chain on a vec4<i32> register (4 independent lanes). */
+export declare function prepareFlopsI8Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** int8-range mat4 FLOPS: a 4x4 integer matvec emulated via four dot(vec4<i32>) calls (WGSL has no mat4x4<i32>). */
+export declare function prepareFlopsI8Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** int8 register-resident matvec tile with weights unpacked to vec4<i32>, two integer dot() calls per output row. */
+export declare function prepareFlopsI8Matvec(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** int8 register-resident matvec tile on packed u32 words, two dot4I8Packed calls per output row. */
+export declare function prepareFlopsI8MatvecDp4a(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop. */
+export declare function prepareFlopsI8Dp4a(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+//# sourceMappingURL=flopsI8.d.ts.map

package/dist/benchmarks/flopsI8.d.ts.map

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package/dist/benchmarks/flopsI8.js

@@ -0,0 +1,83 @@
+import { prepareFlopsBenchmark } from "./flopsCommon.js";
+import { OPS_METRIC } from "./common.js";
+import { flopsI8ScalarWgsl } from "../shaders/flopsI8Scalar.js";
+import { flopsI8Vec4Wgsl } from "../shaders/flopsI8Vec4.js";
+import { flopsI8Mat4Wgsl } from "../shaders/flopsI8Mat4.js";
+import { flopsI8Dp4aWgsl } from "../shaders/flopsI8Dp4a.js";
+import { flopsI8MatvecWgsl } from "../shaders/flopsI8Matvec.js";
+import { flopsI8MatvecDp4aWgsl } from "../shaders/flopsI8MatvecDp4a.js";
+/** Raw int8-range FLOPS: eight independent scalar i32 multiply-add chains per thread, unrolled 4x. */
+export function prepareFlopsI8Scalar(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-i8-scalar',
+        label: 'int8-range scalar FMA FLOPS',
+        description: 'Same eight independent, 4x-unrolled multiply-add chains as the fp32 scalar test, but on i32 (WGSL has no first-class i8 type). Measures integer multiply-add throughput; overflow wraps.',
+        wgsl: flopsI8ScalarWgsl,
+        metric: OPS_METRIC,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+    }, harness);
+}
+/** int8-range vec4 FLOPS: one integer FMA chain on a vec4<i32> register (4 independent lanes). */
+export function prepareFlopsI8Vec4(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-i8-vec4',
+        label: 'int8-range vec4 FLOPS',
+        description: 'Same single multiply-add chain as the fp32 vec4 test, but held in a vec4<i32> register: 4 independent integer lanes per step.',
+        wgsl: flopsI8Vec4Wgsl,
+        metric: OPS_METRIC,
+        flopsPerIteration: 8,
+        defaultIterations: 1024,
+    }, harness);
+}
+/** int8-range mat4 FLOPS: a 4x4 integer matvec emulated via four dot(vec4<i32>) calls (WGSL has no mat4x4<i32>). */
+export function prepareFlopsI8Mat4(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-i8-mat4',
+        label: 'int8-range mat4 FLOPS',
+        description: 'x = m * x + c chained in a register, where m is a 4x4 integer matrix emulated as four vec4<i32> rows combined with dot() (WGSL has no mat4x4<i32>): the same 4 dot products a real int4x4 multiply compiles to.',
+        wgsl: flopsI8Mat4Wgsl,
+        metric: OPS_METRIC,
+        flopsPerIteration: 32,
+        defaultIterations: 1024,
+    }, harness);
+}
+/** int8 register-resident matvec tile with weights unpacked to vec4<i32>, two integer dot() calls per output row. */
+export function prepareFlopsI8Matvec(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-i8-matvec',
+        label: 'int8 matvec FLOPS (i32 dot)',
+        description: 'Same register-resident 4x8 matvec tile as the fp32 matvec test, with int8-range weights and inputs held unpacked as vec4<i32> and accumulated with integer dot(). The no-extension int8 path: what dot4I8Packed is competing against.',
+        wgsl: flopsI8MatvecWgsl,
+        metric: OPS_METRIC,
+        flopsPerIteration: 64,
+        defaultIterations: 512,
+    }, harness);
+}
+/** int8 register-resident matvec tile on packed u32 words, two dot4I8Packed calls per output row. */
+export function prepareFlopsI8MatvecDp4a(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-i8-matvec-dp4a',
+        label: 'int8 matvec FLOPS (dot4I8Packed)',
+        description: "Same 4x8 matvec tile, but weights and inputs stay packed four int8 lanes per u32 and each 4-wide dot product is one dot4I8Packed call from the packed_4x8_integer_dot_product extension. On GPUs without a native dp4a instruction this runs the extension's polyfill.",
+        wgsl: flopsI8MatvecDp4aWgsl,
+        metric: OPS_METRIC,
+        flopsPerIteration: 64,
+        defaultIterations: 512,
+        requiresI8Dot: true,
+    }, harness);
+}
+/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop. */
+export function prepareFlopsI8Dp4a(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-i8-dp4a',
+        label: 'int8 dot4I8Packed FLOPS',
+        description: "One thread per lane, accumulating dot4I8Packed(a, b) — the packed_4x8_integer_dot_product extension's 4-wide int8 dot-product instruction — in a tight loop to measure its peak throughput in isolation.",
+        wgsl: flopsI8Dp4aWgsl,
+        metric: OPS_METRIC,
+        flopsPerIteration: 8,
+        defaultIterations: 1024,
+        requiresI8Dot: true,
+    }, harness);
+}
+//# sourceMappingURL=flopsI8.js.map

package/dist/benchmarks/flopsI8.js.map

@@ -0,0 +1 @@
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package/dist/benchmarks/flopsMath.d.ts

@@ -0,0 +1,28 @@
+import type { GpuContext } from '../gpu/context.ts';
+import { type FlopsHarnessConfig } from './flopsCommon.ts';
+import type { PreparedBenchmark } from './common.ts';
+/**
+ * "Real" ALU ops beyond multiply-add: division and the transcendentals
+ * (sqrt, pow, sin/cos, log) that 3D math leans on constantly (normalize,
+ * lighting falloff, exponential roughness/tonemap curves, trig for angles).
+ * These aren't FLOPs in the IEEE sense — a GPU's sqrt/sin/pow are either a
+ * dedicated special-function-unit instruction or a multi-instruction
+ * polynomial approximation, so "ops/s" here means "results/s", not a fixed
+ * instruction count — but they're counted with the same MAC-as-2 convention
+ * as the multiply-add kernels so the throughput numbers stay comparable.
+ */
+/** fp32 divide-add ops: same shape as the fp32 scalar FMA test, multiply swapped for divide. */
+export declare function prepareFlopsF32Div(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** i32 divide-add ops: same shape as the int8-range scalar test, multiply swapped for divide. */
+export declare function prepareFlopsI32Div(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 sqrt-add ops: sqrt in place of the FMA multiply. */
+export declare function prepareFlopsF32Sqrt(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 rsqrt-add ops: inverseSqrt in place of the FMA multiply. */
+export declare function prepareFlopsF32Rsqrt(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 pow-add ops: pow in place of the FMA multiply. */
+export declare function prepareFlopsF32Pow(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 sin(cos(x)) ops: the trig pair 3D math uses for angles/rotations. */
+export declare function prepareFlopsF32Sincos(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+/** fp32 ln-add ops: natural log in place of the FMA multiply. */
+export declare function prepareFlopsF32Log(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
+//# sourceMappingURL=flopsMath.d.ts.map

package/dist/benchmarks/flopsMath.d.ts.map

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package/dist/benchmarks/flopsMath.js

@@ -0,0 +1,98 @@
+import { prepareFlopsBenchmark } from "./flopsCommon.js";
+import { flopsF32DivWgsl } from "../shaders/flopsF32Div.js";
+import { flopsI32DivWgsl } from "../shaders/flopsI32Div.js";
+import { flopsF32SqrtWgsl } from "../shaders/flopsF32Sqrt.js";
+import { flopsF32RsqrtWgsl } from "../shaders/flopsF32Rsqrt.js";
+import { flopsF32PowWgsl } from "../shaders/flopsF32Pow.js";
+import { flopsF32SincosWgsl } from "../shaders/flopsF32Sincos.js";
+import { flopsF32LogWgsl } from "../shaders/flopsF32Log.js";
+import { OPS_METRIC } from "./common.js";
+/**
+ * "Real" ALU ops beyond multiply-add: division and the transcendentals
+ * (sqrt, pow, sin/cos, log) that 3D math leans on constantly (normalize,
+ * lighting falloff, exponential roughness/tonemap curves, trig for angles).
+ * These aren't FLOPs in the IEEE sense — a GPU's sqrt/sin/pow are either a
+ * dedicated special-function-unit instruction or a multi-instruction
+ * polynomial approximation, so "ops/s" here means "results/s", not a fixed
+ * instruction count — but they're counted with the same MAC-as-2 convention
+ * as the multiply-add kernels so the throughput numbers stay comparable.
+ */
+/** fp32 divide-add ops: same shape as the fp32 scalar FMA test, multiply swapped for divide. */
+export function prepareFlopsF32Div(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-div',
+        label: 'fp32 div FLOPS',
+        description: 'Eight independent scalar f32 divide-add chains per thread, unrolled 4x — the fp32 scalar FMA test with divide in place of multiply, so the gap between the two isolates the cost of division.',
+        wgsl: flopsF32DivWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+    }, harness);
+}
+/** i32 divide-add ops: same shape as the int8-range scalar test, multiply swapped for divide. */
+export function prepareFlopsI32Div(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-i32-div',
+        label: 'i32 div FLOPS',
+        description: 'Eight independent scalar i32 divide-add chains per thread, unrolled 4x — the int8-range scalar test with divide in place of multiply. Integer division is typically the slowest basic ALU op on a GPU.',
+        wgsl: flopsI32DivWgsl,
+        metric: OPS_METRIC,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+    }, harness);
+}
+/** fp32 sqrt-add ops: sqrt in place of the FMA multiply. */
+export function prepareFlopsF32Sqrt(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-sqrt',
+        label: 'fp32 sqrt FLOPS',
+        description: 'Eight independent scalar f32 sqrt-add chains per thread, unrolled 4x. sqrt is a common special-function-unit instruction; this measures its throughput in isolation.',
+        wgsl: flopsF32SqrtWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+    }, harness);
+}
+/** fp32 rsqrt-add ops: inverseSqrt in place of the FMA multiply. */
+export function prepareFlopsF32Rsqrt(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-rsqrt',
+        label: 'fp32 rsqrt FLOPS',
+        description: 'Eight independent scalar f32 inverseSqrt-add chains per thread, unrolled 4x. The op behind every normalize(); most GPUs have a dedicated fast-rsqrt path, so compare against flops-f32-sqrt to see the gap.',
+        wgsl: flopsF32RsqrtWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+    }, harness);
+}
+/** fp32 pow-add ops: pow in place of the FMA multiply. */
+export function prepareFlopsF32Pow(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-pow',
+        label: 'fp32 pow FLOPS',
+        description: 'Eight independent scalar f32 pow-add chains per thread, unrolled 4x. pow(x, e) for a non-integer e is usually exp2(e * log2(x)) under the hood — several instructions — so expect this well below sqrt/div throughput.',
+        wgsl: flopsF32PowWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 128,
+    }, harness);
+}
+/** fp32 sin(cos(x)) ops: the trig pair 3D math uses for angles/rotations. */
+export function prepareFlopsF32Sincos(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-sincos',
+        label: 'fp32 sin/cos FLOPS',
+        description: 'Eight independent scalar f32 cos(sin(x)) chains per thread, unrolled 4x. Naturally bounded to [-1, 1], so no stabilization term is needed. Measures combined sin+cos throughput.',
+        wgsl: flopsF32SincosWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 128,
+    }, harness);
+}
+/** fp32 ln-add ops: natural log in place of the FMA multiply. */
+export function prepareFlopsF32Log(ctx, harness = {}) {
+    return prepareFlopsBenchmark(ctx, {
+        id: 'flops-f32-log',
+        label: 'fp32 ln FLOPS',
+        description: 'Eight independent scalar f32 ln-add chains per thread, unrolled 4x. log(x) is usually log2(x) * ln(2) under the hood, so expect throughput close to a raw log2 special-function call.',
+        wgsl: flopsF32LogWgsl,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
+    }, harness);
+}
+//# sourceMappingURL=flopsMath.js.map

package/dist/benchmarks/flopsMath.js.map

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package/dist/benchmarks/streamBandwidth.d.ts

@@ -0,0 +1,17 @@
+import type { GpuContext } from '../gpu/context.ts';
+import type { GeneratedData } from '../data/generate.ts';
+import { type HarnessConfig, type PreparedBenchmark } from './common.ts';
+/**
+ * Read-bandwidth test: streams the (already-allocated, matrix-sized) input
+ * buffer through each thread with nothing but addition, writing back a
+ * single scalar per thread. Reads vastly outweigh writes, so `gbps` here is
+ * a read-bandwidth-bound number close to the device's peak.
+ */
+export declare function prepareReadBandwidth(ctx: GpuContext, data: GeneratedData, harness?: HarnessConfig): Promise<PreparedBenchmark>;
+/**
+ * Write-bandwidth test: streams computed values out into a matrix-sized
+ * output buffer. No buffer reads at all, so `gbps` here is a
+ * write-bandwidth-bound number close to the device's peak.
+ */
+export declare function prepareWriteBandwidth(ctx: GpuContext, data: GeneratedData, harness?: HarnessConfig): Promise<PreparedBenchmark>;
+//# sourceMappingURL=streamBandwidth.d.ts.map

package/dist/benchmarks/streamBandwidth.d.ts.map

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package/dist/benchmarks/streamBandwidth.js

@@ -0,0 +1,78 @@
+import { createUniformBuffer, createStorageBuffer, createEmptyStorageBuffer } from "../gpu/buffers.js";
+import { createPipeline, prepareKernelBenchmark, BYTES_METRIC, } from "./common.js";
+import { streamReadWgsl } from "../shaders/streamRead.js";
+import { streamWriteWgsl } from "../shaders/streamWrite.js";
+/**
+ * Read-bandwidth test: streams the (already-allocated, matrix-sized) input
+ * buffer through each thread with nothing but addition, writing back a
+ * single scalar per thread. Reads vastly outweigh writes, so `gbps` here is
+ * a read-bandwidth-bound number close to the device's peak.
+ */
+export async function prepareReadBandwidth(ctx, data, harness = {}) {
+    const { device } = ctx;
+    const cols4 = data.cols / 4;
+    const pipeline = await createPipeline(device, 'stream-read', streamReadWgsl);
+    const paramsBuf = createUniformBuffer(device, new Uint32Array([data.rows, cols4]), 'params');
+    const dataBuf = createStorageBuffer(device, data.matrix, 'data');
+    const outBuf = createEmptyStorageBuffer(device, data.rows * 4, 'out');
+    const bindGroup = device.createBindGroup({
+        layout: pipeline.getBindGroupLayout(0),
+        entries: [
+            { binding: 0, resource: { buffer: paramsBuf } },
+            { binding: 1, resource: { buffer: dataBuf } },
+            { binding: 2, resource: { buffer: outBuf } },
+        ],
+    });
+    return prepareKernelBenchmark({
+        id: 'read-bandwidth',
+        label: 'Read bandwidth',
+        description: 'One thread per row; streams a large buffer in via vec4<f32> loads and addition only, writes one scalar. Read-bandwidth-bound.',
+        source: streamReadWgsl,
+        category: 'bandwidth',
+        ctx,
+        rows: data.rows,
+        cols: data.cols,
+        metric: BYTES_METRIC,
+        amountPerOp: data.matrix.byteLength,
+        workgroupsPerIteration: [Math.ceil(data.rows / 64), 1, 1],
+        pipeline,
+        bindGroup,
+        ...harness,
+    });
+}
+/**
+ * Write-bandwidth test: streams computed values out into a matrix-sized
+ * output buffer. No buffer reads at all, so `gbps` here is a
+ * write-bandwidth-bound number close to the device's peak.
+ */
+export async function prepareWriteBandwidth(ctx, data, harness = {}) {
+    const { device } = ctx;
+    const cols4 = data.cols / 4;
+    const pipeline = await createPipeline(device, 'stream-write', streamWriteWgsl);
+    const paramsBuf = createUniformBuffer(device, new Uint32Array([data.rows, cols4]), 'params');
+    const outBuf = createEmptyStorageBuffer(device, data.matrix.byteLength, 'out');
+    const bindGroup = device.createBindGroup({
+        layout: pipeline.getBindGroupLayout(0),
+        entries: [
+            { binding: 0, resource: { buffer: paramsBuf } },
+            { binding: 1, resource: { buffer: outBuf } },
+        ],
+    });
+    return prepareKernelBenchmark({
+        id: 'write-bandwidth',
+        label: 'Write bandwidth',
+        description: 'One thread per row; stores computed vec4<f32> values into a large buffer with no buffer reads. Write-bandwidth-bound.',
+        source: streamWriteWgsl,
+        category: 'bandwidth',
+        ctx,
+        rows: data.rows,
+        cols: data.cols,
+        metric: BYTES_METRIC,
+        amountPerOp: data.matrix.byteLength,
+        workgroupsPerIteration: [Math.ceil(data.rows / 64), 1, 1],
+        pipeline,
+        bindGroup,
+        ...harness,
+    });
+}
+//# sourceMappingURL=streamBandwidth.js.map

package/dist/benchmarks/streamBandwidth.js.map

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package/dist/data/generate.d.ts

@@ -0,0 +1,23 @@
+/**
+ * Deterministic data generation for the bandwidth benchmarks. Every
+ * benchmark run (in every browser, on every machine) sees a byte-identical
+ * buffer to stream, so results are reproducible run to run.
+ */
+/** Small, fast, seedable PRNG (mulberry32) — deterministic across platforms. */
+export declare function mulberry32(seed: number): () => number;
+/** Round up to the next multiple of 4 (so vec4/mat4 kernels can index without bounds checks). */
+export declare function padToMultipleOf4(n: number): number;
+export interface GeneratedData {
+    rows: number;
+    cols: number;
+    /** row-major, rows x cols */
+    matrix: Float32Array;
+    vector: Float32Array;
+}
+/**
+ * Generates a deterministic pseudo-random matrix and vector, values in
+ * [-1, 1), sized to LLM-weight-like magnitudes (scaled by 1/sqrt(cols) so
+ * dot products don't blow up in magnitude as cols grows).
+ */
+export declare function generateMatVecData(rows: number, cols: number, seed?: number): GeneratedData;
+//# sourceMappingURL=generate.d.ts.map

package/dist/data/generate.d.ts.map

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package/dist/data/generate.js

@@ -0,0 +1,41 @@
+/**
+ * Deterministic data generation for the bandwidth benchmarks. Every
+ * benchmark run (in every browser, on every machine) sees a byte-identical
+ * buffer to stream, so results are reproducible run to run.
+ */
+/** Small, fast, seedable PRNG (mulberry32) — deterministic across platforms. */
+export function mulberry32(seed) {
+    let a = seed >>> 0;
+    return () => {
+        a = (a + 0x6d2b79f5) | 0;
+        let t = a;
+        t = Math.imul(t ^ (t >>> 15), t | 1);
+        t ^= t + Math.imul(t ^ (t >>> 7), t | 61);
+        return ((t ^ (t >>> 14)) >>> 0) / 4294967296;
+    };
+}
+/** Round up to the next multiple of 4 (so vec4/mat4 kernels can index without bounds checks). */
+export function padToMultipleOf4(n) {
+    return Math.ceil(n / 4) * 4;
+}
+/**
+ * Generates a deterministic pseudo-random matrix and vector, values in
+ * [-1, 1), sized to LLM-weight-like magnitudes (scaled by 1/sqrt(cols) so
+ * dot products don't blow up in magnitude as cols grows).
+ */
+export function generateMatVecData(rows, cols, seed = 1234) {
+    const paddedRows = padToMultipleOf4(rows);
+    const paddedCols = padToMultipleOf4(cols);
+    const rand = mulberry32(seed);
+    const scale = 1 / Math.sqrt(paddedCols);
+    const matrix = new Float32Array(paddedRows * paddedCols);
+    for (let i = 0; i < matrix.length; i++) {
+        matrix[i] = (rand() * 2 - 1) * scale;
+    }
+    const vector = new Float32Array(paddedCols);
+    for (let i = 0; i < vector.length; i++) {
+        vector[i] = rand() * 2 - 1;
+    }
+    return { rows: paddedRows, cols: paddedCols, matrix, vector };
+}
+//# sourceMappingURL=generate.js.map

package/dist/data/generate.js.map

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