rp2040js 0.17.17 → 0.18.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/cjs/clock/clock.d.ts +11 -11
- package/dist/cjs/clock/clock.js +2 -2
- package/dist/cjs/clock/mock-clock.d.ts +17 -17
- package/dist/cjs/clock/mock-clock.js +52 -52
- package/dist/cjs/clock/realtime-clock.d.ts +23 -23
- package/dist/cjs/clock/realtime-clock.js +73 -73
- package/dist/cjs/cortex-m0-core.d.ts +87 -87
- package/dist/cjs/cortex-m0-core.js +1251 -1251
- package/dist/cjs/gdb/gdb-connection.d.ts +11 -11
- package/dist/cjs/gdb/gdb-connection.js +57 -57
- package/dist/cjs/gdb/gdb-server.d.ts +23 -23
- package/dist/cjs/gdb/gdb-server.js +232 -232
- package/dist/cjs/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/cjs/gdb/gdb-tcp-server.js +34 -34
- package/dist/cjs/gdb/gdb-utils.d.ts +9 -9
- package/dist/cjs/gdb/gdb-utils.js +48 -48
- package/dist/cjs/gpio-pin.d.ts +56 -56
- package/dist/cjs/gpio-pin.js +216 -216
- package/dist/cjs/index.d.ts +11 -11
- package/dist/cjs/index.js +36 -36
- package/dist/cjs/interpolator.d.ts +36 -36
- package/dist/cjs/interpolator.js +150 -150
- package/dist/cjs/irq.d.ts +29 -29
- package/dist/cjs/irq.js +33 -33
- package/dist/cjs/peripherals/adc.d.ts +52 -52
- package/dist/cjs/peripherals/adc.js +261 -261
- package/dist/cjs/peripherals/busctrl.d.ts +10 -10
- package/dist/cjs/peripherals/busctrl.js +84 -84
- package/dist/cjs/peripherals/clocks.d.ts +9 -9
- package/dist/cjs/peripherals/clocks.js +42 -42
- package/dist/cjs/peripherals/dma.d.ts +109 -109
- package/dist/cjs/peripherals/dma.js +520 -520
- package/dist/cjs/peripherals/i2c.d.ts +54 -54
- package/dist/cjs/peripherals/i2c.js +458 -458
- package/dist/cjs/peripherals/io.d.ts +11 -11
- package/dist/cjs/peripherals/io.js +100 -100
- package/dist/cjs/peripherals/pads.d.ts +13 -13
- package/dist/cjs/peripherals/pads.js +58 -58
- package/dist/cjs/peripherals/peripheral.d.ts +22 -22
- package/dist/cjs/peripherals/peripheral.js +61 -61
- package/dist/cjs/peripherals/pio.d.ts +120 -120
- package/dist/cjs/peripherals/pio.js +1086 -1086
- package/dist/cjs/peripherals/ppb.d.ts +25 -25
- package/dist/cjs/peripherals/ppb.js +229 -229
- package/dist/cjs/peripherals/pwm.d.ts +65 -65
- package/dist/cjs/peripherals/pwm.js +372 -372
- package/dist/cjs/peripherals/reset.d.ts +8 -8
- package/dist/cjs/peripherals/reset.js +40 -40
- package/dist/cjs/peripherals/rtc.d.ts +10 -10
- package/dist/cjs/peripherals/rtc.js +74 -74
- package/dist/cjs/peripherals/spi.d.ts +38 -38
- package/dist/cjs/peripherals/spi.js +240 -240
- package/dist/cjs/peripherals/ssi.d.ts +6 -6
- package/dist/cjs/peripherals/ssi.js +43 -43
- package/dist/cjs/peripherals/syscfg.d.ts +5 -5
- package/dist/cjs/peripherals/syscfg.js +26 -26
- package/dist/cjs/peripherals/sysinfo.d.ts +4 -4
- package/dist/cjs/peripherals/sysinfo.js +22 -22
- package/dist/cjs/peripherals/tbman.d.ts +4 -4
- package/dist/cjs/peripherals/tbman.js +17 -17
- package/dist/cjs/peripherals/timer.d.ts +18 -18
- package/dist/cjs/peripherals/timer.js +156 -156
- package/dist/cjs/peripherals/uart.d.ts +31 -31
- package/dist/cjs/peripherals/uart.js +132 -132
- package/dist/cjs/peripherals/usb.d.ts +29 -29
- package/dist/cjs/peripherals/usb.js +309 -309
- package/dist/cjs/rp2040.d.ts +71 -71
- package/dist/cjs/rp2040.js +361 -361
- package/dist/cjs/sio.d.ts +21 -21
- package/dist/cjs/sio.js +425 -425
- package/dist/cjs/usb/cdc.d.ts +20 -20
- package/dist/cjs/usb/cdc.js +126 -126
- package/dist/cjs/usb/interfaces.d.ts +47 -47
- package/dist/cjs/usb/interfaces.js +46 -46
- package/dist/cjs/usb/setup.d.ts +5 -5
- package/dist/cjs/usb/setup.js +53 -53
- package/dist/cjs/utils/assembler.d.ts +79 -79
- package/dist/cjs/utils/assembler.js +328 -328
- package/dist/cjs/utils/bit.d.ts +3 -3
- package/dist/cjs/utils/bit.js +15 -15
- package/dist/cjs/utils/fifo.d.ts +15 -15
- package/dist/cjs/utils/fifo.js +56 -56
- package/dist/cjs/utils/logging.d.ts +23 -23
- package/dist/cjs/utils/logging.js +48 -48
- package/dist/cjs/utils/pio-assembler.d.ts +45 -45
- package/dist/cjs/utils/pio-assembler.js +87 -87
- package/dist/cjs/utils/time.d.ts +2 -2
- package/dist/cjs/utils/time.js +32 -32
- package/dist/cjs/utils/timer32.d.ts +57 -57
- package/dist/cjs/utils/timer32.js +208 -208
- package/dist/esm/clock/clock.d.ts +11 -11
- package/dist/esm/clock/clock.js +1 -1
- package/dist/esm/clock/mock-clock.d.ts +17 -17
- package/dist/esm/clock/mock-clock.js +47 -47
- package/dist/esm/clock/realtime-clock.d.ts +23 -23
- package/dist/esm/clock/realtime-clock.js +68 -68
- package/dist/esm/cortex-m0-core.d.ts +87 -87
- package/dist/esm/cortex-m0-core.js +1247 -1247
- package/dist/esm/gdb/gdb-connection.d.ts +11 -11
- package/dist/esm/gdb/gdb-connection.js +53 -53
- package/dist/esm/gdb/gdb-server.d.ts +23 -23
- package/dist/esm/gdb/gdb-server.js +228 -228
- package/dist/esm/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/esm/gdb/gdb-tcp-server.js +30 -30
- package/dist/esm/gdb/gdb-utils.d.ts +9 -9
- package/dist/esm/gdb/gdb-utils.js +36 -36
- package/dist/esm/gpio-pin.d.ts +56 -56
- package/dist/esm/gpio-pin.js +212 -212
- package/dist/esm/index.d.ts +11 -11
- package/dist/esm/index.js +11 -11
- package/dist/esm/interpolator.d.ts +36 -36
- package/dist/esm/interpolator.js +145 -145
- package/dist/esm/irq.d.ts +29 -29
- package/dist/esm/irq.js +30 -30
- package/dist/esm/peripherals/adc.d.ts +52 -52
- package/dist/esm/peripherals/adc.js +257 -257
- package/dist/esm/peripherals/busctrl.d.ts +10 -10
- package/dist/esm/peripherals/busctrl.js +80 -80
- package/dist/esm/peripherals/clocks.d.ts +9 -9
- package/dist/esm/peripherals/clocks.js +38 -38
- package/dist/esm/peripherals/dma.d.ts +109 -109
- package/dist/esm/peripherals/dma.js +515 -515
- package/dist/esm/peripherals/i2c.d.ts +54 -54
- package/dist/esm/peripherals/i2c.js +454 -454
- package/dist/esm/peripherals/io.d.ts +11 -11
- package/dist/esm/peripherals/io.js +96 -96
- package/dist/esm/peripherals/pads.d.ts +13 -13
- package/dist/esm/peripherals/pads.js +54 -54
- package/dist/esm/peripherals/peripheral.d.ts +22 -22
- package/dist/esm/peripherals/peripheral.js +55 -55
- package/dist/esm/peripherals/pio.d.ts +120 -120
- package/dist/esm/peripherals/pio.js +1081 -1081
- package/dist/esm/peripherals/ppb.d.ts +25 -25
- package/dist/esm/peripherals/ppb.js +225 -225
- package/dist/esm/peripherals/pwm.d.ts +65 -65
- package/dist/esm/peripherals/pwm.js +368 -368
- package/dist/esm/peripherals/reset.d.ts +8 -8
- package/dist/esm/peripherals/reset.js +36 -36
- package/dist/esm/peripherals/rtc.d.ts +10 -10
- package/dist/esm/peripherals/rtc.js +70 -70
- package/dist/esm/peripherals/spi.d.ts +38 -38
- package/dist/esm/peripherals/spi.js +236 -236
- package/dist/esm/peripherals/ssi.d.ts +6 -6
- package/dist/esm/peripherals/ssi.js +39 -39
- package/dist/esm/peripherals/syscfg.d.ts +5 -5
- package/dist/esm/peripherals/syscfg.js +22 -22
- package/dist/esm/peripherals/sysinfo.d.ts +4 -4
- package/dist/esm/peripherals/sysinfo.js +18 -18
- package/dist/esm/peripherals/tbman.d.ts +4 -4
- package/dist/esm/peripherals/tbman.js +13 -13
- package/dist/esm/peripherals/timer.d.ts +18 -18
- package/dist/esm/peripherals/timer.js +152 -152
- package/dist/esm/peripherals/uart.d.ts +31 -31
- package/dist/esm/peripherals/uart.js +128 -128
- package/dist/esm/peripherals/usb.d.ts +29 -29
- package/dist/esm/peripherals/usb.js +305 -305
- package/dist/esm/rp2040.d.ts +71 -71
- package/dist/esm/rp2040.js +357 -357
- package/dist/esm/sio.d.ts +21 -21
- package/dist/esm/sio.js +421 -421
- package/dist/esm/usb/cdc.d.ts +20 -20
- package/dist/esm/usb/cdc.js +121 -121
- package/dist/esm/usb/interfaces.d.ts +47 -47
- package/dist/esm/usb/interfaces.js +43 -43
- package/dist/esm/usb/setup.d.ts +5 -5
- package/dist/esm/usb/setup.js +46 -46
- package/dist/esm/utils/assembler.d.ts +79 -79
- package/dist/esm/utils/assembler.js +245 -245
- package/dist/esm/utils/bit.d.ts +3 -3
- package/dist/esm/utils/bit.js +9 -9
- package/dist/esm/utils/fifo.d.ts +15 -15
- package/dist/esm/utils/fifo.js +52 -52
- package/dist/esm/utils/logging.d.ts +23 -23
- package/dist/esm/utils/logging.js +44 -44
- package/dist/esm/utils/pio-assembler.d.ts +45 -45
- package/dist/esm/utils/pio-assembler.js +75 -75
- package/dist/esm/utils/time.d.ts +2 -2
- package/dist/esm/utils/time.js +27 -27
- package/dist/esm/utils/timer32.d.ts +57 -57
- package/dist/esm/utils/timer32.js +203 -203
- package/package.json +33 -22
- package/dist/esm/package.json +0 -1
|
@@ -1,257 +1,257 @@
|
|
|
1
|
-
import { IRQ } from '../irq';
|
|
2
|
-
import { FIFO } from '../utils/fifo';
|
|
3
|
-
import { DREQChannel } from './dma';
|
|
4
|
-
import { BasePeripheral } from './peripheral';
|
|
5
|
-
const CS = 0x00; // ADC Control and Status
|
|
6
|
-
const RESULT = 0x04; // Result of most recent ADC conversion
|
|
7
|
-
const FCS = 0x08; // FIFO control and status
|
|
8
|
-
const FIFO_REG = 0x0c; // Conversion result FIFO
|
|
9
|
-
const DIV = 0x10; // Clock divider.0x14 INTR Raw Interrupts
|
|
10
|
-
const INTR = 0x14; // Raw Interrupts
|
|
11
|
-
const INTE = 0x18; // Interrupt Enable
|
|
12
|
-
const INTF = 0x1c; // Interrupt Force
|
|
13
|
-
const INTS = 0x20; // Interrupt status after masking & forcing
|
|
14
|
-
// CS bits
|
|
15
|
-
const CS_RROBIN_MASK = 0x1f;
|
|
16
|
-
const CS_RROBIN_SHIFT = 16;
|
|
17
|
-
const CS_AINSEL_MASK = 0x7;
|
|
18
|
-
const CS_AINSEL_SHIFT = 12;
|
|
19
|
-
const CS_ERR_STICKY = 1 << 10;
|
|
20
|
-
const CS_ERR = 1 << 9;
|
|
21
|
-
const CS_READY = 1 << 8;
|
|
22
|
-
const CS_START_MANY = 1 << 3;
|
|
23
|
-
const CS_START_ONE = 1 << 2;
|
|
24
|
-
const CS_TS_EN = 1 << 1;
|
|
25
|
-
const CS_EN = 1 << 0;
|
|
26
|
-
const CS_WRITE_MASK = (CS_RROBIN_MASK << CS_RROBIN_SHIFT) |
|
|
27
|
-
(CS_AINSEL_MASK << CS_AINSEL_SHIFT) |
|
|
28
|
-
CS_START_MANY |
|
|
29
|
-
CS_START_ONE |
|
|
30
|
-
CS_TS_EN |
|
|
31
|
-
CS_EN;
|
|
32
|
-
// FCS bits
|
|
33
|
-
const FCS_THRES_MASK = 0xf;
|
|
34
|
-
const FCS_THRESH_SHIFT = 24;
|
|
35
|
-
const FCS_LEVEL_MASK = 0xf;
|
|
36
|
-
const FCS_LEVEL_SHIFT = 16;
|
|
37
|
-
const FCS_OVER = 1 << 11;
|
|
38
|
-
const FCS_UNDER = 1 << 10;
|
|
39
|
-
const FCS_FULL = 1 << 9;
|
|
40
|
-
const FCS_EMPTY = 1 << 8;
|
|
41
|
-
const FCS_DREQ_EN = 1 << 3;
|
|
42
|
-
const FCS_ERR = 1 << 2;
|
|
43
|
-
const FCS_SHIFT = 1 << 1;
|
|
44
|
-
const FCS_EN = 1 << 0;
|
|
45
|
-
const FCS_WRITE_MASK = (FCS_THRES_MASK << FCS_THRESH_SHIFT) | FCS_DREQ_EN | FCS_ERR | FCS_SHIFT | FCS_EN;
|
|
46
|
-
// FIFO_REG bits
|
|
47
|
-
const FIFO_ERR = 1 << 15;
|
|
48
|
-
// DIV bits
|
|
49
|
-
const DIV_INT_MASK = 0xffff;
|
|
50
|
-
const DIV_INT_SHIFT = 8;
|
|
51
|
-
const DIV_FRAC_MASK = 0xff;
|
|
52
|
-
const DIV_FRAC_SHIFT = 0;
|
|
53
|
-
// Interrupt bits
|
|
54
|
-
const FIFO_INT = 1 << 0;
|
|
55
|
-
export class RPADC extends BasePeripheral {
|
|
56
|
-
|
|
57
|
-
|
|
58
|
-
|
|
59
|
-
|
|
60
|
-
|
|
61
|
-
|
|
62
|
-
|
|
63
|
-
|
|
64
|
-
|
|
65
|
-
|
|
66
|
-
|
|
67
|
-
|
|
68
|
-
|
|
69
|
-
|
|
70
|
-
|
|
71
|
-
|
|
72
|
-
|
|
73
|
-
|
|
74
|
-
|
|
75
|
-
|
|
76
|
-
|
|
77
|
-
|
|
78
|
-
|
|
79
|
-
|
|
80
|
-
|
|
81
|
-
|
|
82
|
-
|
|
83
|
-
|
|
84
|
-
this.
|
|
85
|
-
|
|
86
|
-
|
|
87
|
-
|
|
88
|
-
this.
|
|
89
|
-
|
|
90
|
-
|
|
91
|
-
|
|
92
|
-
|
|
93
|
-
|
|
94
|
-
|
|
95
|
-
this.
|
|
96
|
-
|
|
97
|
-
|
|
98
|
-
|
|
99
|
-
|
|
100
|
-
|
|
101
|
-
|
|
102
|
-
|
|
103
|
-
|
|
104
|
-
|
|
105
|
-
|
|
106
|
-
|
|
107
|
-
|
|
108
|
-
|
|
109
|
-
|
|
110
|
-
|
|
111
|
-
|
|
112
|
-
|
|
113
|
-
|
|
114
|
-
|
|
115
|
-
|
|
116
|
-
|
|
117
|
-
|
|
118
|
-
|
|
119
|
-
this.
|
|
120
|
-
this.
|
|
121
|
-
}
|
|
122
|
-
checkInterrupts() {
|
|
123
|
-
this.rp2040.setInterrupt(IRQ.ADC_FIFO, !!this.intStatus);
|
|
124
|
-
}
|
|
125
|
-
startADCRead() {
|
|
126
|
-
this.busy = true;
|
|
127
|
-
this.onADCRead(this.activeChannel);
|
|
128
|
-
}
|
|
129
|
-
updateDMA() {
|
|
130
|
-
if (this.fcs & FCS_DREQ_EN) {
|
|
131
|
-
const thres = (this.fcs >> FCS_THRESH_SHIFT) & FCS_THRES_MASK;
|
|
132
|
-
if (this.fifo.itemCount >= thres) {
|
|
133
|
-
this.rp2040.dma.setDREQ(this.dreq);
|
|
134
|
-
}
|
|
135
|
-
else {
|
|
136
|
-
this.rp2040.dma.clearDREQ(this.dreq);
|
|
137
|
-
}
|
|
138
|
-
}
|
|
139
|
-
}
|
|
140
|
-
completeADCRead(value, error) {
|
|
141
|
-
this.busy = false;
|
|
142
|
-
this.result = value;
|
|
143
|
-
if (error) {
|
|
144
|
-
this.cs |= CS_ERR_STICKY | CS_ERR;
|
|
145
|
-
}
|
|
146
|
-
else {
|
|
147
|
-
this.cs &= ~CS_ERR;
|
|
148
|
-
}
|
|
149
|
-
// FIFO
|
|
150
|
-
if (this.fcs & FCS_EN) {
|
|
151
|
-
if (this.fifo.full) {
|
|
152
|
-
this.fcs |= FCS_OVER;
|
|
153
|
-
}
|
|
154
|
-
else {
|
|
155
|
-
value &= 0xfff; // 12 bits
|
|
156
|
-
if (this.fcs & FCS_SHIFT) {
|
|
157
|
-
value >>= 4;
|
|
158
|
-
}
|
|
159
|
-
if (error && this.fcs & FCS_ERR) {
|
|
160
|
-
value |= FIFO_ERR;
|
|
161
|
-
}
|
|
162
|
-
this.fifo.push(value);
|
|
163
|
-
this.updateDMA();
|
|
164
|
-
this.checkInterrupts();
|
|
165
|
-
}
|
|
166
|
-
}
|
|
167
|
-
// Round-robin
|
|
168
|
-
const round = (this.cs >> CS_RROBIN_SHIFT) & CS_RROBIN_MASK;
|
|
169
|
-
if (round) {
|
|
170
|
-
let channel = this.activeChannel + 1;
|
|
171
|
-
while (!(round & (1 << channel))) {
|
|
172
|
-
channel = (channel + 1) % this.numChannels;
|
|
173
|
-
}
|
|
174
|
-
this.activeChannel = channel;
|
|
175
|
-
}
|
|
176
|
-
// Multi-shot conversions
|
|
177
|
-
if (this.cs & CS_START_MANY) {
|
|
178
|
-
const clockMHZ = 48;
|
|
179
|
-
const sampleTicks = clockMHZ * this.sampleTime;
|
|
180
|
-
if (this.divider > sampleTicks) {
|
|
181
|
-
// clock runs at 48MHz, subtract 2uS
|
|
182
|
-
const micros = (this.divider - sampleTicks) / clockMHZ;
|
|
183
|
-
this.rp2040.clock.createTimer(micros, () => {
|
|
184
|
-
if (this.cs & CS_START_MANY) {
|
|
185
|
-
this.startADCRead();
|
|
186
|
-
}
|
|
187
|
-
});
|
|
188
|
-
}
|
|
189
|
-
else {
|
|
190
|
-
this.startADCRead();
|
|
191
|
-
}
|
|
192
|
-
}
|
|
193
|
-
}
|
|
194
|
-
readUint32(offset) {
|
|
195
|
-
switch (offset) {
|
|
196
|
-
case CS:
|
|
197
|
-
return this.cs | (this.err ? CS_ERR : 0) | (this.busy ? 0 : CS_READY);
|
|
198
|
-
case RESULT:
|
|
199
|
-
return this.result;
|
|
200
|
-
case FCS:
|
|
201
|
-
return (this.fcs |
|
|
202
|
-
((this.fifo.itemCount & FCS_LEVEL_MASK) << FCS_LEVEL_SHIFT) |
|
|
203
|
-
(this.fifo.full ? FCS_FULL : 0) |
|
|
204
|
-
(this.fifo.empty ? FCS_EMPTY : 0));
|
|
205
|
-
case FIFO_REG:
|
|
206
|
-
if (this.fifo.empty) {
|
|
207
|
-
this.fcs |= FCS_UNDER;
|
|
208
|
-
return 0;
|
|
209
|
-
}
|
|
210
|
-
else {
|
|
211
|
-
const value = this.fifo.pull();
|
|
212
|
-
this.updateDMA();
|
|
213
|
-
return value;
|
|
214
|
-
}
|
|
215
|
-
case DIV:
|
|
216
|
-
return this.clockDiv;
|
|
217
|
-
case INTR:
|
|
218
|
-
return this.intRaw;
|
|
219
|
-
case INTE:
|
|
220
|
-
return this.intEnable;
|
|
221
|
-
case INTF:
|
|
222
|
-
return this.intForce;
|
|
223
|
-
case INTS:
|
|
224
|
-
return this.intStatus;
|
|
225
|
-
}
|
|
226
|
-
return super.readUint32(offset);
|
|
227
|
-
}
|
|
228
|
-
writeUint32(offset, value) {
|
|
229
|
-
switch (offset) {
|
|
230
|
-
case CS:
|
|
231
|
-
this.fcs &= ~(value & CS_ERR_STICKY); // Write-clear bits
|
|
232
|
-
this.cs = (this.cs & ~CS_WRITE_MASK) | (value & CS_WRITE_MASK);
|
|
233
|
-
if (value & CS_EN && !this.busy && (value & CS_START_ONE || value & CS_START_MANY)) {
|
|
234
|
-
this.startADCRead();
|
|
235
|
-
}
|
|
236
|
-
break;
|
|
237
|
-
case FCS:
|
|
238
|
-
this.fcs &= ~(value & (FCS_OVER | FCS_UNDER)); // Write-clear bits
|
|
239
|
-
this.fcs = (this.fcs & ~FCS_WRITE_MASK) | (value & FCS_WRITE_MASK);
|
|
240
|
-
this.checkInterrupts();
|
|
241
|
-
break;
|
|
242
|
-
case DIV:
|
|
243
|
-
this.clockDiv = value;
|
|
244
|
-
break;
|
|
245
|
-
case INTE:
|
|
246
|
-
this.intEnable = value & FIFO_INT;
|
|
247
|
-
this.checkInterrupts();
|
|
248
|
-
break;
|
|
249
|
-
case INTF:
|
|
250
|
-
this.intForce = value & FIFO_INT;
|
|
251
|
-
this.checkInterrupts();
|
|
252
|
-
break;
|
|
253
|
-
default:
|
|
254
|
-
super.writeUint32(offset, value);
|
|
255
|
-
}
|
|
256
|
-
}
|
|
257
|
-
}
|
|
1
|
+
import { IRQ } from '../irq.js';
|
|
2
|
+
import { FIFO } from '../utils/fifo.js';
|
|
3
|
+
import { DREQChannel } from './dma.js';
|
|
4
|
+
import { BasePeripheral } from './peripheral.js';
|
|
5
|
+
const CS = 0x00; // ADC Control and Status
|
|
6
|
+
const RESULT = 0x04; // Result of most recent ADC conversion
|
|
7
|
+
const FCS = 0x08; // FIFO control and status
|
|
8
|
+
const FIFO_REG = 0x0c; // Conversion result FIFO
|
|
9
|
+
const DIV = 0x10; // Clock divider.0x14 INTR Raw Interrupts
|
|
10
|
+
const INTR = 0x14; // Raw Interrupts
|
|
11
|
+
const INTE = 0x18; // Interrupt Enable
|
|
12
|
+
const INTF = 0x1c; // Interrupt Force
|
|
13
|
+
const INTS = 0x20; // Interrupt status after masking & forcing
|
|
14
|
+
// CS bits
|
|
15
|
+
const CS_RROBIN_MASK = 0x1f;
|
|
16
|
+
const CS_RROBIN_SHIFT = 16;
|
|
17
|
+
const CS_AINSEL_MASK = 0x7;
|
|
18
|
+
const CS_AINSEL_SHIFT = 12;
|
|
19
|
+
const CS_ERR_STICKY = 1 << 10;
|
|
20
|
+
const CS_ERR = 1 << 9;
|
|
21
|
+
const CS_READY = 1 << 8;
|
|
22
|
+
const CS_START_MANY = 1 << 3;
|
|
23
|
+
const CS_START_ONE = 1 << 2;
|
|
24
|
+
const CS_TS_EN = 1 << 1;
|
|
25
|
+
const CS_EN = 1 << 0;
|
|
26
|
+
const CS_WRITE_MASK = (CS_RROBIN_MASK << CS_RROBIN_SHIFT) |
|
|
27
|
+
(CS_AINSEL_MASK << CS_AINSEL_SHIFT) |
|
|
28
|
+
CS_START_MANY |
|
|
29
|
+
CS_START_ONE |
|
|
30
|
+
CS_TS_EN |
|
|
31
|
+
CS_EN;
|
|
32
|
+
// FCS bits
|
|
33
|
+
const FCS_THRES_MASK = 0xf;
|
|
34
|
+
const FCS_THRESH_SHIFT = 24;
|
|
35
|
+
const FCS_LEVEL_MASK = 0xf;
|
|
36
|
+
const FCS_LEVEL_SHIFT = 16;
|
|
37
|
+
const FCS_OVER = 1 << 11;
|
|
38
|
+
const FCS_UNDER = 1 << 10;
|
|
39
|
+
const FCS_FULL = 1 << 9;
|
|
40
|
+
const FCS_EMPTY = 1 << 8;
|
|
41
|
+
const FCS_DREQ_EN = 1 << 3;
|
|
42
|
+
const FCS_ERR = 1 << 2;
|
|
43
|
+
const FCS_SHIFT = 1 << 1;
|
|
44
|
+
const FCS_EN = 1 << 0;
|
|
45
|
+
const FCS_WRITE_MASK = (FCS_THRES_MASK << FCS_THRESH_SHIFT) | FCS_DREQ_EN | FCS_ERR | FCS_SHIFT | FCS_EN;
|
|
46
|
+
// FIFO_REG bits
|
|
47
|
+
const FIFO_ERR = 1 << 15;
|
|
48
|
+
// DIV bits
|
|
49
|
+
const DIV_INT_MASK = 0xffff;
|
|
50
|
+
const DIV_INT_SHIFT = 8;
|
|
51
|
+
const DIV_FRAC_MASK = 0xff;
|
|
52
|
+
const DIV_FRAC_SHIFT = 0;
|
|
53
|
+
// Interrupt bits
|
|
54
|
+
const FIFO_INT = 1 << 0;
|
|
55
|
+
export class RPADC extends BasePeripheral {
|
|
56
|
+
get temperatueEnable() {
|
|
57
|
+
return this.cs & CS_TS_EN;
|
|
58
|
+
}
|
|
59
|
+
get enabled() {
|
|
60
|
+
return this.cs & CS_EN;
|
|
61
|
+
}
|
|
62
|
+
get divider() {
|
|
63
|
+
return (1 +
|
|
64
|
+
((this.clockDiv >> DIV_INT_SHIFT) & DIV_INT_MASK) +
|
|
65
|
+
((this.clockDiv >> DIV_FRAC_SHIFT) & DIV_FRAC_MASK) / 256);
|
|
66
|
+
}
|
|
67
|
+
get intRaw() {
|
|
68
|
+
const thres = (this.fcs >> FCS_THRESH_SHIFT) & FCS_THRES_MASK;
|
|
69
|
+
return this.fifo.itemCount >= thres ? FIFO_INT : 0;
|
|
70
|
+
}
|
|
71
|
+
get intStatus() {
|
|
72
|
+
return (this.intRaw & this.intEnable) | this.intForce;
|
|
73
|
+
}
|
|
74
|
+
get activeChannel() {
|
|
75
|
+
return (this.cs >> CS_AINSEL_SHIFT) & CS_AINSEL_MASK;
|
|
76
|
+
}
|
|
77
|
+
set activeChannel(channel) {
|
|
78
|
+
this.cs &= ~(CS_AINSEL_MASK << CS_AINSEL_SHIFT);
|
|
79
|
+
this.cs |= (channel & CS_AINSEL_SHIFT) << CS_AINSEL_SHIFT;
|
|
80
|
+
}
|
|
81
|
+
constructor(rp2040, name) {
|
|
82
|
+
super(rp2040, name);
|
|
83
|
+
/* Number of ADC channels */
|
|
84
|
+
this.numChannels = 5;
|
|
85
|
+
/** ADC resolution (in bits) */
|
|
86
|
+
this.resolution = 12;
|
|
87
|
+
/** Time to read a single sample, in microseconds */
|
|
88
|
+
this.sampleTime = 2;
|
|
89
|
+
/**
|
|
90
|
+
* ADC Channel values. Channels 0...3 are connected to GPIO 26...29, and channel 4 is connected to the built-in
|
|
91
|
+
* temperature sensor: T=27-(ADC_voltage-0.706)/0.001721.
|
|
92
|
+
*
|
|
93
|
+
* Changing the values will change the ADC reading, unless you override onADCRead() with a custom implementation.
|
|
94
|
+
*/
|
|
95
|
+
this.channelValues = [0, 0, 0, 0, 0];
|
|
96
|
+
/**
|
|
97
|
+
* Invoked whenever the emulated code performs an ADC read.
|
|
98
|
+
*
|
|
99
|
+
* The default implementation reads the result from the `channelValues` array, and then calls
|
|
100
|
+
* completeADCRead() after `sampleTime` milliseconds.
|
|
101
|
+
*
|
|
102
|
+
* If you override the default implementation, make sure to call `completeADCRead()` after
|
|
103
|
+
* `sampleTime` milliseconds (or else the ADC read will never complete).
|
|
104
|
+
*/
|
|
105
|
+
this.onADCRead = (channel) => {
|
|
106
|
+
// Default implementation
|
|
107
|
+
this.rp2040.clock.createTimer(this.sampleTime, () => this.completeADCRead(this.channelValues[channel], false));
|
|
108
|
+
};
|
|
109
|
+
this.fifo = new FIFO(4);
|
|
110
|
+
this.dreq = DREQChannel.DREQ_ADC;
|
|
111
|
+
// Registers
|
|
112
|
+
this.cs = 0;
|
|
113
|
+
this.fcs = 0;
|
|
114
|
+
this.clockDiv = 0;
|
|
115
|
+
this.intEnable = 0;
|
|
116
|
+
this.intForce = 0;
|
|
117
|
+
this.result = 0;
|
|
118
|
+
// Status
|
|
119
|
+
this.busy = false;
|
|
120
|
+
this.err = false;
|
|
121
|
+
}
|
|
122
|
+
checkInterrupts() {
|
|
123
|
+
this.rp2040.setInterrupt(IRQ.ADC_FIFO, !!this.intStatus);
|
|
124
|
+
}
|
|
125
|
+
startADCRead() {
|
|
126
|
+
this.busy = true;
|
|
127
|
+
this.onADCRead(this.activeChannel);
|
|
128
|
+
}
|
|
129
|
+
updateDMA() {
|
|
130
|
+
if (this.fcs & FCS_DREQ_EN) {
|
|
131
|
+
const thres = (this.fcs >> FCS_THRESH_SHIFT) & FCS_THRES_MASK;
|
|
132
|
+
if (this.fifo.itemCount >= thres) {
|
|
133
|
+
this.rp2040.dma.setDREQ(this.dreq);
|
|
134
|
+
}
|
|
135
|
+
else {
|
|
136
|
+
this.rp2040.dma.clearDREQ(this.dreq);
|
|
137
|
+
}
|
|
138
|
+
}
|
|
139
|
+
}
|
|
140
|
+
completeADCRead(value, error) {
|
|
141
|
+
this.busy = false;
|
|
142
|
+
this.result = value;
|
|
143
|
+
if (error) {
|
|
144
|
+
this.cs |= CS_ERR_STICKY | CS_ERR;
|
|
145
|
+
}
|
|
146
|
+
else {
|
|
147
|
+
this.cs &= ~CS_ERR;
|
|
148
|
+
}
|
|
149
|
+
// FIFO
|
|
150
|
+
if (this.fcs & FCS_EN) {
|
|
151
|
+
if (this.fifo.full) {
|
|
152
|
+
this.fcs |= FCS_OVER;
|
|
153
|
+
}
|
|
154
|
+
else {
|
|
155
|
+
value &= 0xfff; // 12 bits
|
|
156
|
+
if (this.fcs & FCS_SHIFT) {
|
|
157
|
+
value >>= 4;
|
|
158
|
+
}
|
|
159
|
+
if (error && this.fcs & FCS_ERR) {
|
|
160
|
+
value |= FIFO_ERR;
|
|
161
|
+
}
|
|
162
|
+
this.fifo.push(value);
|
|
163
|
+
this.updateDMA();
|
|
164
|
+
this.checkInterrupts();
|
|
165
|
+
}
|
|
166
|
+
}
|
|
167
|
+
// Round-robin
|
|
168
|
+
const round = (this.cs >> CS_RROBIN_SHIFT) & CS_RROBIN_MASK;
|
|
169
|
+
if (round) {
|
|
170
|
+
let channel = this.activeChannel + 1;
|
|
171
|
+
while (!(round & (1 << channel))) {
|
|
172
|
+
channel = (channel + 1) % this.numChannels;
|
|
173
|
+
}
|
|
174
|
+
this.activeChannel = channel;
|
|
175
|
+
}
|
|
176
|
+
// Multi-shot conversions
|
|
177
|
+
if (this.cs & CS_START_MANY) {
|
|
178
|
+
const clockMHZ = 48;
|
|
179
|
+
const sampleTicks = clockMHZ * this.sampleTime;
|
|
180
|
+
if (this.divider > sampleTicks) {
|
|
181
|
+
// clock runs at 48MHz, subtract 2uS
|
|
182
|
+
const micros = (this.divider - sampleTicks) / clockMHZ;
|
|
183
|
+
this.rp2040.clock.createTimer(micros, () => {
|
|
184
|
+
if (this.cs & CS_START_MANY) {
|
|
185
|
+
this.startADCRead();
|
|
186
|
+
}
|
|
187
|
+
});
|
|
188
|
+
}
|
|
189
|
+
else {
|
|
190
|
+
this.startADCRead();
|
|
191
|
+
}
|
|
192
|
+
}
|
|
193
|
+
}
|
|
194
|
+
readUint32(offset) {
|
|
195
|
+
switch (offset) {
|
|
196
|
+
case CS:
|
|
197
|
+
return this.cs | (this.err ? CS_ERR : 0) | (this.busy ? 0 : CS_READY);
|
|
198
|
+
case RESULT:
|
|
199
|
+
return this.result;
|
|
200
|
+
case FCS:
|
|
201
|
+
return (this.fcs |
|
|
202
|
+
((this.fifo.itemCount & FCS_LEVEL_MASK) << FCS_LEVEL_SHIFT) |
|
|
203
|
+
(this.fifo.full ? FCS_FULL : 0) |
|
|
204
|
+
(this.fifo.empty ? FCS_EMPTY : 0));
|
|
205
|
+
case FIFO_REG:
|
|
206
|
+
if (this.fifo.empty) {
|
|
207
|
+
this.fcs |= FCS_UNDER;
|
|
208
|
+
return 0;
|
|
209
|
+
}
|
|
210
|
+
else {
|
|
211
|
+
const value = this.fifo.pull();
|
|
212
|
+
this.updateDMA();
|
|
213
|
+
return value;
|
|
214
|
+
}
|
|
215
|
+
case DIV:
|
|
216
|
+
return this.clockDiv;
|
|
217
|
+
case INTR:
|
|
218
|
+
return this.intRaw;
|
|
219
|
+
case INTE:
|
|
220
|
+
return this.intEnable;
|
|
221
|
+
case INTF:
|
|
222
|
+
return this.intForce;
|
|
223
|
+
case INTS:
|
|
224
|
+
return this.intStatus;
|
|
225
|
+
}
|
|
226
|
+
return super.readUint32(offset);
|
|
227
|
+
}
|
|
228
|
+
writeUint32(offset, value) {
|
|
229
|
+
switch (offset) {
|
|
230
|
+
case CS:
|
|
231
|
+
this.fcs &= ~(value & CS_ERR_STICKY); // Write-clear bits
|
|
232
|
+
this.cs = (this.cs & ~CS_WRITE_MASK) | (value & CS_WRITE_MASK);
|
|
233
|
+
if (value & CS_EN && !this.busy && (value & CS_START_ONE || value & CS_START_MANY)) {
|
|
234
|
+
this.startADCRead();
|
|
235
|
+
}
|
|
236
|
+
break;
|
|
237
|
+
case FCS:
|
|
238
|
+
this.fcs &= ~(value & (FCS_OVER | FCS_UNDER)); // Write-clear bits
|
|
239
|
+
this.fcs = (this.fcs & ~FCS_WRITE_MASK) | (value & FCS_WRITE_MASK);
|
|
240
|
+
this.checkInterrupts();
|
|
241
|
+
break;
|
|
242
|
+
case DIV:
|
|
243
|
+
this.clockDiv = value;
|
|
244
|
+
break;
|
|
245
|
+
case INTE:
|
|
246
|
+
this.intEnable = value & FIFO_INT;
|
|
247
|
+
this.checkInterrupts();
|
|
248
|
+
break;
|
|
249
|
+
case INTF:
|
|
250
|
+
this.intForce = value & FIFO_INT;
|
|
251
|
+
this.checkInterrupts();
|
|
252
|
+
break;
|
|
253
|
+
default:
|
|
254
|
+
super.writeUint32(offset, value);
|
|
255
|
+
}
|
|
256
|
+
}
|
|
257
|
+
}
|
|
@@ -1,10 +1,10 @@
|
|
|
1
|
-
import { RP2040 } from '../rp2040';
|
|
2
|
-
import { BasePeripheral, Peripheral } from './peripheral';
|
|
3
|
-
export declare class RPBUSCTRL extends BasePeripheral implements Peripheral {
|
|
4
|
-
voltageSelect: number;
|
|
5
|
-
readonly perfCtr: number[];
|
|
6
|
-
readonly perfSel: number[];
|
|
7
|
-
constructor(rp2040: RP2040, name: string);
|
|
8
|
-
readUint32(offset: number): number;
|
|
9
|
-
writeUint32(offset: number, value: number): void;
|
|
10
|
-
}
|
|
1
|
+
import { RP2040 } from '../rp2040.js';
|
|
2
|
+
import { BasePeripheral, Peripheral } from './peripheral.js';
|
|
3
|
+
export declare class RPBUSCTRL extends BasePeripheral implements Peripheral {
|
|
4
|
+
voltageSelect: number;
|
|
5
|
+
readonly perfCtr: number[];
|
|
6
|
+
readonly perfSel: number[];
|
|
7
|
+
constructor(rp2040: RP2040, name: string);
|
|
8
|
+
readUint32(offset: number): number;
|
|
9
|
+
writeUint32(offset: number, value: number): void;
|
|
10
|
+
}
|