rp2040js 0.17.17 → 0.18.0

package/dist/cjs/peripherals/spi.js

@@ -1,240 +1,240 @@
-"use strict";
-Object.defineProperty(exports, "__esModule", { value: true });
-exports.RPSPI = void 0;
-const fifo_1 = require("../utils/fifo");
-const peripheral_1 = require("./peripheral");
-const SSPCR0 = 0x000; // Control register 0, SSPCR0 on page 3-4
-const SSPCR1 = 0x004; // Control register 1, SSPCR1 on page 3-5
-const SSPDR = 0x008; // Data register, SSPDR on page 3-6
-const SSPSR = 0x00c; // Status register, SSPSR on page 3-7
-const SSPCPSR = 0x010; // Clock prescale register, SSPCPSR on page 3-8
-const SSPIMSC = 0x014; // Interrupt mask set or clear register, SSPIMSC on page 3-9
-const SSPRIS = 0x018; // Raw interrupt status register, SSPRIS on page 3-10
-const SSPMIS = 0x01c; // Masked interrupt status register, SSPMIS on page 3-11
-const SSPICR = 0x020; // Interrupt clear register, SSPICR on page 3-11
-const SSPDMACR = 0x024; // DMA control register, SSPDMACR on page 3-12
-const SSPPERIPHID0 = 0xfe0; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-const SSPPERIPHID1 = 0xfe4; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-const SSPPERIPHID2 = 0xfe8; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-const SSPPERIPHID3 = 0xfec; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-const SSPPCELLID0 = 0xff0; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-const SSPPCELLID1 = 0xff4; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-const SSPPCELLID2 = 0xff8; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-const SSPPCELLID3 = 0xffc; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-// SSPCR0 bits:
-const SCR_MASK = 0xff;
-const SCR_SHIFT = 8;
-const SPH = 1 << 7;
-const SPO = 1 << 6;
-const FRF_MASK = 0x3;
-const FRF_SHIFT = 4;
-const DSS_MASK = 0xf;
-const DSS_SHIFT = 0;
-// SSPCR1 bits:
-const SOD = 1 << 3;
-const MS = 1 << 2;
-const SSE = 1 << 1;
-const LBM = 1 << 0;
-// SSPSR bits:
-const BSY = 1 << 4;
-const RFF = 1 << 3;
-const RNE = 1 << 2;
-const TNF = 1 << 1;
-const TFE = 1 << 0;
-// SSPCPSR bits:
-const CPSDVSR_MASK = 0xfe;
-const CPSDVSR_SHIFT = 0;
-// SSPDMACR bits:
-const TXDMAE = 1 << 1;
-const RXDMAE = 1 << 0;
-// Interrupts:
-const SSPTXINTR = 1 << 3;
-const SSPRXINTR = 1 << 2;
-const SSPRTINTR = 1 << 1;
-const SSPRORINTR = 1 << 0;
-class RPSPI extends peripheral_1.BasePeripheral {
-    constructor(rp2040, name, irq, dreq) {
-        super(rp2040, name);
-        this.irq = irq;
-        this.dreq = dreq;
-        this.rxFIFO = new fifo_1.FIFO(8);
-        this.txFIFO = new fifo_1.FIFO(8);
-        // User provided callbacks
-        this.onTransmit = () => this.completeTransmit(0);
-        this.busy = false;
-        this.control0 = 0;
-        this.control1 = 0;
-        this.dmaControl = 0;
-        this.clockDivisor = 0;
-        this.intRaw = 0;
-        this.intEnable = 0;
-        this.updateDMATx();
-        this.updateDMARx();
-    }
-    get intStatus() {
-        return this.intRaw & this.intEnable;
-    }
-    get enabled() {
-        return !!(this.control1 & SSE);
-    }
-    /** Data size in bits: 4 to 16 bits */
-    get dataBits() {
-        return ((this.control0 >> DSS_SHIFT) & DSS_MASK) + 1;
-    }
-    get masterMode() {
-        return !(this.control0 & MS);
-    }
-    get spiMode() {
-        const cpol = this.control0 & SPO;
-        const cpha = this.control0 & SPH;
-        return cpol ? (cpha ? 2 : 3) : cpha ? 1 : 0;
-    }
-    get clockFrequency() {
-        if (!this.clockDivisor) {
-            return 0;
-        }
-        const scr = (this.control0 >> SCR_SHIFT) & SCR_MASK;
-        return this.rp2040.clkPeri / (this.clockDivisor * (1 + scr));
-    }
-    updateDMATx() {
-        if (this.txFIFO.full) {
-            this.rp2040.dma.clearDREQ(this.dreq.tx);
-        }
-        else {
-            this.rp2040.dma.setDREQ(this.dreq.tx);
-        }
-    }
-    updateDMARx() {
-        if (this.rxFIFO.empty) {
-            this.rp2040.dma.clearDREQ(this.dreq.rx);
-        }
-        else {
-            this.rp2040.dma.setDREQ(this.dreq.rx);
-        }
-    }
-    doTX() {
-        if (!this.busy && !this.txFIFO.empty) {
-            const value = this.txFIFO.pull();
-            this.busy = true;
-            this.onTransmit(value);
-            this.fifosUpdated();
-        }
-    }
-    completeTransmit(rxValue) {
-        this.busy = false;
-        if (!this.rxFIFO.full) {
-            this.rxFIFO.push(rxValue);
-        }
-        else {
-            this.intRaw |= SSPRORINTR;
-        }
-        this.fifosUpdated();
-        this.doTX();
-    }
-    checkInterrupts() {
-        this.rp2040.setInterrupt(this.irq, !!this.intStatus);
-    }
-    fifosUpdated() {
-        const prevStatus = this.intStatus;
-        if (this.txFIFO.itemCount <= this.txFIFO.size / 2) {
-            this.intRaw |= SSPTXINTR;
-        }
-        else {
-            this.intRaw &= ~SSPTXINTR;
-        }
-        if (this.rxFIFO.itemCount >= this.rxFIFO.size / 2) {
-            this.intRaw |= SSPRXINTR;
-        }
-        else {
-            this.intRaw &= ~SSPRXINTR;
-        }
-        if (this.intStatus !== prevStatus) {
-            this.checkInterrupts();
-        }
-        this.updateDMATx();
-        this.updateDMARx();
-    }
-    readUint32(offset) {
-        switch (offset) {
-            case SSPCR0:
-                return this.control0;
-            case SSPCR1:
-                return this.control1;
-            case SSPDR:
-                if (!this.rxFIFO.empty) {
-                    const value = this.rxFIFO.pull();
-                    this.fifosUpdated();
-                    return value;
-                }
-                return 0;
-            case SSPSR:
-                return ((this.busy || !this.txFIFO.empty ? BSY : 0) |
-                    (this.rxFIFO.full ? RFF : 0) |
-                    (!this.rxFIFO.empty ? RNE : 0) |
-                    (!this.txFIFO.full ? TNF : 0) |
-                    (this.txFIFO.empty ? TFE : 0));
-            case SSPCPSR:
-                return this.clockDivisor;
-            case SSPIMSC:
-                return this.intEnable;
-            case SSPRIS:
-                return this.intRaw;
-            case SSPMIS:
-                return this.intStatus;
-            case SSPDMACR:
-                return this.dmaControl;
-            case SSPPERIPHID0:
-                return 0x22;
-            case SSPPERIPHID1:
-                return 0x10;
-            case SSPPERIPHID2:
-                return 0x34;
-            case SSPPERIPHID3:
-                return 0x00;
-            case SSPPCELLID0:
-                return 0x0d;
-            case SSPPCELLID1:
-                return 0xf0;
-            case SSPPCELLID2:
-                return 0x05;
-            case SSPPCELLID3:
-                return 0xb1;
-        }
-        return super.readUint32(offset);
-    }
-    writeUint32(offset, value) {
-        switch (offset) {
-            case SSPCR0:
-                this.control0 = value;
-                return;
-            case SSPCR1:
-                this.control1 = value;
-                return;
-            case SSPDR:
-                if (!this.txFIFO.full) {
-                    // decoded with respect to SSPCR0.DSS
-                    this.txFIFO.push(value & ((1 << this.dataBits) - 1));
-                    this.doTX();
-                    this.fifosUpdated();
-                }
-                return;
-            case SSPCPSR:
-                this.clockDivisor = value & CPSDVSR_MASK;
-                return;
-            case SSPIMSC:
-                this.intEnable = value;
-                this.checkInterrupts();
-                return;
-            case SSPDMACR:
-                this.dmaControl = value;
-                return;
-            case SSPICR:
-                this.intRaw &= ~(value & (SSPRTINTR | SSPRORINTR));
-                this.checkInterrupts();
-                return;
-            default:
-                super.writeUint32(offset, value);
-        }
-    }
-}
-exports.RPSPI = RPSPI;
+"use strict";
+Object.defineProperty(exports, "__esModule", { value: true });
+exports.RPSPI = void 0;
+const fifo_js_1 = require("../utils/fifo.js");
+const peripheral_js_1 = require("./peripheral.js");
+const SSPCR0 = 0x000; // Control register 0, SSPCR0 on page 3-4
+const SSPCR1 = 0x004; // Control register 1, SSPCR1 on page 3-5
+const SSPDR = 0x008; // Data register, SSPDR on page 3-6
+const SSPSR = 0x00c; // Status register, SSPSR on page 3-7
+const SSPCPSR = 0x010; // Clock prescale register, SSPCPSR on page 3-8
+const SSPIMSC = 0x014; // Interrupt mask set or clear register, SSPIMSC on page 3-9
+const SSPRIS = 0x018; // Raw interrupt status register, SSPRIS on page 3-10
+const SSPMIS = 0x01c; // Masked interrupt status register, SSPMIS on page 3-11
+const SSPICR = 0x020; // Interrupt clear register, SSPICR on page 3-11
+const SSPDMACR = 0x024; // DMA control register, SSPDMACR on page 3-12
+const SSPPERIPHID0 = 0xfe0; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+const SSPPERIPHID1 = 0xfe4; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+const SSPPERIPHID2 = 0xfe8; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+const SSPPERIPHID3 = 0xfec; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+const SSPPCELLID0 = 0xff0; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+const SSPPCELLID1 = 0xff4; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+const SSPPCELLID2 = 0xff8; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+const SSPPCELLID3 = 0xffc; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+// SSPCR0 bits:
+const SCR_MASK = 0xff;
+const SCR_SHIFT = 8;
+const SPH = 1 << 7;
+const SPO = 1 << 6;
+const FRF_MASK = 0x3;
+const FRF_SHIFT = 4;
+const DSS_MASK = 0xf;
+const DSS_SHIFT = 0;
+// SSPCR1 bits:
+const SOD = 1 << 3;
+const MS = 1 << 2;
+const SSE = 1 << 1;
+const LBM = 1 << 0;
+// SSPSR bits:
+const BSY = 1 << 4;
+const RFF = 1 << 3;
+const RNE = 1 << 2;
+const TNF = 1 << 1;
+const TFE = 1 << 0;
+// SSPCPSR bits:
+const CPSDVSR_MASK = 0xfe;
+const CPSDVSR_SHIFT = 0;
+// SSPDMACR bits:
+const TXDMAE = 1 << 1;
+const RXDMAE = 1 << 0;
+// Interrupts:
+const SSPTXINTR = 1 << 3;
+const SSPRXINTR = 1 << 2;
+const SSPRTINTR = 1 << 1;
+const SSPRORINTR = 1 << 0;
+class RPSPI extends peripheral_js_1.BasePeripheral {
+    get intStatus() {
+        return this.intRaw & this.intEnable;
+    }
+    get enabled() {
+        return !!(this.control1 & SSE);
+    }
+    /** Data size in bits: 4 to 16 bits */
+    get dataBits() {
+        return ((this.control0 >> DSS_SHIFT) & DSS_MASK) + 1;
+    }
+    get masterMode() {
+        return !(this.control0 & MS);
+    }
+    get spiMode() {
+        const cpol = this.control0 & SPO;
+        const cpha = this.control0 & SPH;
+        return cpol ? (cpha ? 2 : 3) : cpha ? 1 : 0;
+    }
+    get clockFrequency() {
+        if (!this.clockDivisor) {
+            return 0;
+        }
+        const scr = (this.control0 >> SCR_SHIFT) & SCR_MASK;
+        return this.rp2040.clkPeri / (this.clockDivisor * (1 + scr));
+    }
+    updateDMATx() {
+        if (this.txFIFO.full) {
+            this.rp2040.dma.clearDREQ(this.dreq.tx);
+        }
+        else {
+            this.rp2040.dma.setDREQ(this.dreq.tx);
+        }
+    }
+    updateDMARx() {
+        if (this.rxFIFO.empty) {
+            this.rp2040.dma.clearDREQ(this.dreq.rx);
+        }
+        else {
+            this.rp2040.dma.setDREQ(this.dreq.rx);
+        }
+    }
+    constructor(rp2040, name, irq, dreq) {
+        super(rp2040, name);
+        this.irq = irq;
+        this.dreq = dreq;
+        this.rxFIFO = new fifo_js_1.FIFO(8);
+        this.txFIFO = new fifo_js_1.FIFO(8);
+        // User provided callbacks
+        this.onTransmit = () => this.completeTransmit(0);
+        this.busy = false;
+        this.control0 = 0;
+        this.control1 = 0;
+        this.dmaControl = 0;
+        this.clockDivisor = 0;
+        this.intRaw = 0;
+        this.intEnable = 0;
+        this.updateDMATx();
+        this.updateDMARx();
+    }
+    doTX() {
+        if (!this.busy && !this.txFIFO.empty) {
+            const value = this.txFIFO.pull();
+            this.busy = true;
+            this.onTransmit(value);
+            this.fifosUpdated();
+        }
+    }
+    completeTransmit(rxValue) {
+        this.busy = false;
+        if (!this.rxFIFO.full) {
+            this.rxFIFO.push(rxValue);
+        }
+        else {
+            this.intRaw |= SSPRORINTR;
+        }
+        this.fifosUpdated();
+        this.doTX();
+    }
+    checkInterrupts() {
+        this.rp2040.setInterrupt(this.irq, !!this.intStatus);
+    }
+    fifosUpdated() {
+        const prevStatus = this.intStatus;
+        if (this.txFIFO.itemCount <= this.txFIFO.size / 2) {
+            this.intRaw |= SSPTXINTR;
+        }
+        else {
+            this.intRaw &= ~SSPTXINTR;
+        }
+        if (this.rxFIFO.itemCount >= this.rxFIFO.size / 2) {
+            this.intRaw |= SSPRXINTR;
+        }
+        else {
+            this.intRaw &= ~SSPRXINTR;
+        }
+        if (this.intStatus !== prevStatus) {
+            this.checkInterrupts();
+        }
+        this.updateDMATx();
+        this.updateDMARx();
+    }
+    readUint32(offset) {
+        switch (offset) {
+            case SSPCR0:
+                return this.control0;
+            case SSPCR1:
+                return this.control1;
+            case SSPDR:
+                if (!this.rxFIFO.empty) {
+                    const value = this.rxFIFO.pull();
+                    this.fifosUpdated();
+                    return value;
+                }
+                return 0;
+            case SSPSR:
+                return ((this.busy || !this.txFIFO.empty ? BSY : 0) |
+                    (this.rxFIFO.full ? RFF : 0) |
+                    (!this.rxFIFO.empty ? RNE : 0) |
+                    (!this.txFIFO.full ? TNF : 0) |
+                    (this.txFIFO.empty ? TFE : 0));
+            case SSPCPSR:
+                return this.clockDivisor;
+            case SSPIMSC:
+                return this.intEnable;
+            case SSPRIS:
+                return this.intRaw;
+            case SSPMIS:
+                return this.intStatus;
+            case SSPDMACR:
+                return this.dmaControl;
+            case SSPPERIPHID0:
+                return 0x22;
+            case SSPPERIPHID1:
+                return 0x10;
+            case SSPPERIPHID2:
+                return 0x34;
+            case SSPPERIPHID3:
+                return 0x00;
+            case SSPPCELLID0:
+                return 0x0d;
+            case SSPPCELLID1:
+                return 0xf0;
+            case SSPPCELLID2:
+                return 0x05;
+            case SSPPCELLID3:
+                return 0xb1;
+        }
+        return super.readUint32(offset);
+    }
+    writeUint32(offset, value) {
+        switch (offset) {
+            case SSPCR0:
+                this.control0 = value;
+                return;
+            case SSPCR1:
+                this.control1 = value;
+                return;
+            case SSPDR:
+                if (!this.txFIFO.full) {
+                    // decoded with respect to SSPCR0.DSS
+                    this.txFIFO.push(value & ((1 << this.dataBits) - 1));
+                    this.doTX();
+                    this.fifosUpdated();
+                }
+                return;
+            case SSPCPSR:
+                this.clockDivisor = value & CPSDVSR_MASK;
+                return;
+            case SSPIMSC:
+                this.intEnable = value;
+                this.checkInterrupts();
+                return;
+            case SSPDMACR:
+                this.dmaControl = value;
+                return;
+            case SSPICR:
+                this.intRaw &= ~(value & (SSPRTINTR | SSPRORINTR));
+                this.checkInterrupts();
+                return;
+            default:
+                super.writeUint32(offset, value);
+        }
+    }
+}
+exports.RPSPI = RPSPI;

package/dist/cjs/peripherals/ssi.d.ts

@@ -1,6 +1,6 @@
-import { BasePeripheral, Peripheral } from './peripheral';
-export declare class RPSSI extends BasePeripheral implements Peripheral {
-    private dr0;
-    readUint32(offset: number): number;
-    writeUint32(offset: number, value: number): void;
-}
+import { BasePeripheral, Peripheral } from './peripheral.js';
+export declare class RPSSI extends BasePeripheral implements Peripheral {
+    private dr0;
+    readUint32(offset: number): number;
+    writeUint32(offset: number, value: number): void;
+}

package/dist/cjs/peripherals/ssi.js

@@ -1,43 +1,43 @@
-"use strict";
-Object.defineProperty(exports, "__esModule", { value: true });
-exports.RPSSI = void 0;
-const peripheral_1 = require("./peripheral");
-const SSI_TXFLR = 0x00000020;
-const SSI_RXFLR = 0x00000024;
-const SSI_SR = 0x00000028;
-const SSI_DR0 = 0x00000060;
-const SSI_SR_TFNF_BITS = 0x00000002;
-const SSI_SR_TFE_BITS = 0x00000004;
-const SSI_SR_RFNE_BITS = 0x00000008;
-const CMD_READ_STATUS = 0x05;
-class RPSSI extends peripheral_1.BasePeripheral {
-    constructor() {
-        super(...arguments);
-        this.dr0 = 0;
-    }
-    readUint32(offset) {
-        switch (offset) {
-            case SSI_TXFLR:
-                return 0;
-            case SSI_RXFLR:
-                return 0;
-            case SSI_SR:
-                return SSI_SR_TFE_BITS | SSI_SR_RFNE_BITS | SSI_SR_TFNF_BITS;
-            case SSI_DR0:
-                return this.dr0;
-        }
-        return super.readUint32(offset);
-    }
-    writeUint32(offset, value) {
-        switch (offset) {
-            case SSI_DR0:
-                if (value === CMD_READ_STATUS) {
-                    this.dr0 = 0; // tell stage2 that we completed a write
-                }
-                return;
-            default:
-                super.writeUint32(offset, value);
-        }
-    }
-}
-exports.RPSSI = RPSSI;
+"use strict";
+Object.defineProperty(exports, "__esModule", { value: true });
+exports.RPSSI = void 0;
+const peripheral_js_1 = require("./peripheral.js");
+const SSI_TXFLR = 0x00000020;
+const SSI_RXFLR = 0x00000024;
+const SSI_SR = 0x00000028;
+const SSI_DR0 = 0x00000060;
+const SSI_SR_TFNF_BITS = 0x00000002;
+const SSI_SR_TFE_BITS = 0x00000004;
+const SSI_SR_RFNE_BITS = 0x00000008;
+const CMD_READ_STATUS = 0x05;
+class RPSSI extends peripheral_js_1.BasePeripheral {
+    constructor() {
+        super(...arguments);
+        this.dr0 = 0;
+    }
+    readUint32(offset) {
+        switch (offset) {
+            case SSI_TXFLR:
+                return 0;
+            case SSI_RXFLR:
+                return 0;
+            case SSI_SR:
+                return SSI_SR_TFE_BITS | SSI_SR_RFNE_BITS | SSI_SR_TFNF_BITS;
+            case SSI_DR0:
+                return this.dr0;
+        }
+        return super.readUint32(offset);
+    }
+    writeUint32(offset, value) {
+        switch (offset) {
+            case SSI_DR0:
+                if (value === CMD_READ_STATUS) {
+                    this.dr0 = 0; // tell stage2 that we completed a write
+                }
+                return;
+            default:
+                super.writeUint32(offset, value);
+        }
+    }
+}
+exports.RPSSI = RPSSI;

package/dist/cjs/peripherals/syscfg.d.ts

@@ -1,5 +1,5 @@
-import { BasePeripheral, Peripheral } from './peripheral';
-export declare class RP2040SysCfg extends BasePeripheral implements Peripheral {
-    readUint32(offset: number): number;
-    writeUint32(offset: number, value: number): void;
-}
+import { BasePeripheral, Peripheral } from './peripheral.js';
+export declare class RP2040SysCfg extends BasePeripheral implements Peripheral {
+    readUint32(offset: number): number;
+    writeUint32(offset: number, value: number): void;
+}

package/dist/cjs/peripherals/syscfg.js

@@ -1,26 +1,26 @@
-"use strict";
-Object.defineProperty(exports, "__esModule", { value: true });
-exports.RP2040SysCfg = void 0;
-const peripheral_1 = require("./peripheral");
-const PROC0_NMI_MASK = 0;
-// eslint-disable-next-line @typescript-eslint/no-unused-vars
-const PROC1_NMI_MASK = 4;
-class RP2040SysCfg extends peripheral_1.BasePeripheral {
-    readUint32(offset) {
-        switch (offset) {
-            case PROC0_NMI_MASK:
-                return this.rp2040.core.interruptNMIMask;
-        }
-        return super.readUint32(offset);
-    }
-    writeUint32(offset, value) {
-        switch (offset) {
-            case PROC0_NMI_MASK:
-                this.rp2040.core.interruptNMIMask = value;
-                break;
-            default:
-                super.writeUint32(offset, value);
-        }
-    }
-}
-exports.RP2040SysCfg = RP2040SysCfg;
+"use strict";
+Object.defineProperty(exports, "__esModule", { value: true });
+exports.RP2040SysCfg = void 0;
+const peripheral_js_1 = require("./peripheral.js");
+const PROC0_NMI_MASK = 0;
+// eslint-disable-next-line @typescript-eslint/no-unused-vars
+const PROC1_NMI_MASK = 4;
+class RP2040SysCfg extends peripheral_js_1.BasePeripheral {
+    readUint32(offset) {
+        switch (offset) {
+            case PROC0_NMI_MASK:
+                return this.rp2040.core.interruptNMIMask;
+        }
+        return super.readUint32(offset);
+    }
+    writeUint32(offset, value) {
+        switch (offset) {
+            case PROC0_NMI_MASK:
+                this.rp2040.core.interruptNMIMask = value;
+                break;
+            default:
+                super.writeUint32(offset, value);
+        }
+    }
+}
+exports.RP2040SysCfg = RP2040SysCfg;

package/dist/cjs/peripherals/sysinfo.d.ts

@@ -1,4 +1,4 @@
-import { BasePeripheral, Peripheral } from './peripheral';
-export declare class RP2040SysInfo extends BasePeripheral implements Peripheral {
-    readUint32(offset: number): number;
-}
+import { BasePeripheral, Peripheral } from './peripheral.js';
+export declare class RP2040SysInfo extends BasePeripheral implements Peripheral {
+    readUint32(offset: number): number;
+}