ming_node 3.0.2 → 3.0.5

package/output/npr/npr_plugins/verilog/uart/top_UART_TX.v

@@ -0,0 +1,41 @@
+`timescale 1ns / 1ns
+
+module top_UART_TX
+(
+    input	      sys_clk,                  //系统时钟
+    input         sys_rst_n,                //系统复位，低电平有效
+    output      txd
+ );
+
+//wire define
+
+wire [7:0] data_inline;              //UART接收数据
+wire       uart_send_en;                //UART发送使能
+
+
+wire       uart_recv_done;              //UART接收完成
+
+wire [7:0] uart_send_data;              //UART发送数据
+wire       uart_tx_busy;                //UART发送忙状态标志
+
+uart_tx#(.UART_BPS(960000)) u_uart_transmit
+(
+    .sys_clk (sys_clk),                   //系统时钟
+    .sys_rst_n  (sys_rst_n),                //系统复位，低电平有效
+    .uart_en (uart_send_en),                  //发送使能信号
+    .uart_din (data_inline),                 //待发送数据
+    .uart_txd (txd)                  //UART发送端口
+ );
+
+
+
+
+ uart_tx_count#(.COUNT_200(3000)) u_uart_tx_count
+ (
+        .sys_clk (sys_clk),
+        .sys_rst_n (sys_rst_n),
+        .enable_txd (uart_send_en),  //允许串口发送
+        .data  (data_inline)
+ );
+
+endmodule

package/output/npr/npr_plugins/verilog/uart/uart_rx.v

@@ -0,0 +1,148 @@
+`timescale 1ns / 1ns
+/***************************************************************
+ * Copyright(C), 2022 蓝萌电子 All Rights Reserved.
+ * ModuleName : uart_rx.v
+ * Date       : 2022年6月9日
+ * Time       : 0:28:11
+ * Author     : 沈玲玲
+ * Version    : V1.0
+ *      Version | Modify
+ *      ----------------------------------
+ *       v1.0    .....
+ *   * Copyright: 2022 蓝萌电子 All Rights Reserved.
+ *   *
+ *   * This software is licensed under terms that can be found in the LICENSE file
+ *   * in the root directory of this software component.
+ *   * If no LICENSE file comes with this software, it is provided GPL3.0.
+ *   *
+ *   * Description:
+ ***************************************************************/
+
+
+
+module  uart_rx
+#(
+	parameter CLK_FREQ = 50000000,
+	parameter UART_BPS = 9600
+)
+(
+    input sys_clk,
+    input sys_rst_n,
+    input uart_rxd,
+    output reg uart_done,
+    output reg [7:0] uart_data
+);
+
+localparam BPS_CNT = CLK_FREQ/UART_BPS;
+//reg define
+reg uart_rxd_d0;
+reg uart_rxd_d1;
+reg [15:0] clk_cnt;
+reg [3:0] rx_cnt;
+reg rx_flag;
+reg [7:0] rxdata;
+
+//wire define
+wire start_flag;
+
+/**
+  *  Main Code
+  *  主要运行代码
+ **/
+//捕获下降沿
+assign start_flag = uart_rxd_d1&(~uart_rxd_d0);
+//对UART接收端口数据延时两个周期
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n) begin
+	uart_rxd_d0 <= 1'b0;
+	uart_rxd_d1 <= 1'b0;
+    end
+    else begin
+	uart_rxd_d0 <= uart_rxd;
+	uart_rxd_d1 <= uart_rxd_d0;
+    end
+end
+//检测脉冲信号srart_flag  进入接受过程
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n)
+		rx_flag <= 1'b0;
+    else  begin
+        if(start_flag)
+            rx_flag <= 1'b1;
+        else if((rx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2))
+            rx_flag <= 1'b0;
+        else
+            rx_flag <= rx_flag;
+    end
+end
+//进入接受过程，启动系统时钟计数器
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n) begin
+        clk_cnt <= 16'd0;
+    end
+    else if(rx_flag) begin
+        if(clk_cnt < BPS_CNT -1)
+            clk_cnt <= clk_cnt +1'b1;
+        else
+            clk_cnt <= 16'd0;
+        end
+    else
+        clk_cnt <= 16'd0;
+end
+
+//进入接受过程，启动接收数据计数器
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n) begin
+        rx_cnt <= 4'd0;
+    end
+    else if(rx_flag) begin
+        if(clk_cnt < BPS_CNT -1)
+            rx_cnt <= rx_cnt +1'b1;
+        else
+            rx_cnt <= rx_cnt;
+    end
+    else
+        rx_cnt <= 4'd0;
+end
+
+//根据接收数据计数器来寄存uart接收端口数据
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if ( !sys_rst_n)
+        rxdata <= 8'd0;
+    else if(rx_flag)                            //系统处于接收过程
+        if (clk_cnt == BPS_CNT/2) begin         //判断系统时钟计数器计数到数据位中间
+            case ( rx_cnt )
+             4'd1 : rxdata[0] <= uart_rxd_d1;   //寄存数据位最低位
+             4'd2 : rxdata[1] <= uart_rxd_d1;
+             4'd3 : rxdata[2] <= uart_rxd_d1;
+             4'd4 : rxdata[3] <= uart_rxd_d1;
+             4'd5 : rxdata[4] <= uart_rxd_d1;
+             4'd6 : rxdata[5] <= uart_rxd_d1;
+             4'd7 : rxdata[6] <= uart_rxd_d1;
+             4'd8 : rxdata[7] <= uart_rxd_d1;   //寄存数据位最高位
+             default:;
+            endcase
+        end
+        else
+            rxdata <= rxdata;
+    else
+        rxdata <= 8'd0;
+end
+
+//数据接收完毕后给出标志信号并寄存输出接收到的数据
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if (!sys_rst_n) begin
+        uart_data <= 8'd0;
+        uart_done <= 1'b0;
+    end
+    else if(rx_cnt == 4'd9) begin               //接收数据计数器计数到停止位时
+        uart_data <= rxdata;                    //寄存输出接收到的数据
+        uart_done <= 1'b1;                      //并将接收完成标志位拉高
+    end
+    else begin
+        uart_data <= uart_data;
+        uart_done <= 1'b0;
+    end
+end
+
+endmodule

package/output/npr/npr_plugins/verilog/uart/uart_rx_led.v

@@ -0,0 +1,23 @@
+`timescale 1ns / 1ns
+
+
+module uart_rx_led
+(
+    input [7:0]      input_led,
+    output reg [7:0] output_led,
+    input sys_clk,
+    input sys_rst_n
+);
+
+
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n) begin
+        output_led  <= 8'b1111_1111;
+    end
+    else  begin
+        output_led <=  ~input_led;
+    end
+end
+
+
+endmodule

package/output/npr/npr_plugins/verilog/uart/uart_tx.v

@@ -0,0 +1,121 @@
+`timescale 1ns / 1ns
+module uart_tx
+#(
+    parameter  CLK_FREQ = 50000000,            //系统时钟频率
+    parameter  UART_BPS = 9600                //串口波特率
+)
+(
+    input	      sys_clk,                  //系统时钟
+    input         sys_rst_n,                //系统复位，低电平有效
+
+    input         uart_en,                  //发送使能信号
+    input  [7:0]  uart_din,                 //待发送数据
+    output        uart_tx_busy,             //发送忙状态标志
+    output  reg   uart_txd                  //UART发送端口
+);
+
+localparam  BPS_CNT  = CLK_FREQ/UART_BPS;
+//reg define
+reg        uart_en_d0;
+reg        uart_en_d1;
+reg [15:0] clk_cnt;                         //系统时钟计数器
+reg [ 3:0] tx_cnt;                          //发送数据计数器
+reg        tx_flag;                         //发送过程标志信号
+reg [ 7:0] tx_data;                         //寄存发送数据
+
+//wire define
+wire       en_flag;
+
+/****************************************
+  *  			Main Code
+  *  			主要代码
+ ****************************************/
+ //在串口发送过程中给出忙状态标志
+assign uart_tx_busy = tx_flag;
+
+//捕获uart_en上升沿，得到一个时钟周期的脉冲信号
+assign en_flag = (~uart_en_d1) & uart_en_d0;
+
+ always @ (posedge sys_clk or negedge sys_rst_n) begin
+     if(!sys_rst_n) begin
+         uart_en_d0 <= 1'b0;
+         uart_en_d1 <= 1'b0;
+     end
+     else begin
+         uart_en_d0 <= uart_en;
+         uart_en_d1 <= uart_en_d0;
+     end
+ end
+
+ //当脉冲信号en_flag到达时,寄存待发送的数据，并进入发送过程
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if (!sys_rst_n) begin
+        tx_flag <= 1'b0;
+        tx_data <= 8'd0;
+    end
+    else if (en_flag) begin                 //检测到发送使能上升沿
+            tx_flag <= 1'b1;                //进入发送过程，标志位tx_flag拉高
+            tx_data <= uart_din;            //寄存待发送的数据
+        end
+                                            //计数到停止位结束时，停止发送过程
+        else if ((tx_cnt == 4'd9) && (clk_cnt == BPS_CNT -(BPS_CNT/16))) begin
+            tx_flag <= 1'b0;                //发送过程结束，标志位tx_flag拉低
+            tx_data <= 8'd0;
+        end
+        else begin
+            tx_flag <= tx_flag;
+            tx_data <= tx_data;
+        end
+end
+
+ //进入发送过程后，启动系统时钟计数器
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if (!sys_rst_n)
+        clk_cnt <= 16'd0;
+    else if (tx_flag) begin                 //处于发送过程
+        if (clk_cnt < BPS_CNT - 1)
+            clk_cnt <= clk_cnt + 1'b1;
+        else
+            clk_cnt <= 16'd0;               //对系统时钟计数达一个波特率周期后清零
+    end
+    else
+        clk_cnt <= 16'd0; 				    //发送过程结束
+end
+
+//进入发送过程后，启动发送数据计数器
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if (!sys_rst_n)
+        tx_cnt <= 4'd0;
+    else if (tx_flag) begin                 //处于发送过程
+        if (clk_cnt == BPS_CNT - 1)			//对系统时钟计数达一个波特率周期
+            tx_cnt <= tx_cnt + 1'b1;		//此时发送数据计数器加1
+        else
+            tx_cnt <= tx_cnt;
+    end
+    else
+        tx_cnt  <= 4'd0;				    //发送过程结束
+end
+
+//根据发送数据计数器来给uart发送端口赋值
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if (!sys_rst_n)
+        uart_txd <= 1'b1;
+    else if (tx_flag)
+        case(tx_cnt)
+            4'd0: uart_txd <= 1'b0;         //起始位
+            4'd1: uart_txd <= tx_data[0];   //数据位最低位
+            4'd2: uart_txd <= tx_data[1];
+            4'd3: uart_txd <= tx_data[2];
+            4'd4: uart_txd <= tx_data[3];
+            4'd5: uart_txd <= tx_data[4];
+            4'd6: uart_txd <= tx_data[5];
+            4'd7: uart_txd <= tx_data[6];
+            4'd8: uart_txd <= tx_data[7];   //数据位最高位
+            4'd9: uart_txd <= 1'b1;         //停止位
+            default: ;
+        endcase
+    else
+        uart_txd <= 1'b1;                   //空闲时发送端口为高电平
+end
+
+endmodule

package/output/npr/npr_plugins/verilog/uart/uart_tx_count.v

@@ -0,0 +1,72 @@
+`timescale 1ns / 1ns
+
+module uart_tx_count
+#(
+	parameter COUNT_200 = 26'd10000000
+)
+(
+    input sys_clk,
+    input sys_rst_n,
+    output reg enable_txd,  //允许串口发送
+    output reg [7:0] data
+ );
+
+reg [25:0] clk_cnt; //计数器
+reg [3:0]  dat_cnt;//数据计数器，发送第几个
+
+
+
+
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n) begin
+        clk_cnt <= 26'b0;
+    end
+    else if(clk_cnt == COUNT_200) begin
+        clk_cnt <= 26'b0;
+    end
+    else begin
+        clk_cnt <= clk_cnt + 1'b1;
+    end
+end
+
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n) begin
+        dat_cnt <= 4'b0;
+        enable_txd <= 1'b0;
+    end
+    else if(clk_cnt == COUNT_200 - 1'b1) begin
+            dat_cnt <= dat_cnt + 1'b1;
+            enable_txd <= 1'b1;
+    end
+    else
+        enable_txd <= 1'b0;
+end
+
+always @ (posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n) begin
+        data <= 8'b0;
+    end
+    else begin
+        case(dat_cnt)
+            4'd0:data <= 8'b00110000;
+            4'd1:data <= 8'b00110001;
+            4'd2:data <= 8'b00110010;
+            4'd3:data <= 8'b00110011;
+            4'd4:data <= 8'b00110100;
+            4'd5:data <= 8'b00110101;
+            4'd6:data <= 8'b00110110;
+            4'd7:data <= 8'b00110111;
+            4'd8:data <= 8'b00111000;
+            4'd9:data <= 8'b00111001;
+            4'd10:data <= 8'b00111010;
+            4'd11:data <= 8'b00111011;
+            4'd12:data <= 8'b00111100;
+            4'd13:data <= 8'b00111101;
+            4'd14:data <= 8'b00111110;
+            4'd15:data <= 8'b00111111;
+            default:;
+            endcase
+    end
+end
+
+endmodule

package/output/npr/readme.md

@@ -0,0 +1,7 @@
+# npr
+
+npr 用于执行个js文件
+
+```markdown
+npr hello
+```

package/package.json

@@ -46,5 +46,5 @@
   "scripts": {
     "test": "echo \"Error: no test specified\" && exit 1"
   },
-  "version": "3.0.2"
+  "version": "3.0.5"
 }

package/plugins/Modelsim/Modelsim.js

@@ -0,0 +1,29 @@
+/**
+ build/CUR_DIR
+ led/tb.v led.v
+ */
+
+const fs = require('fs');
+
+fs.writeFileSync('run.bat',
+
+`rmdir /s /q work
+del server.js
+del vsim.wlf
+del transcript
+set MY_PARAM=%1%
+modelsim -do top.do`
+
+);
+
+
+fs.writeFileSync('top.do',
+
+`vlib work
+vmap work work
+vlog   ../$::env(MY_PARAM)/*.v
+vsim -voptargs=+acc  work.tb
+add wave -position insertpoint sim:/tb/*
+run 100ns`
+
+);

package/plugins/Modelsim/run.bat

@@ -0,0 +1,6 @@
+rmdir /s /q work
+del server.js
+del vsim.wlf
+del transcript
+set MY_PARAM=%1%
+modelsim -do top.do

package/plugins/Modelsim/top.do

@@ -0,0 +1,6 @@
+vlib work
+vmap work work
+vlog   ../$::env(MY_PARAM)/*.v
+vsim -voptargs=+acc  work.tb
+add wave -position insertpoint sim:/tb/*
+run 100ns