ming_node 3.0.2 → 3.0.5

package/output/ming_api_mock/mock.bat

@@ -0,0 +1,21 @@
+@ECHO OFF
+TITLE mock
+
+SET curPath=%cd%
+
+:start
+set p1=%1%
+set p2=%2% 
+set port=8888
+set serverfile=""
+set swi=0
+echo %p1%|findstr /be "[0-9]*" >nul &&  set swi=1 || set swi=2
+
+
+if %swi%==1   set  port=%p1%
+if %swi%==2   set  serverfile=%p1% 
+if %swi%==2   set  port=%p2%
+if %swi%==2   (if not "%1" == ""  curl %serverfile% > server.js)
+echo port=%port%
+echo serverfile=%serverfile%
+node "%~dp0/ming_api_mock.js" "%curPath%/" %port% "%1" "%2" "%3" "%4" "%5" "%6" "%7" "%8" "%9"

package/output/ming_api_mock/mock.sh

@@ -0,0 +1,15 @@
+#!/bin/bash
+#port=8888
+serverfile=""
+sw=`echo  $1 | sed 's/[0-9]//g' | sed 's/-//g'`
+if [ ${#sw} -eq 0 ];then
+port=$1
+else
+serverfile=$1
+port=$2
+curl $serverfile > server.js
+fi
+
+echo port=$port
+echo serverfile=$serverfile
+node  $(cd $(dirname ${BASH_SOURCE:-$0});pwd)/ming_api_mock.js  $(pwd)/  $port $@

package/output/npr/npr.bat

@@ -0,0 +1,7 @@
+@ECHO OFF
+TITLE npr
+:start
+set p1=%1%
+set p2=%2%
+set curPath=%cd%
+node "%~dp0/npr_plugins/%1/index.js" "%curPath%/" "%1" "%2" "%3" "%4" "%5" "%6" "%7" "%8" "%9"

package/output/npr/npr_plugins/MakeModelsim/index.js

@@ -0,0 +1,157 @@
+/**
+ build/CUR_DIR
+ led/tb.v led.v
+ */
+const child_process = require('child_process');
+const fs = require('fs');
+var args = process.argv.splice(2)
+let argsPath=args[0] || "./";
+
+
+const M={};
+M.exec = function (comand) {
+    let promise = new Promise(function (reslove, reject) {
+        child_process.exec(comand, function (err, stdout, stderr) {
+            if (err || stderr) console.error(err, stderr);
+            reslove(stdout);
+        });
+
+    })
+    return promise;
+}
+
+
+
+
+async function install(){
+    await M.exec(`mkdir doc`);
+    await M.exec(`mkdir opt`);
+    await M.exec(`mkdir sims`);
+    await M.exec(`mkdir src`);
+    await M.exec(`mkdir tb`);
+
+    fs.writeFileSync('doc/Readme.md',
+`# led
+led test`
+    );
+
+    fs.writeFileSync('sims/filelist.f',
+`"../src/led.v"
+"../tb/tb.v"`
+    );
+
+
+    fs.writeFileSync('sims/Makefile',
+        `#setting parameter
+work= work
+output= ../opt
+vsimbatch0= -do "run -all"
+
+
+#commandbegin
+all:compile vsim
+lib:
+\techo "start compile for Questasim10.6c"
+\tvlib $(work)
+\tvmap work $(work)
+vlog :
+\tvlog  -f filelist.f -l $(output)/compile.log
+compile: lib vlog
+run:
+\tmodelsim -do ./run.do
+#make clean
+clean:
+\tdel *.wlf
+\tdel vsim_stacktrace.vstf
+\tdel transcript
+\tdel modelsim.ini
+\trmdir /s /q work
+`
+    );
+
+    fs.writeFileSync('sims/run.do',
+        `vsim -voptargs=+acc  work.tb
+add wave -position insertpoint sim:/tb/*
+run 100ns`
+    );
+
+
+    fs.writeFileSync('src/led.v',
+        `module led(                     
+    input     key , 
+    
+    output    led  
+);
+
+
+assign led =key;   
+
+endmodule`
+    );
+
+    fs.writeFileSync('tb/tb.v',
+        `\`timescale 1ns / 1ns        //仿真单位/仿真精度
+
+module tb();
+
+
+
+reg           key;
+wire          led;
+
+
+initial begin
+    key <= 1'b1;   
+    #12        
+    key <= 1'b1;  
+    #3
+    key <= 1'b0;   
+    #2
+    key <= 1'b1;
+    #2
+    key <= 1'b0;
+    #2        
+    key <= 1'b1;  
+    #3
+    key <= 1'b0;   
+    #2
+    key <= 1'b1;
+    #2
+    key <= 1'b0;
+end
+
+//例化led模块
+led  u_led(
+    .key          (key),
+    .led          (led)
+    );
+
+endmodule
+
+`
+    );
+
+    console.log("MakeModelsim install success!")
+}
+
+function help(){
+    console.log(
+        `
+cd sims;
+make compile
+make run
+`)
+}
+
+function main(){
+
+    switch (args[2]){
+        case "": install();break;
+        case "help": help();break;
+    }
+
+}
+
+
+main()
+

package/output/npr/npr_plugins/Modelsim/index.js

@@ -0,0 +1,72 @@
+/**
+ build/CUR_DIR
+ led/tb.v led.v
+ */
+const child_process = require('child_process');
+const fs = require('fs');
+var args = process.argv.splice(2)
+let argsPath=args[0] || "./";
+
+
+const M={};
+M.exec = function (comand) {
+    let promise = new Promise(function (reslove, reject) {
+        child_process.exec(comand, function (err, stdout, stderr) {
+            if (err || stderr) console.error(err, stderr);
+            reslove(stdout);
+        });
+
+    })
+    return promise;
+}
+
+
+
+
+async function install(){
+    await M.exec(`mkdir build`);
+    fs.writeFileSync('build/run.bat',
+
+        `rmdir /s /q work
+del vsim.wlf
+del transcript
+set MY_PARAM=%1%
+modelsim -do top.do`
+
+    );
+
+
+    fs.writeFileSync('build/top.do',
+
+        `vlib work
+vmap work work
+vlog   ../$::env(MY_PARAM)/*v
+vsim -voptargs=+acc  work.tb
+add wave -position insertpoint sim:/tb/*
+run 100ns`
+
+    );
+
+    console.log("Modelsim install success!")
+}
+
+function help(){
+    console.log(
+        `
+build/$:run led
+led/tb.v led.v
+`)
+}
+
+function main(){
+
+    switch (args[2]){
+        case "": install();break;
+        case "help": help();break;
+    }
+
+}
+
+
+main()
+

package/output/npr/npr_plugins/common/ming_node.js

@@ -0,0 +1,58 @@
+const child_process = require('child_process');
+const fs = require('fs');
+const path = require('path');
+
+const M={};
+M.exec = function (comand) {
+    let promise = new Promise(function (reslove, reject) {
+        child_process.exec(comand, function (err, stdout, stderr) {
+            if (err || stderr) console.error(err, stderr);
+            reslove(stdout);
+        });
+
+    })
+    return promise;
+}
+
+M.copyFile= (relfile)=>{
+    let dir=path.parse(relfile).dir;
+    if (!fs.existsSync(dir)) {
+        fs.mkdirSync(dir);
+    }
+    let srcText= fs.readFileSync(path.join(CUR_DIR,relfile), "utf-8");
+    fs.writeFileSync(relfile,srcText);
+    return true;
+}
+const checkDirectory = function (src, dst, callback) {
+    fs.access(dst, fs.constants.F_OK, (err) => {
+        if (err) {
+            fs.mkdirSync(dst);
+            callback(src, dst);
+        } else {
+            callback(src, dst);
+        }
+    });
+};
+
+M.copyDir = function (src, dst) {
+    if (!fs.existsSync(dst)) {
+        fs.mkdirSync(dst);
+    }
+    let paths = fs.readdirSync(src); //同步读取当前目录
+    paths.forEach(function (path) {
+        let _src = src + '/' + path;
+        let _dst = dst + '/' + path;
+        fs.stat(_src, function (err, stats) {  //stats  该对�? 包含文件属�?
+            if (err) throw err;
+            if (stats.isFile()) { //如果是个文件则拷�?
+                let readable = fs.createReadStream(_src);//创建读取�?
+                let writable = fs.createWriteStream(_dst);//创建写入�?
+                readable.pipe(writable);
+            } else if (stats.isDirectory()) { //是目录则 递归
+                checkDirectory(_src, _dst, M.copyDir);
+            }
+        });
+    });
+}
+
+module.exports = M;

package/output/npr/npr_plugins/demo/index.js

@@ -0,0 +1 @@
+console.log("demo111")

package/output/npr/npr_plugins/hello/index.js

@@ -0,0 +1 @@
+console.log("hello word")

package/output/npr/npr_plugins/install/index.js

@@ -0,0 +1,27 @@
+const child_process = require('child_process');
+var args = process.argv.splice(2)
+const M={};
+M.exec = function (comand) {
+    let promise = new Promise(function (reslove, reject) {
+        child_process.exec(comand, function (err, stdout, stderr) {
+            if (err || stderr) console.error(err, stderr);
+            reslove(stdout);
+        });
+
+    })
+    return promise;
+}
+M.getFileNameByUrl=function (url){
+    let split= url.split("/");
+    return split[split.length-1]
+}
+
+async function main(){
+    let npr_pluginsPath=process.argv[1].replaceAll("\\install\\index.js","");
+    let fileName=M.getFileNameByUrl(args[2]).replace(".js","");
+    await M.exec(`mkdir ${npr_pluginsPath}\\${fileName}`)
+    await M.exec(`curl ${args[2]} > ${npr_pluginsPath}\\${fileName}\\index.js`)
+    console.log(fileName+"  install success!")
+}
+
+main()

package/output/npr/npr_plugins/list/index.js

@@ -0,0 +1,20 @@
+const child_process = require('child_process');
+
+const M={};
+M.exec = function (comand) {
+    let promise = new Promise(function (reslove, reject) {
+        child_process.exec(comand, function (err, stdout, stderr) {
+            if (err || stderr) console.error(err, stderr);
+            reslove(stdout);
+        });
+
+    })
+    return promise;
+}
+
+async function main(){
+    let npr_pluginsPath=process.argv[1].replaceAll("\\list\\index.js","");
+    let r=  await M.exec("dir /b "+ npr_pluginsPath);
+    console.log(r.replaceAll(".idea",""));
+}
+main()

package/output/npr/npr_plugins/verilog/Readme.md

@@ -0,0 +1 @@
+demo����򵥵ķ�������

package/output/npr/npr_plugins/verilog/breath_led/breath_led.v

@@ -0,0 +1,99 @@
+
+module breath_led(
+    input       clk ,      //系统时钟 50MHz
+    input       rst_n ,    //系统复位，低电平有效
+    output reg  led            //LED灯
+);
+
+
+parameter CNT_2US_MAX = 7'd100;
+parameter CNT_2MS_MAX = 10'd1000;
+parameter CNT_2S_MAX  = 10'd1000;
+
+//reg define
+reg [6:0] cnt_2us=0;
+reg [9:0] cnt_2ms=0;
+reg [9:0] cnt_2s=0;
+reg       inc_dec_flag; //亮度递增/递减 0:递增 1:递减
+
+wire add_cnt_2us;
+wire end_cnt_2us;
+wire add_cnt_2ms;
+wire end_cnt_2ms;
+wire add_cnt_2s;
+wire end_cnt_2s;
+
+
+assign add_cnt_2us = 1;
+assign end_cnt_2us = add_cnt_2us && cnt_2us== CNT_2US_MAX-1;
+
+assign add_cnt_2ms= end_cnt_2us;
+assign end_cnt_2ms= add_cnt_2ms &&  cnt_2ms == CNT_2MS_MAX - 1;
+
+assign add_cnt_2s=  end_cnt_2ms;
+assign end_cnt_2s=  add_cnt_2s  &&   cnt_2s == CNT_2S_MAX - 1;
+
+
+//cnt_2us:计数2us
+always @(posedge clk or negedge rst_n)begin
+	if(!rst_n)begin
+		cnt_2us <= 0;
+	end
+	else if(add_cnt_2us)begin
+		if(end_cnt_2us)
+			cnt_2us <= 0;
+		else
+			cnt_2us <= cnt_2us + 1;
+	end
+end
+
+//cnt_2ms:计数2ms
+always@(posedge clk or negedge rst_n) begin
+    if(!rst_n)
+        cnt_2ms <= 10'b0;
+    else if(add_cnt_2ms) begin
+        if(end_cnt_2ms)
+            cnt_2ms <= 10'b0;
+        else
+      		cnt_2ms <= cnt_2ms + 1;
+    end
+end
+
+//cnt_2s:计数2s
+always@(posedge clk or negedge rst_n) begin
+    if(!rst_n)
+        cnt_2s <= 0;
+    else if(add_cnt_2s) begin
+        if(end_cnt_2s)
+            cnt_2s <= 10'b0;
+        else
+      		cnt_2s <= cnt_2s + 1;
+    end
+end
+
+
+
+
+
+
+//inc_dec_flag为低电平，led灯由暗变亮，inc_dec_flag为高电平，led灯由亮变暗
+always@(posedge clk or negedge rst_n) begin
+    if(!rst_n)
+        inc_dec_flag <= 1'b0;
+    else if(end_cnt_2s && end_cnt_2ms && end_cnt_2us)
+        inc_dec_flag <= ~inc_dec_flag;
+    else
+        inc_dec_flag <= inc_dec_flag;
+end
+
+//led:输出信号连接到外部的led灯
+always@(posedge clk or negedge rst_n) begin
+    if(!rst_n)
+        led <= 1'b0;
+    else if((inc_dec_flag == 1'b1 && cnt_2ms >= cnt_2s) || (inc_dec_flag == 1'b0 && cnt_2ms <= cnt_2s))
+        led <= 1'b1;
+    else
+        led <= 1'b0;
+end
+
+endmodule

package/output/npr/npr_plugins/verilog/breath_led/tb.v

@@ -0,0 +1,39 @@
+`timescale  1ns / 1ns
+
+module tb;
+
+// 10ns
+parameter PERIOD       = 10      ;
+parameter CNT_2US_MAX  = 7'd10  ;
+parameter CNT_2MS_MAX  = 10'd100;
+parameter CNT_2S_MAX   = 10'd100;
+
+// breath_led Inputs
+reg   sys_clk                              = 0 ;
+reg   sys_rst_n                            = 0 ;
+
+// breath_led Outputs
+wire  led                                  ;
+
+
+initial
+begin
+    forever #(PERIOD/2)  sys_clk=~sys_clk;
+end
+
+initial
+begin
+    #(PERIOD*2) sys_rst_n  =  1;
+end
+
+breath_led #(
+    .CNT_2US_MAX ( CNT_2US_MAX ),
+    .CNT_2MS_MAX ( CNT_2MS_MAX ),
+    .CNT_2S_MAX  ( CNT_2S_MAX  ))
+ u_breath_led (
+    .clk                 ( sys_clk     ),
+    .rst_n               ( sys_rst_n   ),
+    .led                 ( led         )
+);
+
+endmodule

package/output/npr/npr_plugins/verilog/demo/led.v

@@ -0,0 +1,12 @@
+
+
+module led(
+    input     key ,
+
+    output    led
+);
+
+
+assign led = ~key;
+
+endmodule

package/output/npr/npr_plugins/verilog/demo/sims/Makefile

@@ -0,0 +1,25 @@
+#setting parameter
+work= work
+output= ./
+vsimbatch0= -do "run -all"
+
+
+#commandbegin
+all:compile vsim
+lib:
+	echo "start compile for Questasim10.6c"
+	vlib $(work)
+	vmap work $(work)
+vlog :
+	vlog  -f filelist.f -l $(output)/compile.log
+compile: lib vlog
+run:
+	modelsim -do ./run.do
+#make clean
+clean:
+	del *.wlf
+	del vsim_stacktrace.vstf
+	del transcript
+	del compile.log
+	del modelsim.ini
+	rmdir /s /q work

package/output/npr/npr_plugins/verilog/demo/sims/filelist.f

@@ -0,0 +1 @@
+"../*v"

package/output/npr/npr_plugins/verilog/demo/sims/run.do

@@ -0,0 +1,3 @@
+vsim -voptargs=+acc  work.tb
+add wave -position insertpoint sim:/tb/*
+run 100ns

package/output/npr/npr_plugins/verilog/demo/tb.v

@@ -0,0 +1,30 @@
+`timescale 1ns / 1ns        //���浥λ/���澫��
+
+module tb();
+
+
+
+reg           key;
+wire          led;
+
+
+initial begin
+    key <= 1'b1;
+    #2
+    key <= 1'b1;
+    #3
+    key <= 1'b0;
+    #2
+    key <= 1'b1;
+    #2
+    key <= 1'b0;
+end
+
+//����ledģ��
+led  u_led(
+    .key          (key),
+    .led          (led)
+    );
+
+endmodule
+

package/output/npr/npr_plugins/verilog/index.js

@@ -0,0 +1,25 @@
+const path = require('path');
+var args = process.argv.splice(2)
+var CUR_DIR=path.parse(process.argv[1]).dir;
+const M=require("../common/ming_node");
+async function install(dir){
+    M.copyDir(path.join(CUR_DIR,dir),dir);
+}
+async function help(){
+   let r=await  M.exec("dir "+CUR_DIR);
+   console.log(r);
+}
+
+function main(){
+    switch (args[2]){
+        case "": install("led");break;
+        case "help": help();break;
+        default:{
+            install(args[2]);break;
+        }
+    }
+
+}
+
+main();
+

package/output/npr/npr_plugins/verilog/key_led/key_debounce.v

@@ -0,0 +1,57 @@
+module key_debounce(
+    input  clk,
+    input  rst_n,
+    input        key_in     ,
+    output  reg  key_out
+);
+
+//计算器值
+parameter  MAX_CNT =10 ;
+reg[7:0] cnt=0;
+wire add_cnt;
+wire end_cnt;
+reg        key_d0;            //将按键信号延迟一个时钟周期
+reg        key_d1;            //将按键信号延迟两个时钟周期
+
+always @ (posedge clk or negedge rst_n) begin
+    if(!rst_n) begin
+        key_d0 <= 1'b1;
+        key_d1 <= 1'b1;
+    end
+    else begin
+        key_d0 <= key_in;
+        key_d1 <= key_d0;
+    end
+end
+
+
+//第一段：同步时序always模块，格式化描述次态寄存器迁移到现态寄存器(不需更改）
+always @(posedge clk or negedge rst_n)begin
+	if(!rst_n)begin
+		cnt <= 0;
+	end
+	else if(add_cnt)begin
+		if(end_cnt)
+			cnt <= 0;
+		else
+			cnt <= cnt + 1;
+	end
+end
+
+
+//第二段：设计转移条件
+assign add_cnt = cnt<MAX_CNT;
+assign end_cnt = (add_cnt && cnt== MAX_CNT-1)||key_d1!=key_d0 ;
+
+
+//第三段：同步时序always模块,输出
+always @(posedge clk or negedge rst_n)begin
+    if(rst_n==1'b0)
+       key_out<=1'b1;
+    else if(cnt==MAX_CNT-1)
+       key_out<=key_d1;
+end
+
+
+
+endmodule