ming_node 3.0.2 → 3.0.5

package/output/npr/npr_plugins/verilog/key_led/tb.v

@@ -0,0 +1,78 @@
+
+`timescale 1ns / 1ns        //仿真单位/仿真精度
+
+module tb();
+
+//parameter define
+parameter  CLK_PERIOD = 10;           //时钟周期 10ns
+parameter  CNT_MAX = 20'd10;          //消抖时间 10ns
+
+//reg define
+reg           sys_clk;
+reg           sys_rst_n;
+reg           key;
+
+wire          key_out;
+wire          beep;
+
+//信号初始化
+initial begin
+    sys_clk <= 1'b0;
+    sys_rst_n <= 1'b0;
+    key <= 1'b1;
+    #200
+    sys_rst_n <= 1'b1;
+//key信号变化
+    #20
+    key <= 1'b0;
+    #20
+    key <= 1'b1;
+    #50
+    key <= 1'b0;
+    #40
+    key <= 1'b1;
+    #20
+    key <= 1'b0;
+    #300
+    key <= 1'b1;
+    #50
+    key <= 1'b0;
+    #40
+    key <= 1'b1;
+    #300
+    key <= 1'b0;
+    #300
+    key <= 1'b1;
+    #500
+    key <= 1'b0;
+    #500
+    key <= 1'b1;
+    #500
+    key <= 1'b0;
+    #500
+    key <= 1'b1;
+end
+
+//产生时钟
+always #(CLK_PERIOD/2) sys_clk = ~sys_clk;
+
+//按键消抖
+key_debounce #(
+    .MAX_CNT    (CNT_MAX)
+)u_top_key_beep(
+    .clk      (sys_clk),
+    .rst_n    (sys_rst_n),
+    .key_in   (key),
+    .key_out(key_out)
+    );
+
+//灯取反
+toggle_pin u_toggle_pin(
+    .clk      (sys_clk),
+    .rst_n    (sys_rst_n),
+    .in_pin(~key_out),
+    .out_pin(beep)
+);
+
+endmodule
+

package/output/npr/npr_plugins/verilog/key_led/toggle_pin.v

@@ -0,0 +1,35 @@
+module toggle_pin(
+    input        clk,
+    input        rst_n,
+    input        in_pin,
+    output  reg  out_pin
+    );
+
+
+reg    in_pin_d0;          //将消抖后的按键值延迟一个时钟周期
+reg    in_pin_d1;
+
+
+always @ (posedge clk or negedge rst_n) begin
+    if(!rst_n) begin
+        in_pin_d0 <= 1'b1;
+        in_pin_d1 <= 1'b1;
+    end
+    else begin
+        in_pin_d0 <= in_pin;
+        in_pin_d1 <= in_pin_d0;
+    end
+end
+
+
+//每次按键按下时，就翻转蜂鸣器的状态
+always @ (posedge clk or negedge rst_n) begin
+    if(!rst_n)
+        out_pin <= 1'b1;
+    else if(in_pin_d0==0  &&  in_pin_d1 == 1)
+        out_pin <= ~out_pin;
+    else
+        out_pin <= out_pin;
+end
+
+endmodule

package/output/npr/npr_plugins/verilog/led/led.v

@@ -0,0 +1,12 @@
+
+
+module led(                     
+    input     key , 
+    
+    output    led  
+);
+
+
+assign led = ~key;   
+
+endmodule

package/output/npr/npr_plugins/verilog/led/tb.v

@@ -0,0 +1,30 @@
+`timescale 1ns / 1ns        //���浥λ/���澫��
+
+module tb();
+
+
+
+reg           key;
+wire          led;
+
+
+initial begin
+    key <= 1'b1;   
+    #2        
+    key <= 1'b1;  
+    #3
+    key <= 1'b0;   
+    #2
+    key <= 1'b1;
+    #2
+    key <= 1'b0;
+end
+
+//����ledģ��
+led  u_led(
+    .key          (key),
+    .led          (led)
+    );
+
+endmodule
+

package/output/npr/npr_plugins/verilog/modelsim_tcl/filelist.f

@@ -0,0 +1,2 @@
+"../src/*v"
+"../tb/*v"

package/output/npr/npr_plugins/verilog/modelsim_tcl/restart.tcl

@@ -0,0 +1 @@
+vlog -f filelist.f;restart -f;run 100ns

package/output/npr/npr_plugins/verilog/modelsim_tcl/run.do

@@ -0,0 +1,3 @@
+vsim -voptargs=+acc  work.tb
+add wave -position insertpoint sim:/tb/*
+run 100ns

package/output/npr/npr_plugins/verilog/modelsim_tcl//346/216/247/345/210/266/345/217/260_Makefile

@@ -0,0 +1,24 @@
+#setting parameter
+work= work
+output= ../opt
+vsimbatch0= -do "run -all"
+
+
+#commandbegin
+all:compile vsim
+lib:
+	echo "start compile for Questasim10.6c"
+	vlib $(work)
+	vmap work $(work)
+vlog :
+	vlog  -f filelist.f -l $(output)/compile.log
+compile: lib vlog
+run:
+	vsim work.tb -l tb.log -c -do "run -all;exit;"
+#make clean
+clean:
+	del *.wlf
+	del vsim_stacktrace.vstf
+	del transcript
+	del modelsim.ini
+	rmdir /s /q work

package/output/npr/npr_plugins/verilog/modelsim_tcl//347/252/227/345/217/243_Makefile

@@ -0,0 +1,24 @@
+#setting parameter
+work= work
+output= ../opt
+vsimbatch0= -do "run -all"
+
+
+#commandbegin
+all:compile vsim
+lib:
+	echo "start compile for Questasim10.6c"
+	vlib $(work)
+	vmap work $(work)
+vlog :
+	vlog  -f filelist.f -l $(output)/compile.log
+compile: lib vlog
+run:
+	modelsim -do ./run.do
+#make clean
+clean:
+	del *.wlf
+	del vsim_stacktrace.vstf
+	del transcript
+	del modelsim.ini
+	rmdir /s /q work

package/output/npr/npr_plugins/verilog/simple_verilog/sims/C_Makefile

@@ -0,0 +1,27 @@
+#setting parameter
+work= work
+output= ./
+vsimbatch0= -do "run -all"
+
+#commandbegin
+all:compile vsim
+lib:
+	echo "start compile for Questasim10.6c"
+	vlib $(work)
+	vmap work $(work)
+vlog :
+	vlog  -f filelist.f -l $(output)/compile.log
+compile: lib vlog
+run:
+	vsim work.tb -l tb.log -c -do "run -all;exit;"
+restart:
+	vlog -f filelist.f -l $(output)/compile.log
+	vsim work.tb -l tb.log -c -do "run -all;exit;"	
+#make clean
+clean:
+	del *.log
+	del *.wlf
+	del vsim_stacktrace.vstf
+	del transcript
+	del modelsim.ini
+	rmdir /s /q work

package/output/npr/npr_plugins/verilog/simple_verilog/sims/Makefile

@@ -0,0 +1,25 @@
+#setting parameter
+work= work
+output= ./
+vsimbatch0= -do "run -all"
+
+
+#commandbegin
+all:compile vsim
+lib:
+	echo "start compile for Questasim10.6c"
+	vlib $(work)
+	vmap work $(work)
+vlog :
+	vlog  -f filelist.f -l $(output)/compile.log
+compile: lib vlog
+run:
+	modelsim -do ./run.do
+#make clean
+clean:
+	del *.log
+	del *.wlf
+	del vsim_stacktrace.vstf
+	del transcript
+	del modelsim.ini
+	rmdir /s /q work

package/output/npr/npr_plugins/verilog/simple_verilog/sims/W_Makefile

@@ -0,0 +1,24 @@
+#setting parameter
+work= work
+output= ../opt
+vsimbatch0= -do "run -all"
+
+
+#commandbegin
+all:compile vsim
+lib:
+	echo "start compile for Questasim10.6c"
+	vlib $(work)
+	vmap work $(work)
+vlog :
+	vlog  -f filelist.f -l $(output)/compile.log
+compile: lib vlog
+run:
+	modelsim -do ./run.do
+#make clean
+clean:
+	del *.wlf
+	del vsim_stacktrace.vstf
+	del transcript
+	del modelsim.ini
+	rmdir /s /q work

package/output/npr/npr_plugins/verilog/simple_verilog/sims/filelist.f

@@ -0,0 +1 @@
+"../tb/*v"

package/output/npr/npr_plugins/verilog/simple_verilog/sims/run.do

@@ -0,0 +1,3 @@
+vsim -voptargs=+acc  work.tb
+add wave -position insertpoint sim:/tb/*
+run 100ns

package/output/npr/npr_plugins/verilog/simple_verilog/tb/led.sv

@@ -0,0 +1,72 @@
+module led(
+    input clk,
+    input rst_n,
+    input  key,
+    output wire[2:0]  led
+);
+
+typedef enum reg [2:0] {
+    S0, 
+    S1, 
+    S2, 
+    S3 
+} state_t;
+state_t state_c=S0, state_n=S0;
+logic s0_s1_start;
+logic s1_s2_start;
+logic s2_s3_start;
+
+
+always@(posedge clk or negedge rst_n)begin
+    if(!rst_n)begin
+        state_c <= S0;
+    end
+    else begin
+        state_c <= state_n;
+    end
+end
+
+always@(*)begin
+    case(state_c)
+        S0: begin
+            if(s0_s1_start)begin
+                state_n = S1;
+            end
+            else begin
+                state_n = state_c;
+            end
+        end
+
+        S1:begin
+            if(s1_s2_start)begin
+                state_n = S2;
+            end
+            else begin
+                state_n = state_c;
+            end
+        end
+
+        S2:begin
+            if(s2_s3_start)begin
+                state_n = S3;
+            end
+            else begin
+                state_n = state_c;
+            end
+        end
+        default:begin
+                state_n = S0;
+        end
+    endcase
+end
+
+assign s0_s1_start  = state_c==S0 ;
+assign s1_s2_start   = state_c==S1  ;
+assign s2_s3_start   = state_c==S2   ;
+
+
+assign led=state_c;
+
+
+endmodule
+

package/output/npr/npr_plugins/verilog/simple_verilog/tb/tb.sv

@@ -0,0 +1,54 @@
+`timescale 1ns / 1ns
+
+module tb();
+
+
+parameter PERIOD  = 10;
+
+reg           clk=1;
+reg           rst_n=1;
+reg           key;
+wire[2:0]          led;
+
+
+
+initial begin
+    forever #(PERIOD/2)  clk=~clk;
+end
+
+
+
+initial begin
+    $monitor ("rst_n=%0b led=%0b",rst_n, led);
+    #(PERIOD*2) 
+    rst_n  =  1;
+    key <= 1'b1;   
+    #(PERIOD*2)        
+    key <= 1'b1;  
+    #(PERIOD*2) 
+    key <= 1'b0;   
+    #(PERIOD*2) 
+    key <= 1'b1;
+     #(PERIOD*2) 
+    key <= 1'b0;
+     #(PERIOD*2) 
+    key <= 1'b1;  
+    #(PERIOD*2) 
+    key <= 1'b0;   
+     #(PERIOD*2) 
+    key <= 1'b1;
+    #(PERIOD*2) 
+    key <= 1'b0;
+    $display("TTTT");
+end
+
+
+led  u_led(
+     .clk          (clk),
+    .rst_n          (rst_n),
+    .key          (key),
+    .led          (led)
+    );
+
+endmodule
+

package/output/npr/npr_plugins/verilog/smg/HC_FPGA_Demo_Top.v

@@ -0,0 +1,29 @@
+module HC_FPGA_Demo_Top
+(
+    input CLOCK_XTAL_50MHz,
+	input RESET,
+	output[7:0] DIG,
+	output[5:0] SEL
+);
+
+
+wire[3:0] d0=5;
+wire[3:0] d1=2;
+wire[3:0] d2=1;
+wire[3:0] d3=7;
+
+
+digital_tube  u_digital_tube (
+    .clk                     ( CLOCK_XTAL_50MHz          ),
+    .rst_n                   ( RESET        ),
+    .d0                      ( d0 ),
+    .d1                      ( d1 ),
+    .d2                      ( d2 ),
+    .d3                      ( d3 ),
+    .dp_in                   ( ~0 ),
+    .sel                     ( SEL    [5:0] ),
+    .dig                     ( DIG    [7:0] )
+);
+
+
+endmodule

package/output/npr/npr_plugins/verilog/smg/digital_tube.v

@@ -0,0 +1,93 @@
+module digital_tube(
+    input clk,
+    input rst_n,
+    input [3:0] d0, //第一个数码管显示的数字
+    input [3:0] d1,
+    input [3:0] d2,
+    input [3:0] d3,
+    input [3:0] dp_in, //小数点控制
+    output reg [5:0] sel,   //片选
+    output reg [7:0] dig  //段选
+    );
+
+	localparam N = 16; //使用低16位对50Mhz的时钟进行分频(50MHZ/2^16)
+	localparam
+    NUM0 = ~8'h3f,
+    NUM1 = ~8'h06,
+    NUM2 = ~8'h5b,
+    NUM3 = ~8'h4f,
+    NUM4 = ~8'h66,
+    NUM5 = ~8'h6d,
+    NUM6 = ~8'h7d,
+    NUM7 = ~8'h07,
+    NUM8 = ~8'h7f,
+    NUM9 = ~8'h6f,
+    NUMA = ~8'h77,
+    NUMB = ~8'h7c,
+    NUMC = ~8'h39,
+    NUMD = ~8'h5e,
+    NUME = ~8'h79,
+    NUMF = ~8'h71;
+
+
+
+	reg [N-1:0] regN; //高两位作为控制信号，低16位为计数器，对时钟进行分频
+	reg [3:0] hex_in; //段选控制信号
+	reg dp;
+
+	always@(posedge clk or negedge rst_n)
+	begin
+		if(rst_n==0)
+			regN <= 0;
+		else
+			regN <= regN + 1;
+	end
+
+	always@(*) begin
+		case(regN[N-1:N-2])
+            2'b00:begin
+                sel = 6'b111110; //选中第1个数码管
+                hex_in = d0; //数码管显示的数字由hex_in控制，显示d0输入的数字；
+                dp = dp_in[0]; //控制该数码管的小数点的亮灭
+            end
+            2'b01:begin
+                sel = 6'b111101; //选中第二个数码管
+                hex_in = d1;
+                dp = dp_in[1];
+            end
+            2'b10:begin
+                sel = 6'b111011;
+                hex_in = d2;
+                dp = dp_in[2];
+            end
+            default:begin
+                sel = 6'b110111;
+                hex_in = d3;
+                dp = dp_in[3];
+            end
+		endcase
+	end
+
+
+	always@(posedge clk) begin
+		case(hex_in)
+			4'h0: dig[7:0] = NUM0;
+			4'h1: dig[7:0] = NUM1;
+			4'h2: dig[7:0] = NUM2;
+			4'h3: dig[7:0] = NUM3;
+			4'h4: dig[7:0] = NUM4;
+			4'h5: dig[7:0] = NUM5;
+			4'h6: dig[7:0] = NUM6;
+			4'h7: dig[7:0] = NUM7;
+			4'h8: dig[7:0] = NUM8;
+			4'h9: dig[7:0] = NUM9;
+			4'ha: dig[7:0] = NUMA;
+			4'hb: dig[7:0] = NUMB;
+			4'hc: dig[7:0] = NUMC;
+			4'hd: dig[7:0] = NUMD;
+			4'he: dig[7:0] = NUME;
+			default: dig[6:0] = 7'b0111000;
+		endcase
+		dig[7] = dp;
+	end
+endmodule

package/output/npr/npr_plugins/verilog/smg/tb.v

@@ -0,0 +1,56 @@
+`timescale  1ns / 1ps
+
+module tb;
+
+// digital_tube Parameters
+parameter PERIOD  = 10;
+
+
+// digital_tube Inputs
+reg   clk                                  = 0 ;
+reg   rst_n                                = 0 ;
+reg[3:0] d0=4'b0011;
+reg[3:0] d1=4'b0111;
+reg[3:0] d2=4'b1111;
+reg[3:0] d3=4'b1011;
+reg   [3:0]  dp_in                         = 0 ;
+
+// digital_tube Outputs
+wire  [3:0]  sel                           ;
+wire  [7:0]  dig                           ;
+
+
+initial begin
+    forever #(PERIOD/2)  clk=~clk;
+
+end
+
+
+initial begin
+    #(PERIOD*2)
+    rst_n  =  1;
+    d0=4'b0001;
+    #(PERIOD*2)
+    d0=4'b0011;
+    #(PERIOD*2)
+    d0=4'b0110;
+    #(PERIOD*2)
+    d0=4'b0111;
+end
+
+
+digital_tube  u_digital_tube (
+    .clk                     ( clk          ),
+    .rst_n                   ( rst_n        ),
+    .d0                      ( d0 ),
+    .d1                      ( d1 ),
+    .d2                      ( d2 ),
+    .d3                      ( d3 ),
+    .dp_in                   ( d3 ),
+    .sel                     (sel),
+    .dig                     (dig )
+);
+
+
+endmodule
+

package/output/npr/npr_plugins/verilog/uart/calc.js

@@ -0,0 +1,4 @@
+CLK_FREQ=50000000
+UART_BPS=960000
+N=CLK_FREQ/UART_BPS
+console.log(2*N)

package/output/npr/npr_plugins/verilog/uart/tb.v

@@ -0,0 +1,35 @@
+`timescale  1ns / 1ns
+
+module tb;
+
+// digital_tube Parameters
+parameter PERIOD  = 2;
+
+
+// digital_tube Inputs
+reg   clk                                  = 0 ;
+reg   rst_n                                = 1 ;
+wire  txd;
+
+initial begin
+    forever #(PERIOD/2)  clk=~clk;
+end
+
+
+initial begin
+    #(PERIOD*2)
+    rst_n  =  0;
+    #(PERIOD*2)
+    rst_n  =  1;
+end
+
+
+top_UART_TX  u_top_UART_TX (
+    .sys_clk                     ( clk          ),
+    .sys_rst_n                   ( rst_n        ),
+    .txd                      ( txd )
+);
+
+
+endmodule
+

package/output/npr/npr_plugins/verilog/uart/top_UART_RX.v

@@ -0,0 +1,37 @@
+`timescale 1ns / 1ns
+module top_UART_RX
+(
+    input sys_clk,
+    input sys_rst_n,
+    input rxd,
+	//write wire
+    output wire [7:0] led_output
+);
+
+wire [7:0] rxd_data;
+/****************************************
+  *  			Main Code
+  *  			主要代码
+ ****************************************/
+
+ //串口接收模块
+uart_rx u_uart_recv
+(
+    .sys_clk        (sys_clk),
+    .sys_rst_n      (sys_rst_n),
+
+    .uart_rxd       (rxd),
+    .uart_data      (rxd_data)
+);
+
+//LED灯
+uart_rx_led u_uart_rx_led
+(
+    .input_led (rxd_data),
+    .output_led (led_output),
+    .sys_clk (sys_clk),
+    .sys_rst_n (sys_rst_n)
+);
+
+
+endmodule