circuit-json-to-spice 0.0.23 → 0.0.25
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/index.js +2 -2
- package/lib/circuitJsonToSpice.ts +1 -1
- package/package.json +1 -1
- package/tests/examples/ac-voltage-source.test.tsx +2 -21
- package/tests/examples/assets/AC-voltage-source.json +474 -0
- package/tests/examples/assets/Boost-converter-circuit.json +1739 -0
- package/tests/examples/assets/circuit-with-multiple-components.json +558 -0
- package/tests/examples/assets/circuit-with-unrelated-voltage-source-components.json +3890 -0
- package/tests/examples/assets/circuit1-simple-resistor-divider.json +298 -0
- package/tests/examples/assets/example01.json +301 -0
- package/tests/examples/assets/simple-resistor-divider.json +1620 -0
- package/tests/examples/boost-converter.test.tsx +2 -71
- package/tests/examples/circuit1.test.tsx +4 -32
- package/tests/examples/circuit2.test.tsx +2 -45
- package/tests/examples/example01.test.tsx +3 -22
- package/tests/examples/voltage-divider.test.tsx +2 -49
- package/tests/unit/assets/RC-circuit-with-trace.json +354 -0
- package/tests/unit/assets/circuit-with-simulation-voltage-source.json +978 -0
- package/tests/unit/assets/single-resistor-circuit.json +190 -0
- package/tests/unit/circuit-json-conversion.test.tsx +7 -57
- package/tests/unit/voltage-probe.test.ts +8 -8
- package/tests/fixtures/getTestFixture.tsx +0 -7
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import { test, expect } from "bun:test"
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import { sel } from "tscircuit"
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import { getTestFixture } from "tests/fixtures/getTestFixture"
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import { circuitJsonToSpice } from "lib/circuitJsonToSpice"
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import {
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convertCircuitJsonToSchematicSvg,
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convertCircuitJsonToPcbSvg,
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} from "circuit-to-svg"
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import boostConverterCircuit from "./assets/Boost-converter-circuit.json"
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test(
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"Boost converter circuit",
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async () => {
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const
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circuit.add(
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<board width={30} height={30}>
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<voltagesource
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name="V1"
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voltage={"5V"}
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schY={2}
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schX={-5}
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schRotation={270}
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/>
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<trace from={".V1 > .pin1"} to={".L1 > .pin1"} />
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<trace from={".L1 > .pin2"} to={".D1 > .anode"} />
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<trace from={".D1 > .cathode"} to={".C1 > .pin1"} />
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<trace from={".D1 > .cathode"} to={".R1 > .pin1"} />
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<trace from={".C1 > .pin2"} to={".R1 > .pin2"} />
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<trace from={".R1 > .pin2"} to={".V1 > .pin2"} />
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<trace from={".L1 > .pin2"} to={".M1 > .drain"} />
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<trace from={".M1 > .source"} to={".V1 > .pin2"} />
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<trace from={".M1 > .source"} to={"net.GND"} />
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<trace from={".M1 > .gate"} to={".V2 > .pin1"} />
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<trace from={".V2 > .pin2"} to={".V1 > .pin2"} />
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<inductor name="L1" inductance={"1H"} schY={3} pcbY={3} />
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<diode
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name="D1"
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footprint={"0603"}
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schY={3}
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schX={3}
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pcbY={6}
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pcbX={3}
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/>
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<capacitor
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polarized
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schRotation={270}
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name="C1"
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capacitance={"10uF"}
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footprint={"0603"}
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schX={3}
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pcbX={3}
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/>
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<resistor
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schRotation={270}
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name="R1"
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resistance={"1k"}
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footprint={"0603"}
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schX={6}
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pcbX={9}
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/>
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<voltagesource
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name="V2"
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schRotation={270}
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voltage={"10V"}
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waveShape="square"
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dutyCycle={0.68}
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frequency={"1kHz"}
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schX={-3}
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/>
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<mosfet
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channelType="n"
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footprint={"sot23"}
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name="M1"
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mosfetMode="enhancement"
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pcbX={-4}
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/>
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</board>,
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)
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await circuit.renderUntilSettled()
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const circuitJson = circuit.getCircuitJson()
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const circuitJson = boostConverterCircuit as any
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const spiceNetlist = circuitJsonToSpice(circuitJson)
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const spiceString = spiceNetlist.toSpiceString()
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import { test, expect } from "bun:test"
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import { sel } from "tscircuit"
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import { getTestFixture } from "tests/fixtures/getTestFixture"
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import { circuitJsonToSpice } from "lib/circuitJsonToSpice"
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import circuitWithMultipleComponents from "./assets/circuit-with-multiple-components.json"
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import circuit1SimpleResistorDivider from "./assets/circuit1-simple-resistor-divider.json"
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test("circuit with multiple components", async () => {
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const
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circuit.add(
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<board>
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<resistor name="R1" resistance="10k" />
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<resistor name="R2" resistance="5.6k" />
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<capacitor name="C1" capacitance="100nF" />
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<capacitor name="C2" capacitance="1uF" />
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{/* Connect components */}
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<trace from={sel.R1.pin1} to={sel.C1.pin1} />
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<trace from={sel.R1.pin2} to={sel.R2.pin1} />
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<trace from={sel.R2.pin2} to={sel.C2.pin1} />
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</board>,
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)
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await circuit.renderUntilSettled()
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const circuitJson = circuit.getCircuitJson()
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const circuitJson = circuitWithMultipleComponents as any
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const spiceNetlist = circuitJsonToSpice(circuitJson)
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const spiceString = spiceNetlist.toSpiceString()
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})
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test("simple resistor divider", async () => {
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const
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circuit.add(
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<board>
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<resistor name="R1" resistance="1k" />
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<resistor name="R2" resistance="2k" />
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<trace from={sel.R1.pin2} to={sel.R2.pin1} />
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</board>,
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)
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await circuit.renderUntilSettled()
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const circuitJson = circuit.getCircuitJson()
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const circuitJson = circuit1SimpleResistorDivider as any
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const spiceNetlist = circuitJsonToSpice(circuitJson)
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const spiceString = spiceNetlist.toSpiceString()
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import { test, expect } from "bun:test"
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import { sel } from "tscircuit"
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import { getTestFixture } from "tests/fixtures/getTestFixture"
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import { circuitJsonToSpice } from "lib/circuitJsonToSpice"
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import circuitWithUnrelatedVoltageSourceComponents from "./assets/circuit-with-unrelated-voltage-source-components.json"
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test("circuit with unrelated voltage_source components", async () => {
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const
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circuit.add(
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<board width="20mm" height="20mm">
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<resistor name="R1_Test" resistance="10k" footprint="0402" />
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<chip name="U1_Test" footprint="soic8" />
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<trace from=".R1_Test > .pin1" to="net.SCL" />
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<trace from="net.VCC" to=".U1_Test > .pin1" />
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<chip
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name="U_REG"
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footprint="soic8"
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pinLabels={{
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pin2: "GND",
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pin3: "VOUT",
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}}
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pinAttributes={{
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VOUT: { providesPower: true, providesVoltage: 3.3 },
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GND: { providesGround: true },
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}}
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/>
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<chip
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name="U_MCU"
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footprint="soic8"
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pinLabels={{
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pin8: "VCC",
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pin4: "GND",
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}}
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/>
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<trace from=".U_REG > .VOUT" to="net.V_3V3" />
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<trace from=".U_REG > .GND" to="net.GND" />
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<trace from=".U_MCU > .VCC" to="net.V_3V3" />
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<trace from=".U_MCU > .GND" to="net.GND" />
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<resistor name="R2_Test" resistance="10k" footprint="0402" />
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<chip name="U2_Test" footprint="soic8" />
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<trace from=".R2_Test > .pin1" to=".U_MCU > .GND" />
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<trace from=".R2_Test > .pin2" to=".R1_Test > .pin1" />
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<trace from=".U_REG > .VOUT" to=".R1_Test > .pin2" />
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</board>,
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)
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await circuit.renderUntilSettled()
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const circuitJson = circuit.getCircuitJson()
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const circuitJson = circuitWithUnrelatedVoltageSourceComponents as any
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const spiceNetlist = circuitJsonToSpice(circuitJson)
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const spiceString = spiceNetlist.toSpiceString()
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expect(spiceString).toMatchInlineSnapshot(`
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import { test, expect } from "bun:test"
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import {
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import
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import { convertSpiceNetlistToString } from "lib/spice-utils/convertSpiceNetlistToString"
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import { circuitJsonToSpice } from "lib/circuitJsonToSpice"
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import example01 from "./assets/example01.json"
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test("example01", async () => {
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circuit.add(
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<board>
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<resistor name="R1" resistance="1k" />
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<capacitor
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name="C1"
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capacitance="1uF"
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connections={{
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pin1: sel.R1.pin1,
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}}
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/>
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</board>,
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)
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await circuit.renderUntilSettled()
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const circuitJson = circuit.getCircuitJson()
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const circuitJson = example01 as any
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// Convert circuit JSON to SPICE
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const { circuitJsonToSpice } = await import("lib/circuitJsonToSpice")
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const spiceNetlist = circuitJsonToSpice(circuitJson)
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const spiceString = spiceNetlist.toSpiceString()
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import { test, expect } from "bun:test"
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import { sel } from "tscircuit"
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import { getTestFixture } from "tests/fixtures/getTestFixture"
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import { circuitJsonToSpice } from "lib/circuitJsonToSpice"
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import simpleResistorDivider from "./assets/simple-resistor-divider.json"
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test("simple resistor divider", async () => {
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circuit.add(
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<board width={16} height={16}>
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<chip
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name="V1"
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footprint="sot23"
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pinLabels={{
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pin1: "VOUT",
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pin2: "GND",
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}}
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pinAttributes={{
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VOUT: { providesPower: true, providesVoltage: 5 },
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GND: { providesGround: true },
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}}
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/>
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<resistor name="R1" resistance="1k" footprint="0402" pcbX={4} pcbY={4} />
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<resistor
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name="R2"
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resistance="2k"
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footprint="0402"
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pcbX={-4}
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pcbY={-4}
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/>
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<capacitor
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name="C1"
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capacitance="10uF"
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footprint="0402"
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pcbX={0}
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pcbY={-2}
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/>
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<trace from={"net.VOUT"} to={sel.R1.pin1} />
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<trace from={".V1 > .VOUT"} to={"net.VOUT"} />
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<trace from={sel.R1.pin2} to={sel.R2.pin1} />
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<trace from={sel.R2.pin2} to={"net.GND"} />
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<trace from={"net.GND"} to={".V1 > .GND"} />
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<trace from={sel.C1.pin1} to={sel.R1.pin2} />
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<trace from={sel.C1.pin2} to={"net.GND"} />
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</board>,
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)
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await circuit.renderUntilSettled()
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const circuitJson = circuit.getCircuitJson()
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const circuitJson = simpleResistorDivider as any
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const spiceNetlist = circuitJsonToSpice(circuitJson)
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const spiceString = spiceNetlist.toSpiceString()
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expect(spiceString).toMatchInlineSnapshot(`
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[
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{
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"type": "source_project_metadata",
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"source_project_metadata_id": "source_project_metadata_0",
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"software_used_string": "@tscircuit/core@0.0.874"
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},
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{
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"type": "source_group",
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"source_group_id": "source_group_0",
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|
+
"is_subcircuit": true,
|
|
11
|
+
"was_automatically_named": true,
|
|
12
|
+
"subcircuit_id": "subcircuit_source_group_0"
|
|
13
|
+
},
|
|
14
|
+
{
|
|
15
|
+
"type": "source_port",
|
|
16
|
+
"source_port_id": "source_port_0",
|
|
17
|
+
"name": "pin1",
|
|
18
|
+
"pin_number": 1,
|
|
19
|
+
"port_hints": ["pin1", "anode", "pos", "left", "1"],
|
|
20
|
+
"source_component_id": "source_component_0",
|
|
21
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
22
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net1"
|
|
23
|
+
},
|
|
24
|
+
{
|
|
25
|
+
"type": "source_port",
|
|
26
|
+
"source_port_id": "source_port_1",
|
|
27
|
+
"name": "pin2",
|
|
28
|
+
"pin_number": 2,
|
|
29
|
+
"port_hints": ["pin2", "cathode", "neg", "right", "2"],
|
|
30
|
+
"source_component_id": "source_component_0",
|
|
31
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
32
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net0"
|
|
33
|
+
},
|
|
34
|
+
{
|
|
35
|
+
"type": "source_component",
|
|
36
|
+
"source_component_id": "source_component_0",
|
|
37
|
+
"ftype": "simple_resistor",
|
|
38
|
+
"name": "R1",
|
|
39
|
+
"resistance": 1000,
|
|
40
|
+
"display_resistance": "1kΩ",
|
|
41
|
+
"are_pins_interchangeable": true,
|
|
42
|
+
"source_group_id": "source_group_0"
|
|
43
|
+
},
|
|
44
|
+
{
|
|
45
|
+
"type": "source_port",
|
|
46
|
+
"source_port_id": "source_port_2",
|
|
47
|
+
"name": "pin1",
|
|
48
|
+
"pin_number": 1,
|
|
49
|
+
"port_hints": ["pin1", "pos", "1"],
|
|
50
|
+
"source_component_id": "source_component_1",
|
|
51
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
52
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net0"
|
|
53
|
+
},
|
|
54
|
+
{
|
|
55
|
+
"type": "source_port",
|
|
56
|
+
"source_port_id": "source_port_3",
|
|
57
|
+
"name": "pin2",
|
|
58
|
+
"pin_number": 2,
|
|
59
|
+
"port_hints": ["pin2", "neg", "2"],
|
|
60
|
+
"source_component_id": "source_component_1",
|
|
61
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
62
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net2"
|
|
63
|
+
},
|
|
64
|
+
{
|
|
65
|
+
"type": "source_component",
|
|
66
|
+
"source_component_id": "source_component_1",
|
|
67
|
+
"ftype": "simple_capacitor",
|
|
68
|
+
"name": "C1",
|
|
69
|
+
"capacitance": 0.000001,
|
|
70
|
+
"display_capacitance": "1uF",
|
|
71
|
+
"are_pins_interchangeable": true,
|
|
72
|
+
"source_group_id": "source_group_0"
|
|
73
|
+
},
|
|
74
|
+
{
|
|
75
|
+
"type": "source_net",
|
|
76
|
+
"source_net_id": "source_net_0",
|
|
77
|
+
"name": "GND1",
|
|
78
|
+
"member_source_group_ids": [],
|
|
79
|
+
"is_ground": true,
|
|
80
|
+
"is_power": false,
|
|
81
|
+
"is_positive_voltage_source": false,
|
|
82
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
83
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net1"
|
|
84
|
+
},
|
|
85
|
+
{
|
|
86
|
+
"type": "source_net",
|
|
87
|
+
"source_net_id": "source_net_1",
|
|
88
|
+
"name": "GND2",
|
|
89
|
+
"member_source_group_ids": [],
|
|
90
|
+
"is_ground": true,
|
|
91
|
+
"is_power": false,
|
|
92
|
+
"is_positive_voltage_source": false,
|
|
93
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
94
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net2"
|
|
95
|
+
},
|
|
96
|
+
{
|
|
97
|
+
"type": "source_board",
|
|
98
|
+
"source_board_id": "source_board_0",
|
|
99
|
+
"source_group_id": "source_group_0"
|
|
100
|
+
},
|
|
101
|
+
{
|
|
102
|
+
"type": "source_trace",
|
|
103
|
+
"source_trace_id": "source_trace_0",
|
|
104
|
+
"connected_source_port_ids": ["source_port_1", "source_port_2"],
|
|
105
|
+
"connected_source_net_ids": [],
|
|
106
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
107
|
+
"max_length": null,
|
|
108
|
+
"display_name": ".R1 > .pin2 to .C1 > .pin1",
|
|
109
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net0"
|
|
110
|
+
},
|
|
111
|
+
{
|
|
112
|
+
"type": "source_trace",
|
|
113
|
+
"source_trace_id": "source_trace_1",
|
|
114
|
+
"connected_source_port_ids": ["source_port_0"],
|
|
115
|
+
"connected_source_net_ids": ["source_net_0"],
|
|
116
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
117
|
+
"display_name": ".R1 > .pin1 to net.GND1",
|
|
118
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net1"
|
|
119
|
+
},
|
|
120
|
+
{
|
|
121
|
+
"type": "source_trace",
|
|
122
|
+
"source_trace_id": "source_trace_2",
|
|
123
|
+
"connected_source_port_ids": ["source_port_3"],
|
|
124
|
+
"connected_source_net_ids": ["source_net_1"],
|
|
125
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
126
|
+
"max_length": null,
|
|
127
|
+
"display_name": ".C1 > .pin2 to net.GND2",
|
|
128
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net2"
|
|
129
|
+
},
|
|
130
|
+
{
|
|
131
|
+
"type": "schematic_component",
|
|
132
|
+
"schematic_component_id": "schematic_component_0",
|
|
133
|
+
"center": {
|
|
134
|
+
"x": 0,
|
|
135
|
+
"y": 0
|
|
136
|
+
},
|
|
137
|
+
"size": {
|
|
138
|
+
"width": 1.1,
|
|
139
|
+
"height": 0.388910699999999
|
|
140
|
+
},
|
|
141
|
+
"source_component_id": "source_component_0",
|
|
142
|
+
"is_box_with_pins": true,
|
|
143
|
+
"symbol_name": "boxresistor_right",
|
|
144
|
+
"symbol_display_value": "1kΩ",
|
|
145
|
+
"schematic_group_id": "schematic_group_0"
|
|
146
|
+
},
|
|
147
|
+
{
|
|
148
|
+
"type": "schematic_component",
|
|
149
|
+
"schematic_component_id": "schematic_component_1",
|
|
150
|
+
"center": {
|
|
151
|
+
"x": 1.8000000000000003,
|
|
152
|
+
"y": 0
|
|
153
|
+
},
|
|
154
|
+
"size": {
|
|
155
|
+
"width": 1.1,
|
|
156
|
+
"height": 0.84
|
|
157
|
+
},
|
|
158
|
+
"source_component_id": "source_component_1",
|
|
159
|
+
"is_box_with_pins": true,
|
|
160
|
+
"symbol_name": "capacitor_right",
|
|
161
|
+
"symbol_display_value": "1uF",
|
|
162
|
+
"schematic_group_id": "schematic_group_0"
|
|
163
|
+
},
|
|
164
|
+
{
|
|
165
|
+
"type": "schematic_group",
|
|
166
|
+
"schematic_group_id": "schematic_group_0",
|
|
167
|
+
"is_subcircuit": true,
|
|
168
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
169
|
+
"name": "unnamed_board1",
|
|
170
|
+
"center": {
|
|
171
|
+
"x": 0,
|
|
172
|
+
"y": 0
|
|
173
|
+
},
|
|
174
|
+
"width": 0,
|
|
175
|
+
"height": 0,
|
|
176
|
+
"schematic_component_ids": [],
|
|
177
|
+
"source_group_id": "source_group_0"
|
|
178
|
+
},
|
|
179
|
+
{
|
|
180
|
+
"type": "schematic_port",
|
|
181
|
+
"schematic_port_id": "schematic_port_0",
|
|
182
|
+
"schematic_component_id": "schematic_component_0",
|
|
183
|
+
"center": {
|
|
184
|
+
"x": -0.55,
|
|
185
|
+
"y": 0
|
|
186
|
+
},
|
|
187
|
+
"source_port_id": "source_port_0",
|
|
188
|
+
"facing_direction": "left",
|
|
189
|
+
"distance_from_component_edge": 0.4,
|
|
190
|
+
"pin_number": 1,
|
|
191
|
+
"display_pin_label": "anode",
|
|
192
|
+
"is_connected": false
|
|
193
|
+
},
|
|
194
|
+
{
|
|
195
|
+
"type": "schematic_port",
|
|
196
|
+
"schematic_port_id": "schematic_port_1",
|
|
197
|
+
"schematic_component_id": "schematic_component_0",
|
|
198
|
+
"center": {
|
|
199
|
+
"x": 0.55,
|
|
200
|
+
"y": 0
|
|
201
|
+
},
|
|
202
|
+
"source_port_id": "source_port_1",
|
|
203
|
+
"facing_direction": "right",
|
|
204
|
+
"distance_from_component_edge": 0.4,
|
|
205
|
+
"pin_number": 2,
|
|
206
|
+
"display_pin_label": "cathode",
|
|
207
|
+
"is_connected": true
|
|
208
|
+
},
|
|
209
|
+
{
|
|
210
|
+
"type": "schematic_port",
|
|
211
|
+
"schematic_port_id": "schematic_port_2",
|
|
212
|
+
"schematic_component_id": "schematic_component_1",
|
|
213
|
+
"center": {
|
|
214
|
+
"x": 1.2500000000000002,
|
|
215
|
+
"y": 0
|
|
216
|
+
},
|
|
217
|
+
"source_port_id": "source_port_2",
|
|
218
|
+
"facing_direction": "left",
|
|
219
|
+
"distance_from_component_edge": 0.4,
|
|
220
|
+
"pin_number": 1,
|
|
221
|
+
"display_pin_label": "pos",
|
|
222
|
+
"is_connected": true
|
|
223
|
+
},
|
|
224
|
+
{
|
|
225
|
+
"type": "schematic_port",
|
|
226
|
+
"schematic_port_id": "schematic_port_3",
|
|
227
|
+
"schematic_component_id": "schematic_component_1",
|
|
228
|
+
"center": {
|
|
229
|
+
"x": 2.3500000000000005,
|
|
230
|
+
"y": 0
|
|
231
|
+
},
|
|
232
|
+
"source_port_id": "source_port_3",
|
|
233
|
+
"facing_direction": "right",
|
|
234
|
+
"distance_from_component_edge": 0.4,
|
|
235
|
+
"pin_number": 2,
|
|
236
|
+
"display_pin_label": "neg",
|
|
237
|
+
"is_connected": false
|
|
238
|
+
},
|
|
239
|
+
{
|
|
240
|
+
"type": "schematic_trace",
|
|
241
|
+
"schematic_trace_id": "schematic_trace_0",
|
|
242
|
+
"source_trace_id": "solver_R1.2-C1.1",
|
|
243
|
+
"edges": [
|
|
244
|
+
{
|
|
245
|
+
"from": {
|
|
246
|
+
"x": 0.55,
|
|
247
|
+
"y": 0
|
|
248
|
+
},
|
|
249
|
+
"to": {
|
|
250
|
+
"x": 1.25,
|
|
251
|
+
"y": 0
|
|
252
|
+
}
|
|
253
|
+
}
|
|
254
|
+
],
|
|
255
|
+
"junctions": [],
|
|
256
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit17_connectivity_net0"
|
|
257
|
+
},
|
|
258
|
+
{
|
|
259
|
+
"type": "schematic_net_label",
|
|
260
|
+
"schematic_net_label_id": "schematic_net_label_0",
|
|
261
|
+
"text": "GND1",
|
|
262
|
+
"anchor_position": {
|
|
263
|
+
"x": -0.55,
|
|
264
|
+
"y": 0
|
|
265
|
+
},
|
|
266
|
+
"center": {
|
|
267
|
+
"x": -0.75,
|
|
268
|
+
"y": 0
|
|
269
|
+
},
|
|
270
|
+
"anchor_side": "right",
|
|
271
|
+
"source_net_id": "source_net_0"
|
|
272
|
+
},
|
|
273
|
+
{
|
|
274
|
+
"type": "schematic_net_label",
|
|
275
|
+
"schematic_net_label_id": "schematic_net_label_1",
|
|
276
|
+
"text": "GND2",
|
|
277
|
+
"anchor_position": {
|
|
278
|
+
"x": 2.3500000000000005,
|
|
279
|
+
"y": 0
|
|
280
|
+
},
|
|
281
|
+
"center": {
|
|
282
|
+
"x": 2.5500000000000007,
|
|
283
|
+
"y": 0
|
|
284
|
+
},
|
|
285
|
+
"anchor_side": "left",
|
|
286
|
+
"source_net_id": "source_net_1"
|
|
287
|
+
},
|
|
288
|
+
{
|
|
289
|
+
"type": "pcb_component",
|
|
290
|
+
"pcb_component_id": "pcb_component_0",
|
|
291
|
+
"center": {
|
|
292
|
+
"x": 0,
|
|
293
|
+
"y": 0
|
|
294
|
+
},
|
|
295
|
+
"width": 0,
|
|
296
|
+
"height": 0,
|
|
297
|
+
"layer": "top",
|
|
298
|
+
"rotation": 0,
|
|
299
|
+
"source_component_id": "source_component_0",
|
|
300
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
301
|
+
"do_not_place": false,
|
|
302
|
+
"obstructs_within_bounds": true
|
|
303
|
+
},
|
|
304
|
+
{
|
|
305
|
+
"type": "pcb_missing_footprint_error",
|
|
306
|
+
"pcb_missing_footprint_error_id": "pcb_missing_footprint_error_0",
|
|
307
|
+
"message": "No footprint found for component: <resistor#8 name=\".R1\" />",
|
|
308
|
+
"source_component_id": "source_component_0",
|
|
309
|
+
"error_type": "pcb_missing_footprint_error"
|
|
310
|
+
},
|
|
311
|
+
{
|
|
312
|
+
"type": "pcb_component",
|
|
313
|
+
"pcb_component_id": "pcb_component_1",
|
|
314
|
+
"center": {
|
|
315
|
+
"x": null,
|
|
316
|
+
"y": null
|
|
317
|
+
},
|
|
318
|
+
"width": 0,
|
|
319
|
+
"height": 0,
|
|
320
|
+
"layer": "top",
|
|
321
|
+
"rotation": 0,
|
|
322
|
+
"source_component_id": "source_component_1",
|
|
323
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
324
|
+
"do_not_place": false,
|
|
325
|
+
"obstructs_within_bounds": true
|
|
326
|
+
},
|
|
327
|
+
{
|
|
328
|
+
"type": "pcb_missing_footprint_error",
|
|
329
|
+
"pcb_missing_footprint_error_id": "pcb_missing_footprint_error_1",
|
|
330
|
+
"message": "No footprint found for component: <capacitor#11 name=\".C1\" />",
|
|
331
|
+
"source_component_id": "source_component_1",
|
|
332
|
+
"error_type": "pcb_missing_footprint_error"
|
|
333
|
+
},
|
|
334
|
+
{
|
|
335
|
+
"type": "pcb_board",
|
|
336
|
+
"pcb_board_id": "pcb_board_0",
|
|
337
|
+
"center": {
|
|
338
|
+
"x": 0,
|
|
339
|
+
"y": 0
|
|
340
|
+
},
|
|
341
|
+
"thickness": 1.4,
|
|
342
|
+
"num_layers": 2,
|
|
343
|
+
"width": 0,
|
|
344
|
+
"height": 0,
|
|
345
|
+
"material": "fr4"
|
|
346
|
+
},
|
|
347
|
+
{
|
|
348
|
+
"type": "pcb_autorouting_error",
|
|
349
|
+
"pcb_autorouting_error_id": "pcb_autorouting_error_0",
|
|
350
|
+
"pcb_error_id": "pcb_autorouter_error_subcircuit_subcircuit_source_group_0",
|
|
351
|
+
"error_type": "pcb_autorouting_error",
|
|
352
|
+
"message": "undefined is not an object (evaluating 'this.nodeEdgeMap.get(t.capacityMeshNodeId).some') (capacity-autorouter@0.0.140)"
|
|
353
|
+
}
|
|
354
|
+
]
|