circuit-json-to-spice 0.0.23 → 0.0.25

package/tests/unit/assets/single-resistor-circuit.json

@@ -0,0 +1,190 @@
+[
+  {
+    "type": "source_project_metadata",
+    "source_project_metadata_id": "source_project_metadata_0",
+    "software_used_string": "@tscircuit/core@0.0.874"
+  },
+  {
+    "type": "source_group",
+    "source_group_id": "source_group_0",
+    "is_subcircuit": true,
+    "was_automatically_named": true,
+    "subcircuit_id": "subcircuit_source_group_0"
+  },
+  {
+    "type": "source_port",
+    "source_port_id": "source_port_0",
+    "name": "pin1",
+    "pin_number": 1,
+    "port_hints": ["pin1", "anode", "pos", "left", "1"],
+    "source_component_id": "source_component_0",
+    "subcircuit_id": "subcircuit_source_group_0"
+  },
+  {
+    "type": "source_port",
+    "source_port_id": "source_port_1",
+    "name": "pin2",
+    "pin_number": 2,
+    "port_hints": ["pin2", "cathode", "neg", "right", "2"],
+    "source_component_id": "source_component_0",
+    "subcircuit_id": "subcircuit_source_group_0",
+    "subcircuit_connectivity_map_key": "unnamedsubcircuit4_connectivity_net0"
+  },
+  {
+    "type": "source_component",
+    "source_component_id": "source_component_0",
+    "ftype": "simple_resistor",
+    "name": "R1",
+    "resistance": 1000,
+    "display_resistance": "1kΩ",
+    "are_pins_interchangeable": true,
+    "source_group_id": "source_group_0"
+  },
+  {
+    "type": "source_net",
+    "source_net_id": "source_net_0",
+    "name": "GND",
+    "member_source_group_ids": [],
+    "is_ground": true,
+    "is_power": false,
+    "is_positive_voltage_source": false,
+    "subcircuit_id": "subcircuit_source_group_0",
+    "subcircuit_connectivity_map_key": "unnamedsubcircuit4_connectivity_net0"
+  },
+  {
+    "type": "source_board",
+    "source_board_id": "source_board_0",
+    "source_group_id": "source_group_0"
+  },
+  {
+    "type": "source_trace",
+    "source_trace_id": "source_trace_0",
+    "connected_source_port_ids": ["source_port_1"],
+    "connected_source_net_ids": ["source_net_0"],
+    "subcircuit_id": "subcircuit_source_group_0",
+    "display_name": ".R1 > .pin2 to net.GND",
+    "subcircuit_connectivity_map_key": "unnamedsubcircuit4_connectivity_net0"
+  },
+  {
+    "type": "source_pin_missing_trace_warning",
+    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_0",
+    "message": "Port pin1 on R1 is missing a trace",
+    "source_component_id": "source_component_0",
+    "source_port_id": "source_port_0",
+    "subcircuit_id": "subcircuit_source_group_0",
+    "warning_type": "source_pin_missing_trace_warning"
+  },
+  {
+    "type": "schematic_component",
+    "schematic_component_id": "schematic_component_0",
+    "center": {
+      "x": 0,
+      "y": 0
+    },
+    "size": {
+      "width": 1.1,
+      "height": 0.388910699999999
+    },
+    "source_component_id": "source_component_0",
+    "is_box_with_pins": true,
+    "symbol_name": "boxresistor_right",
+    "symbol_display_value": "1kΩ",
+    "schematic_group_id": "schematic_group_0"
+  },
+  {
+    "type": "schematic_group",
+    "schematic_group_id": "schematic_group_0",
+    "is_subcircuit": true,
+    "subcircuit_id": "subcircuit_source_group_0",
+    "name": "unnamed_board1",
+    "center": {
+      "x": 0,
+      "y": 0
+    },
+    "width": 0,
+    "height": 0,
+    "schematic_component_ids": [],
+    "source_group_id": "source_group_0"
+  },
+  {
+    "type": "schematic_port",
+    "schematic_port_id": "schematic_port_0",
+    "schematic_component_id": "schematic_component_0",
+    "center": {
+      "x": -0.55,
+      "y": 0
+    },
+    "source_port_id": "source_port_0",
+    "facing_direction": "left",
+    "distance_from_component_edge": 0.4,
+    "pin_number": 1,
+    "display_pin_label": "anode",
+    "is_connected": false
+  },
+  {
+    "type": "schematic_port",
+    "schematic_port_id": "schematic_port_1",
+    "schematic_component_id": "schematic_component_0",
+    "center": {
+      "x": 0.55,
+      "y": 0
+    },
+    "source_port_id": "source_port_1",
+    "facing_direction": "right",
+    "distance_from_component_edge": 0.4,
+    "pin_number": 2,
+    "display_pin_label": "cathode",
+    "is_connected": false
+  },
+  {
+    "type": "schematic_net_label",
+    "schematic_net_label_id": "schematic_net_label_0",
+    "text": "GND",
+    "anchor_position": {
+      "x": 0.55,
+      "y": 0
+    },
+    "center": {
+      "x": 0.7000000000000001,
+      "y": 0
+    },
+    "anchor_side": "left",
+    "source_net_id": "source_net_0"
+  },
+  {
+    "type": "pcb_component",
+    "pcb_component_id": "pcb_component_0",
+    "center": {
+      "x": 0,
+      "y": 0
+    },
+    "width": 0,
+    "height": 0,
+    "layer": "top",
+    "rotation": 0,
+    "source_component_id": "source_component_0",
+    "subcircuit_id": "subcircuit_source_group_0",
+    "do_not_place": false,
+    "obstructs_within_bounds": true
+  },
+  {
+    "type": "pcb_missing_footprint_error",
+    "pcb_missing_footprint_error_id": "pcb_missing_footprint_error_0",
+    "message": "No footprint found for component: <resistor#0 name=\".R1\" />",
+    "source_component_id": "source_component_0",
+    "error_type": "pcb_missing_footprint_error"
+  },
+  {
+    "type": "pcb_board",
+    "pcb_board_id": "pcb_board_0",
+    "center": {
+      "x": 0,
+      "y": 0
+    },
+    "thickness": 1.4,
+    "num_layers": 2,
+    "width": 0,
+    "height": 0,
+    "material": "fr4"
+  }
+]

package/tests/unit/circuit-json-conversion.test.tsx

@@ -1,8 +1,9 @@
 import { test, expect } from "bun:test"
 import { circuitJsonToSpice } from "lib/circuitJsonToSpice"
 import type { AnyCircuitElement } from "circuit-json"
-import { getTestFixture } from "tests/fixtures/getTestFixture"
-import { sel } from "tscircuit"
+import singleResistorCircuit from "./assets/single-resistor-circuit.json"
+import rcCircuitWithTrace from "./assets/RC-circuit-with-trace.json"
+import circuitWithSimulationVoltageSource from "./assets/circuit-with-simulation-voltage-source.json"
 
 test("empty circuit JSON", () => {
   const circuitJson: AnyCircuitElement[] = []
@@ -16,18 +17,7 @@ test("empty circuit JSON", () => {
 })
 
 test("single resistor circuit", async () => {
-  const { circuit } = await getTestFixture()
-
-  circuit.add(
-    <board>
-      <resistor name="R1" resistance="1k" />
-      <trace from="net.GND" to={sel.R1.pin2} />
-    </board>,
-  )
-
-  await circuit.renderUntilSettled()
-
-  const circuitJson = circuit.getCircuitJson()
+  const circuitJson = singleResistorCircuit as any
   const netlist = circuitJsonToSpice(circuitJson)
 
   expect(netlist.components).toHaveLength(1)
@@ -39,21 +29,7 @@ test("single resistor circuit", async () => {
 })
 
 test("RC circuit with trace", async () => {
-  const { circuit } = await getTestFixture()
-
-  circuit.add(
-    <board>
-      <resistor name="R1" resistance="1k" />
-      <capacitor name="C1" capacitance="1uF" />
-      <trace from={sel.R1.pin2} to={sel.C1.pin1} />
-      <trace from="net.GND1" to={sel.R1.pin1} />
-      <trace from="net.GND2" to={sel.C1.pin2} />
-    </board>,
-  )
-
-  await circuit.renderUntilSettled()
-
-  const circuitJson = circuit.getCircuitJson()
+  const circuitJson = rcCircuitWithTrace as any
   const netlist = circuitJsonToSpice(circuitJson)
 
   expect(netlist.components).toHaveLength(2)
@@ -66,33 +42,7 @@ test("RC circuit with trace", async () => {
 })
 
 test("circuit with simulation voltage source", async () => {
-  const { circuit } = await getTestFixture()
-
-  circuit.add(
-    <board>
-      <resistor name="R1" resistance="1k" />
-      <chip
-        name="U1"
-        footprint="soic8"
-        pinLabels={{
-          pin2: "GND",
-          pin3: "VOUT",
-        }}
-        pinAttributes={{
-          VOUT: { providesPower: true, providesVoltage: 5 },
-          GND: { providesGround: true },
-        }}
-      />
-      <trace from={"net.VCC"} to={sel<"VOUT">("U1").VOUT} />
-      <trace from={"net.GND"} to={sel<"GND">("U1").GND} />
-      <trace from={"net.VCC"} to={sel.R1.pin1} />
-      <trace from={"net.GND"} to={sel.R1.pin2} />
-    </board>,
-  )
-
-  await circuit.renderUntilSettled()
-
-  const circuitJson = circuit.getCircuitJson()
+  const circuitJson = circuitWithSimulationVoltageSource as any
   const netlist = circuitJsonToSpice(circuitJson)
 
   expect(netlist.components).toHaveLength(2)
@@ -118,7 +68,7 @@ test("simple switch uses simulation switch control", () => {
       source_component_id: "SW1",
       name: "SW1",
       ftype: "simple_switch",
-    } as AnyCircuitElement,
+    },
     {
       type: "source_net",
       source_net_id: "net_gnd",

package/tests/unit/voltage-probe.test.ts

@@ -81,7 +81,7 @@ test("voltage probe with source_port_id creates .PRINT statement", () => {
   const netlist = circuitJsonToSpice(circuitJson)
   const spiceString = netlist.toSpiceString()
 
-  expect(spiceString).toContain(`.PRINT TRAN V(vout)`)
+  expect(spiceString).toContain(`.PRINT TRAN V(VOUT)`)
   expect(spiceString).toContain(`RR1 N1 VOUT 1K`)
   expect(spiceString).toContain(`RR2 VOUT N2 1K`)
 })
@@ -99,7 +99,7 @@ test("voltage probe with source_net_id creates .PRINT statement", () => {
   const netlist = circuitJsonToSpice(circuitJson)
   const spiceString = netlist.toSpiceString()
 
-  expect(spiceString).toContain(`.PRINT TRAN V(vout)`)
+  expect(spiceString).toContain(`.PRINT TRAN V(VOUT)`)
   expect(spiceString).toContain(`RR1 N1 VOUT 1K`)
   expect(spiceString).toContain(`RR2 VOUT N2 1K`)
 })
@@ -153,7 +153,7 @@ test("voltage probe on ground node is ignored, but other probes are not", () =>
 
   // `R2_p2` is now connected to GND, so it's node 0 and should be ignored
   // `R1_p2` is a non-gnd node and should be printed.
-  expect(spiceString).toContain(`.PRINT TRAN V(vout)`)
+  expect(spiceString).toContain(`.PRINT TRAN V(VOUT)`)
   expect(spiceString).not.toContain("V(0)")
   expect(spiceString).toContain("RR1 N1 VOUT 1K")
   expect(spiceString).toContain("RR2 VOUT 0 1K")
@@ -183,8 +183,8 @@ test("multiple voltage probes create single .PRINT statement", () => {
 
   // The order of probes in the .PRINT statement is not guaranteed
   expect(spiceString).toContain(".PRINT TRAN")
-  expect(spiceString).toContain("V(n1)")
-  expect(spiceString).toContain("V(vout)")
+  expect(spiceString).toContain("V(N1)")
+  expect(spiceString).toContain("V(VOUT)")
 })
 
 test("probes with N-style names don't conflict with auto-generated names", () => {
@@ -367,9 +367,9 @@ test("probes with N-style names don't conflict with auto-generated names", () =>
 
   // The order of probes in the .PRINT statement is not guaranteed
   expect(spiceString).toContain(".PRINT TRAN")
-  expect(spiceString).toContain("V(n1)")
-  expect(spiceString).toContain("V(n2)")
-  expect(spiceString).toContain("V(n4)")
+  expect(spiceString).toContain("V(N1)")
+  expect(spiceString).toContain("V(N2)")
+  expect(spiceString).toContain("V(N4)")
   expect(spiceString).not.toContain("V(n3)")
   expect(spiceString).not.toContain("V(n5)")
 })

package/tests/fixtures/getTestFixture.tsx

@@ -1,7 +0,0 @@
-import { RootCircuit } from "tscircuit"
-
-export const getTestFixture = () => {
-  const circuit = new RootCircuit()
-
-  return { circuit }
-}