circuit-json-to-spice 0.0.23 → 0.0.25
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/index.js +2 -2
- package/lib/circuitJsonToSpice.ts +1 -1
- package/package.json +1 -1
- package/tests/examples/ac-voltage-source.test.tsx +2 -21
- package/tests/examples/assets/AC-voltage-source.json +474 -0
- package/tests/examples/assets/Boost-converter-circuit.json +1739 -0
- package/tests/examples/assets/circuit-with-multiple-components.json +558 -0
- package/tests/examples/assets/circuit-with-unrelated-voltage-source-components.json +3890 -0
- package/tests/examples/assets/circuit1-simple-resistor-divider.json +298 -0
- package/tests/examples/assets/example01.json +301 -0
- package/tests/examples/assets/simple-resistor-divider.json +1620 -0
- package/tests/examples/boost-converter.test.tsx +2 -71
- package/tests/examples/circuit1.test.tsx +4 -32
- package/tests/examples/circuit2.test.tsx +2 -45
- package/tests/examples/example01.test.tsx +3 -22
- package/tests/examples/voltage-divider.test.tsx +2 -49
- package/tests/unit/assets/RC-circuit-with-trace.json +354 -0
- package/tests/unit/assets/circuit-with-simulation-voltage-source.json +978 -0
- package/tests/unit/assets/single-resistor-circuit.json +190 -0
- package/tests/unit/circuit-json-conversion.test.tsx +7 -57
- package/tests/unit/voltage-probe.test.ts +8 -8
- package/tests/fixtures/getTestFixture.tsx +0 -7
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[
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{
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"type": "source_project_metadata",
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"source_project_metadata_id": "source_project_metadata_0",
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"software_used_string": "@tscircuit/core@0.0.874"
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},
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{
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"type": "source_group",
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"source_group_id": "source_group_0",
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"is_subcircuit": true,
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"was_automatically_named": true,
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"subcircuit_id": "subcircuit_source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_0",
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"name": "VOUT",
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"pin_number": 1,
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"port_hints": ["VOUT", "pin1", "1"],
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"source_component_id": "source_component_0",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_1",
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"name": "GND",
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"pin_number": 2,
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"port_hints": ["GND", "pin2", "2"],
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"source_component_id": "source_component_0",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net2"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_2",
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"name": "pin3",
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"pin_number": 3,
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"port_hints": ["pin3", "3"],
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"source_component_id": "source_component_0",
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"subcircuit_id": "subcircuit_source_group_0"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_0",
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"ftype": "simple_chip",
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"name": "V1",
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_3",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "anode", "pos", "left", "1"],
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"source_component_id": "source_component_1",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_4",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "cathode", "neg", "right", "2"],
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"source_component_id": "source_component_1",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net1"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_1",
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"ftype": "simple_resistor",
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"name": "R1",
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"resistance": 1000,
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"display_resistance": "1kΩ",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_5",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "anode", "pos", "left", "1"],
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"source_component_id": "source_component_2",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net1"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_6",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "cathode", "neg", "right", "2"],
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"source_component_id": "source_component_2",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net2"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_2",
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"ftype": "simple_resistor",
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"name": "R2",
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"resistance": 2000,
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"display_resistance": "2kΩ",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_7",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "pos", "anode", "1"],
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"source_component_id": "source_component_3",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net1"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_8",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "neg", "cathode", "2"],
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"source_component_id": "source_component_3",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net2"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_3",
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"ftype": "simple_capacitor",
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"name": "C1",
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"capacitance": 0.00001,
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"display_capacitance": "10uF",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_net",
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"source_net_id": "source_net_0",
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"name": "VOUT",
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"member_source_group_ids": [],
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"is_ground": false,
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"is_power": true,
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"is_positive_voltage_source": true,
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net0"
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},
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{
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"type": "source_net",
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"source_net_id": "source_net_1",
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"name": "GND",
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"member_source_group_ids": [],
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"is_ground": true,
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"is_power": false,
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"is_positive_voltage_source": false,
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net2"
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},
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{
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"type": "source_board",
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"source_board_id": "source_board_0",
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_0",
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"connected_source_port_ids": ["source_port_3"],
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"connected_source_net_ids": ["source_net_0"],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".R1 > .pin1 to net.VOUT",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net0"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_1",
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"connected_source_port_ids": ["source_port_0"],
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"connected_source_net_ids": ["source_net_0"],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".V1 > .VOUT to net.VOUT",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net0"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_2",
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"connected_source_port_ids": ["source_port_4", "source_port_5"],
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"connected_source_net_ids": [],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".R1 > .pin2 to .R2 > .pin1",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net1"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_3",
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"connected_source_port_ids": ["source_port_6"],
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"connected_source_net_ids": ["source_net_1"],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".R2 > .pin2 to net.GND",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net2"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_4",
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"connected_source_port_ids": ["source_port_1"],
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"connected_source_net_ids": ["source_net_1"],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".V1 > .GND to net.GND",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net2"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_5",
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"connected_source_port_ids": ["source_port_7", "source_port_4"],
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"connected_source_net_ids": [],
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"subcircuit_id": "subcircuit_source_group_0",
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"max_length": null,
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"display_name": ".C1 > .pin1 to .R1 > .pin2",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net1"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_6",
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"connected_source_port_ids": ["source_port_8"],
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"connected_source_net_ids": ["source_net_1"],
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"subcircuit_id": "subcircuit_source_group_0",
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"max_length": null,
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"display_name": ".C1 > .pin2 to net.GND",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit1573_connectivity_net2"
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},
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{
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"type": "simulation_voltage_source",
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"simulation_voltage_source_id": "simulation_voltage_source_0",
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"positive_source_port_id": "source_port_0",
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"positive_source_net_id": "source_net_0",
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"negative_source_port_id": "source_port_1",
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"negative_source_net_id": "source_net_1",
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"voltage": 5
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},
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{
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"type": "schematic_component",
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"schematic_component_id": "schematic_component_0",
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"center": {
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"x": 0,
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"y": 0
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},
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"rotation": 0,
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"size": {
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"width": 1.5,
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"height": 0.6000000000000001
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},
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"pin_spacing": 0.2,
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"port_labels": {
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"pin1": "VOUT",
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"pin2": "GND"
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},
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"source_component_id": "source_component_0",
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"schematic_group_id": "schematic_group_0"
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},
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{
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"type": "schematic_text",
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"schematic_text_id": "schematic_text_0",
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"text": "",
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"schematic_component_id": "schematic_component_0",
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"anchor": "left",
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"rotation": 0,
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"position": {
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"x": -0.75,
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"y": -0.43000000000000005
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},
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"color": "#006464",
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"font_size": 0.18
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},
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{
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"type": "schematic_text",
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"schematic_text_id": "schematic_text_1",
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"text": "V1",
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"schematic_component_id": "schematic_component_0",
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280
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708
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711
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714
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715
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716
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717
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718
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719
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721
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722
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723
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724
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725
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726
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727
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728
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729
|
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730
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731
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732
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733
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734
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736
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737
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738
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739
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740
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741
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742
|
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743
|
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744
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745
|
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746
|
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747
|
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748
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749
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750
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751
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752
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753
|
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754
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755
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756
|
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757
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758
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759
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760
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761
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762
|
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763
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764
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765
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766
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767
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768
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769
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770
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771
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772
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773
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{
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774
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775
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776
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777
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778
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779
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780
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781
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782
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783
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784
|
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785
|
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786
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787
|
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788
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789
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790
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791
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792
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793
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794
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795
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796
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797
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798
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799
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800
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801
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802
|
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803
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804
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805
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806
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807
|
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808
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809
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810
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811
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812
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813
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814
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815
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816
|
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817
|
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818
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819
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820
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821
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822
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823
|
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824
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825
|
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826
|
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827
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828
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829
|
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{
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830
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831
|
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832
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833
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834
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835
|
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836
|
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837
|
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838
|
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|
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839
|
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840
|
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841
|
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842
|
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{
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843
|
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|
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844
|
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|
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845
|
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846
|
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847
|
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848
|
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849
|
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850
|
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851
|
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852
|
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853
|
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854
|
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855
|
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856
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857
|
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{
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858
|
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859
|
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860
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861
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862
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863
|
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864
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865
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866
|
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867
|
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868
|
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869
|
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},
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870
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{
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871
|
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872
|
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873
|
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874
|
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875
|
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876
|
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877
|
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878
|
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879
|
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880
|
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881
|
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"text": "V1",
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882
|
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883
|
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884
|
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885
|
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},
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886
|
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{
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887
|
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888
|
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889
|
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890
|
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891
|
+
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892
|
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893
|
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894
|
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895
|
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896
|
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897
|
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898
|
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899
|
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|
900
|
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},
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|
901
|
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{
|
|
902
|
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903
|
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|
|
904
|
+
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|
905
|
+
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|
906
|
+
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907
|
+
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|
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908
|
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|
|
909
|
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910
|
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|
|
911
|
+
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|
|
912
|
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|
|
913
|
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},
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|
914
|
+
{
|
|
915
|
+
"type": "pcb_smtpad",
|
|
916
|
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|
|
917
|
+
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|
|
918
|
+
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|
|
919
|
+
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|
920
|
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921
|
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|
922
|
+
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|
923
|
+
"port_hints": ["2", "right"],
|
|
924
|
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|
925
|
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|
926
|
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|
927
|
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|
928
|
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},
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|
929
|
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{
|
|
930
|
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"type": "pcb_solder_paste",
|
|
931
|
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|
|
932
|
+
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|
933
|
+
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934
|
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|
935
|
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|
|
936
|
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|
|
937
|
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"y": 4,
|
|
938
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941
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942
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945
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967
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968
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969
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971
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979
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995
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997
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999
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1000
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1001
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1002
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1003
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1004
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1005
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1006
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1008
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1009
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1010
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1015
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1017
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1019
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1020
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1021
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1022
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1023
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1024
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1025
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1026
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1027
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1028
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1029
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1030
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1031
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1032
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1033
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1034
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1035
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1036
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1037
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1038
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1039
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1040
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1041
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1042
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1043
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1044
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1065
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1066
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1067
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1068
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1069
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1070
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1077
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1078
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1079
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1081
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1084
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1085
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1086
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1087
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1093
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1094
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1095
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1096
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1097
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1098
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1099
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1100
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1101
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1102
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1103
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1104
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1105
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1106
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1107
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1108
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1109
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1110
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1111
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1112
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1113
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1114
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1115
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1116
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1117
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1118
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1119
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1120
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1121
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1122
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1123
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1124
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1125
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1126
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1127
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1128
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1129
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1130
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1131
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1132
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1133
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1134
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1135
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1136
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1137
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1138
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1139
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1140
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1141
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1142
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1149
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1154
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1159
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1160
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1161
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1162
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1163
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1164
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1165
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1166
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1167
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1168
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1169
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1170
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1171
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1173
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1174
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1175
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1176
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1177
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1178
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1179
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1180
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1181
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1182
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1183
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1184
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1186
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1187
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1188
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1190
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1191
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1192
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1193
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1194
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1195
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1196
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1197
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1198
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1199
|
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1200
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1201
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1202
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1203
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1204
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1205
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1206
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1207
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1208
|
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1209
|
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1210
|
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{
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1211
|
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1212
|
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1213
|
+
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1214
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1215
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1216
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1217
|
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1218
|
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1219
|
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},
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1220
|
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{
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1221
|
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1222
|
+
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1223
|
+
"pcb_component_id": "pcb_component_1",
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1224
|
+
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1225
|
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1226
|
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1227
|
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1228
|
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1229
|
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},
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1230
|
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{
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1231
|
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1232
|
+
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1233
|
+
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|
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1234
|
+
"layers": ["top"],
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1235
|
+
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1236
|
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1237
|
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1238
|
+
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1239
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},
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1240
|
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{
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1241
|
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1242
|
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1243
|
+
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|
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1244
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+
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1245
|
+
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|
|
1246
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|
|
1578
|
+
"route_type": "wire",
|
|
1579
|
+
"x": 3.040627128361783,
|
|
1580
|
+
"y": 5.469372871638217,
|
|
1581
|
+
"width": 0.15,
|
|
1582
|
+
"layer": "top"
|
|
1583
|
+
},
|
|
1584
|
+
{
|
|
1585
|
+
"route_type": "wire",
|
|
1586
|
+
"x": 4.51,
|
|
1587
|
+
"y": 4,
|
|
1588
|
+
"width": 0.15,
|
|
1589
|
+
"layer": "top",
|
|
1590
|
+
"end_pcb_port_id": "pcb_port_4"
|
|
1591
|
+
}
|
|
1592
|
+
],
|
|
1593
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
1594
|
+
"source_trace_id": "source_trace_2"
|
|
1595
|
+
},
|
|
1596
|
+
{
|
|
1597
|
+
"type": "pcb_via",
|
|
1598
|
+
"pcb_via_id": "pcb_via_0",
|
|
1599
|
+
"pcb_trace_id": "source_trace_5_0",
|
|
1600
|
+
"x": 2.5,
|
|
1601
|
+
"y": 2.5,
|
|
1602
|
+
"hole_diameter": 0.3,
|
|
1603
|
+
"outer_diameter": 0.6,
|
|
1604
|
+
"layers": ["top", "bottom"],
|
|
1605
|
+
"from_layer": "top",
|
|
1606
|
+
"to_layer": "bottom"
|
|
1607
|
+
},
|
|
1608
|
+
{
|
|
1609
|
+
"type": "pcb_via",
|
|
1610
|
+
"pcb_via_id": "pcb_via_1",
|
|
1611
|
+
"pcb_trace_id": "source_trace_5_0",
|
|
1612
|
+
"x": -1,
|
|
1613
|
+
"y": 3,
|
|
1614
|
+
"hole_diameter": 0.3,
|
|
1615
|
+
"outer_diameter": 0.6,
|
|
1616
|
+
"layers": ["bottom", "top"],
|
|
1617
|
+
"from_layer": "bottom",
|
|
1618
|
+
"to_layer": "top"
|
|
1619
|
+
}
|
|
1620
|
+
]
|