ac6502 1.3.0 → 1.4.1

package/dist/components/IO/VIA.js

@@ -0,0 +1,597 @@
+"use strict";
+Object.defineProperty(exports, "__esModule", { value: true });
+exports.VIA = void 0;
+/**
+ * VIA - Emulates the 65C22 VIA (Versatile Interface Adapter)
+ *
+ * The 65C22 VIA provides:
+ * - Two 8-bit bidirectional I/O ports (Port A and Port B)
+ * - Two 16-bit timers with interrupt generation
+ * - Shift register for serial I/O
+ * - Handshaking lines for data transfer
+ */
+class VIA {
+    constructor() {
+        // VIA Registers
+        this.regORB = 0x00;
+        this.regORA = 0x00;
+        this.regDDRB = 0x00;
+        this.regDDRA = 0x00;
+        this.regT1C = 0xFFFF;
+        this.regT1L = 0xFFFF;
+        this.regT2C = 0xFFFF;
+        this.regT2L = 0xFF;
+        this.regSR = 0x00;
+        this.regACR = 0x00;
+        this.regPCR = 0x00;
+        this.regIFR = 0x00;
+        this.regIER = 0x00;
+        // Control lines
+        this.CA1 = false;
+        this.CA2 = false;
+        this.CB1 = false;
+        this.CB2 = false;
+        // Timer states
+        this.T1_running = false;
+        this.T2_running = false;
+        this.T1_IRQ_enabled = false;
+        this.T2_IRQ_enabled = false;
+        // Timing
+        this.tickCounter = 0;
+        this.ticksPerMicrosecond = 1;
+        // Attachments
+        this.portA_attachments = [];
+        this.portB_attachments = [];
+        this.portA_attachmentCount = 0;
+        this.portB_attachmentCount = 0;
+        this.raiseIRQ = () => { };
+        this.raiseNMI = () => { };
+        this.reset(true);
+    }
+    reset(coldStart) {
+        // Reset all VIA registers
+        this.regORB = 0x00;
+        this.regORA = 0x00;
+        this.regDDRB = 0x00;
+        this.regDDRA = 0x00;
+        this.regT1C = 0xFFFF;
+        this.regT1L = 0xFFFF;
+        this.regT2C = 0xFFFF;
+        this.regT2L = 0xFF;
+        this.regSR = 0x00;
+        this.regACR = 0x00;
+        this.regPCR = 0x00;
+        this.regIFR = 0x00;
+        this.regIER = 0x00;
+        // Reset control lines
+        this.CA1 = false;
+        this.CA2 = false;
+        this.CB1 = false;
+        this.CB2 = false;
+        // Reset timer states
+        this.T1_running = false;
+        this.T2_running = false;
+        this.T1_IRQ_enabled = false;
+        this.T2_IRQ_enabled = false;
+        // Initialize attachment arrays
+        this.portA_attachmentCount = 0;
+        this.portB_attachmentCount = 0;
+        for (let i = 0; i < VIA.MAX_ATTACHMENTS_PER_PORT; i++) {
+            this.portA_attachments[i] = null;
+            this.portB_attachments[i] = null;
+        }
+        // Reset all attachments
+        for (let i = 0; i < this.portA_attachmentCount; i++) {
+            if (this.portA_attachments[i] !== null) {
+                this.portA_attachments[i].reset();
+            }
+        }
+        for (let i = 0; i < this.portB_attachmentCount; i++) {
+            if (this.portB_attachments[i] !== null) {
+                this.portB_attachments[i].reset();
+            }
+        }
+        // Reset timing
+        this.tickCounter = 0;
+        this.ticksPerMicrosecond = 1;
+    }
+    read(address) {
+        const reg = address & 0x0F;
+        let value = 0x00;
+        switch (reg) {
+            case VIA.VIA_ORB:
+                // Reading ORB clears CB1 and CB2 interrupt flags
+                this.clearIRQFlag(VIA.IRQ_CB1 | VIA.IRQ_CB2);
+                value = this.readPortB();
+                // Notify attachments that interrupts were cleared
+                for (let i = 0; i < this.portB_attachmentCount; i++) {
+                    if (this.portB_attachments[i] !== null) {
+                        this.portB_attachments[i].clearInterrupts(false, false, true, true);
+                    }
+                }
+                break;
+            case VIA.VIA_ORA:
+                // Reading ORA clears CA1 and CA2 interrupt flags
+                this.clearIRQFlag(VIA.IRQ_CA1 | VIA.IRQ_CA2);
+                value = this.readPortA();
+                // Notify attachments that interrupts were cleared
+                for (let i = 0; i < this.portA_attachmentCount; i++) {
+                    if (this.portA_attachments[i] !== null) {
+                        this.portA_attachments[i].clearInterrupts(true, true, false, false);
+                    }
+                }
+                break;
+            case VIA.VIA_DDRB:
+                value = this.regDDRB;
+                break;
+            case VIA.VIA_DDRA:
+                value = this.regDDRA;
+                break;
+            case VIA.VIA_T1CL:
+                // Reading T1CL clears T1 interrupt flag
+                this.clearIRQFlag(VIA.IRQ_T1);
+                value = this.regT1C & 0xFF;
+                break;
+            case VIA.VIA_T1CH:
+                value = (this.regT1C >> 8) & 0xFF;
+                break;
+            case VIA.VIA_T1LL:
+                value = this.regT1L & 0xFF;
+                break;
+            case VIA.VIA_T1LH:
+                value = (this.regT1L >> 8) & 0xFF;
+                break;
+            case VIA.VIA_T2CL:
+                // Reading T2CL clears T2 interrupt flag
+                this.clearIRQFlag(VIA.IRQ_T2);
+                value = this.regT2C & 0xFF;
+                break;
+            case VIA.VIA_T2CH:
+                value = (this.regT2C >> 8) & 0xFF;
+                break;
+            case VIA.VIA_SR:
+                // Reading SR clears SR interrupt flag
+                this.clearIRQFlag(VIA.IRQ_SR);
+                value = this.regSR;
+                break;
+            case VIA.VIA_ACR:
+                value = this.regACR;
+                break;
+            case VIA.VIA_PCR:
+                value = this.regPCR;
+                break;
+            case VIA.VIA_IFR:
+                value = this.regIFR;
+                // Bit 7 is set if any enabled interrupt is active
+                if (this.regIFR & this.regIER & 0x7F) {
+                    value |= VIA.IRQ_IRQ;
+                }
+                break;
+            case VIA.VIA_IER:
+                value = this.regIER | 0x80; // Bit 7 always reads as 1
+                break;
+            case VIA.VIA_ORA_NH:
+                // Reading ORA without handshake (no interrupt flag clearing)
+                value = this.readPortA();
+                break;
+        }
+        return value & 0xFF;
+    }
+    write(address, data) {
+        const reg = address & 0x0F;
+        const value = data & 0xFF;
+        switch (reg) {
+            case VIA.VIA_ORB:
+                // Writing ORB clears CB1 and CB2 interrupt flags
+                this.clearIRQFlag(VIA.IRQ_CB1 | VIA.IRQ_CB2);
+                this.regORB = value;
+                this.writePortB(value);
+                break;
+            case VIA.VIA_ORA:
+                // Writing ORA clears CA1 and CA2 interrupt flags
+                this.clearIRQFlag(VIA.IRQ_CA1 | VIA.IRQ_CA2);
+                this.regORA = value;
+                this.writePortA(value);
+                break;
+            case VIA.VIA_DDRB:
+                this.regDDRB = value;
+                break;
+            case VIA.VIA_DDRA:
+                this.regDDRA = value;
+                break;
+            case VIA.VIA_T1CL:
+            case VIA.VIA_T1LL:
+                // Write to T1 low latch
+                this.regT1L = (this.regT1L & 0xFF00) | value;
+                break;
+            case VIA.VIA_T1CH:
+                // Write to T1 high counter - loads latch into counter and starts timer
+                this.regT1L = (this.regT1L & 0x00FF) | (value << 8);
+                this.regT1C = this.regT1L;
+                this.clearIRQFlag(VIA.IRQ_T1);
+                this.T1_running = true;
+                break;
+            case VIA.VIA_T1LH:
+                // Write to T1 high latch
+                this.regT1L = (this.regT1L & 0x00FF) | (value << 8);
+                this.clearIRQFlag(VIA.IRQ_T1);
+                break;
+            case VIA.VIA_T2CL:
+                // Write to T2 low latch
+                this.regT2L = value;
+                break;
+            case VIA.VIA_T2CH:
+                // Write to T2 high counter - loads latch into counter and starts timer
+                this.regT2C = (value << 8) | this.regT2L;
+                this.clearIRQFlag(VIA.IRQ_T2);
+                this.T2_running = true;
+                break;
+            case VIA.VIA_SR:
+                this.regSR = value;
+                this.clearIRQFlag(VIA.IRQ_SR);
+                break;
+            case VIA.VIA_ACR:
+                this.regACR = value;
+                // ACR controls timer modes, shift register, and latching
+                break;
+            case VIA.VIA_PCR:
+                this.regPCR = value;
+                // PCR controls CA1, CA2, CB1, CB2 behavior
+                this.updateCA2();
+                this.updateCB2();
+                break;
+            case VIA.VIA_IFR:
+                // Writing to IFR clears the corresponding interrupt flags
+                this.regIFR &= ~(value & 0x7F);
+                this.updateIRQ();
+                break;
+            case VIA.VIA_IER:
+                // Bit 7 determines set (1) or clear (0)
+                if (value & 0x80) {
+                    this.regIER |= (value & 0x7F);
+                }
+                else {
+                    this.regIER &= ~(value & 0x7F);
+                }
+                this.updateIRQ();
+                break;
+            case VIA.VIA_ORA_NH:
+                // Writing ORA without handshake (no interrupt flag clearing)
+                this.regORA = value;
+                this.writePortA(value);
+                break;
+        }
+    }
+    tick(frequency) {
+        this.tickCounter++;
+        // Update Timer 1
+        if (this.T1_running && this.regT1C > 0) {
+            this.regT1C--;
+            if (this.regT1C === 0) {
+                this.setIRQFlag(VIA.IRQ_T1);
+                // Check if timer is in free-run mode (ACR bit 6)
+                if (this.regACR & 0x40) {
+                    this.regT1C = this.regT1L; // Reload from latch
+                }
+                else {
+                    this.T1_running = false;
+                }
+                // Toggle PB7 if enabled (ACR bit 7)
+                if (this.regACR & 0x80) {
+                    this.regORB ^= 0x80;
+                }
+            }
+        }
+        // Update Timer 2
+        if (this.T2_running && this.regT2C > 0) {
+            this.regT2C--;
+            if (this.regT2C === 0) {
+                this.setIRQFlag(VIA.IRQ_T2);
+                this.T2_running = false;
+            }
+        }
+        // Tick all attachments
+        for (let i = 0; i < this.portA_attachmentCount; i++) {
+            if (this.portA_attachments[i] !== null) {
+                this.portA_attachments[i].tick(frequency);
+            }
+        }
+        for (let i = 0; i < this.portB_attachmentCount; i++) {
+            if (this.portB_attachments[i] !== null) {
+                this.portB_attachments[i].tick(frequency);
+            }
+        }
+        // Check for attachment interrupts
+        for (let i = 0; i < this.portA_attachmentCount; i++) {
+            if (this.portA_attachments[i] !== null) {
+                if (this.portA_attachments[i].hasCA1Interrupt()) {
+                    this.setIRQFlag(VIA.IRQ_CA1);
+                }
+                if (this.portA_attachments[i].hasCA2Interrupt()) {
+                    this.setIRQFlag(VIA.IRQ_CA2);
+                }
+            }
+        }
+        for (let i = 0; i < this.portB_attachmentCount; i++) {
+            if (this.portB_attachments[i] !== null) {
+                if (this.portB_attachments[i].hasCB1Interrupt()) {
+                    this.setIRQFlag(VIA.IRQ_CB1);
+                }
+                if (this.portB_attachments[i].hasCB2Interrupt()) {
+                    this.setIRQFlag(VIA.IRQ_CB2);
+                }
+            }
+        }
+        // Raise IRQ if any enabled interrupt is active
+        if (this.regIFR & this.regIER & 0x7F) {
+            this.raiseIRQ();
+        }
+    }
+    updateIRQ() {
+        // Update bit 7 of IFR based on enabled interrupts
+        if (this.regIFR & this.regIER & 0x7F) {
+            this.regIFR |= VIA.IRQ_IRQ;
+        }
+        else {
+            this.regIFR &= ~VIA.IRQ_IRQ;
+        }
+    }
+    setIRQFlag(flag) {
+        this.regIFR |= flag;
+        this.updateIRQ();
+    }
+    clearIRQFlag(flag) {
+        this.regIFR &= ~flag;
+        this.updateIRQ();
+    }
+    readPortA() {
+        let value = 0xFF;
+        // Determine input sources from attachments (priority-based multiplexing)
+        let externalInput = 0xFF;
+        // Query all Port A attachments in priority order
+        for (let i = 0; i < this.portA_attachmentCount; i++) {
+            if (this.portA_attachments[i] !== null && this.portA_attachments[i].isEnabled()) {
+                const attachmentData = this.portA_attachments[i].readPortA(this.regDDRA, this.regORA);
+                // First enabled attachment with data (not 0xFF) wins, or AND all values together
+                externalInput &= attachmentData;
+            }
+        }
+        // Apply DDR settings: output bits come from ORA, input bits from external
+        for (let bit = 0; bit < 8; bit++) {
+            if (this.regDDRA & (1 << bit)) {
+                // Output mode - read from register
+                if (this.regORA & (1 << bit)) {
+                    value |= (1 << bit);
+                }
+                else {
+                    value &= ~(1 << bit);
+                }
+            }
+            else {
+                // Input mode - read from external source
+                if (externalInput & (1 << bit)) {
+                    value |= (1 << bit);
+                }
+                else {
+                    value &= ~(1 << bit);
+                }
+            }
+        }
+        return value & 0xFF;
+    }
+    readPortB() {
+        let value = 0xFF;
+        // Determine input sources from attachments (priority-based multiplexing)
+        let externalInput = 0xFF;
+        // Query all Port B attachments in priority order
+        for (let i = 0; i < this.portB_attachmentCount; i++) {
+            if (this.portB_attachments[i] !== null && this.portB_attachments[i].isEnabled()) {
+                const attachmentData = this.portB_attachments[i].readPortB(this.regDDRB, this.regORB);
+                // First enabled attachment with data (not 0xFF) wins, or AND all values together
+                externalInput &= attachmentData;
+            }
+        }
+        // Apply DDR settings: output bits come from ORB, input bits from external
+        for (let bit = 0; bit < 8; bit++) {
+            if (this.regDDRB & (1 << bit)) {
+                // Output mode - read from register
+                if (this.regORB & (1 << bit)) {
+                    value |= (1 << bit);
+                }
+                else {
+                    value &= ~(1 << bit);
+                }
+            }
+            else {
+                // Input mode - read from external source
+                if (externalInput & (1 << bit)) {
+                    value |= (1 << bit);
+                }
+                else {
+                    value &= ~(1 << bit);
+                }
+            }
+        }
+        return value & 0xFF;
+    }
+    writePortA(value) {
+        // Notify all Port A attachments of the write
+        for (let i = 0; i < this.portA_attachmentCount; i++) {
+            if (this.portA_attachments[i] !== null) {
+                this.portA_attachments[i].writePortA(value, this.regDDRA);
+            }
+        }
+    }
+    writePortB(value) {
+        // Notify all Port B attachments of the write
+        for (let i = 0; i < this.portB_attachmentCount; i++) {
+            if (this.portB_attachments[i] !== null) {
+                this.portB_attachments[i].writePortB(value, this.regDDRB);
+            }
+        }
+    }
+    updateCA2() {
+        // CA2 control based on PCR bits 1-3
+        const ca2_control = (this.regPCR >> 1) & 0x07;
+        switch (ca2_control) {
+            case 0x00: // Input mode - negative edge
+            case 0x01: // Independent interrupt input - negative edge
+            case 0x02: // Input mode - positive edge
+            case 0x03: // Independent interrupt input - positive edge
+                // Input modes
+                break;
+            case 0x04: // Handshake output
+            case 0x05: // Pulse output
+                // Output modes
+                break;
+            case 0x06: // Manual output LOW
+                this.CA2 = false;
+                break;
+            case 0x07: // Manual output HIGH
+                this.CA2 = true;
+                break;
+        }
+        // Notify all attachments of control line changes
+        this.notifyAttachmentsControlLines();
+    }
+    updateCB2() {
+        // CB2 control based on PCR bits 5-7
+        const cb2_control = (this.regPCR >> 5) & 0x07;
+        switch (cb2_control) {
+            case 0x00: // Input mode - negative edge
+            case 0x01: // Independent interrupt input - negative edge
+            case 0x02: // Input mode - positive edge
+            case 0x03: // Independent interrupt input - positive edge
+                // Input modes
+                break;
+            case 0x04: // Handshake output
+            case 0x05: // Pulse output
+                // Output modes
+                break;
+            case 0x06: // Manual output LOW
+                this.CB2 = false;
+                break;
+            case 0x07: // Manual output HIGH
+                this.CB2 = true;
+                break;
+        }
+        // Notify all attachments of control line changes
+        this.notifyAttachmentsControlLines();
+    }
+    notifyAttachmentsControlLines() {
+        // Notify all attachments of control line state changes
+        for (let i = 0; i < this.portA_attachmentCount; i++) {
+            if (this.portA_attachments[i] !== null) {
+                this.portA_attachments[i].updateControlLines(this.CA1, this.CA2, this.CB1, this.CB2);
+            }
+        }
+        for (let i = 0; i < this.portB_attachmentCount; i++) {
+            if (this.portB_attachments[i] !== null) {
+                this.portB_attachments[i].updateControlLines(this.CA1, this.CA2, this.CB1, this.CB2);
+            }
+        }
+    }
+    sortAttachmentsByPriority() {
+        // Simple bubble sort for Port A attachments by priority (lower = higher priority)
+        for (let i = 0; i < this.portA_attachmentCount - 1; i++) {
+            for (let j = 0; j < this.portA_attachmentCount - i - 1; j++) {
+                if (this.portA_attachments[j] !== null && this.portA_attachments[j + 1] !== null) {
+                    if (this.portA_attachments[j].getPriority() > this.portA_attachments[j + 1].getPriority()) {
+                        // Swap
+                        const temp = this.portA_attachments[j];
+                        this.portA_attachments[j] = this.portA_attachments[j + 1];
+                        this.portA_attachments[j + 1] = temp;
+                    }
+                }
+            }
+        }
+        // Simple bubble sort for Port B attachments by priority
+        for (let i = 0; i < this.portB_attachmentCount - 1; i++) {
+            for (let j = 0; j < this.portB_attachmentCount - i - 1; j++) {
+                if (this.portB_attachments[j] !== null && this.portB_attachments[j + 1] !== null) {
+                    if (this.portB_attachments[j].getPriority() > this.portB_attachments[j + 1].getPriority()) {
+                        // Swap
+                        const temp = this.portB_attachments[j];
+                        this.portB_attachments[j] = this.portB_attachments[j + 1];
+                        this.portB_attachments[j + 1] = temp;
+                    }
+                }
+            }
+        }
+    }
+    /**
+     * Attach a GPIO device to Port A
+     * @param attachment - The attachment to add
+     */
+    attachToPortA(attachment) {
+        if (attachment !== null && this.portA_attachmentCount < VIA.MAX_ATTACHMENTS_PER_PORT) {
+            this.portA_attachments[this.portA_attachmentCount++] = attachment;
+            this.sortAttachmentsByPriority();
+            // Notify the attachment of current control line states
+            attachment.updateControlLines(this.CA1, this.CA2, this.CB1, this.CB2);
+        }
+    }
+    /**
+     * Attach a GPIO device to Port B
+     * @param attachment - The attachment to add
+     */
+    attachToPortB(attachment) {
+        if (attachment !== null && this.portB_attachmentCount < VIA.MAX_ATTACHMENTS_PER_PORT) {
+            this.portB_attachments[this.portB_attachmentCount++] = attachment;
+            this.sortAttachmentsByPriority();
+            // Notify the attachment of current control line states
+            attachment.updateControlLines(this.CA1, this.CA2, this.CB1, this.CB2);
+        }
+    }
+    /**
+     * Get a Port A attachment by index
+     * @param index - The attachment index
+     * @returns The attachment or null if not found
+     */
+    getPortAAttachment(index) {
+        if (index < this.portA_attachmentCount) {
+            return this.portA_attachments[index];
+        }
+        return null;
+    }
+    /**
+     * Get a Port B attachment by index
+     * @param index - The attachment index
+     * @returns The attachment or null if not found
+     */
+    getPortBAttachment(index) {
+        if (index < this.portB_attachmentCount) {
+            return this.portB_attachments[index];
+        }
+        return null;
+    }
+}
+exports.VIA = VIA;
+// VIA Register addresses (offset from base address)
+VIA.VIA_ORB = 0x00; // Output Register B
+VIA.VIA_ORA = 0x01; // Output Register A
+VIA.VIA_DDRB = 0x02; // Data Direction Register B
+VIA.VIA_DDRA = 0x03; // Data Direction Register A
+VIA.VIA_T1CL = 0x04; // Timer 1 Counter Low
+VIA.VIA_T1CH = 0x05; // Timer 1 Counter High
+VIA.VIA_T1LL = 0x06; // Timer 1 Latch Low
+VIA.VIA_T1LH = 0x07; // Timer 1 Latch High
+VIA.VIA_T2CL = 0x08; // Timer 2 Counter Low
+VIA.VIA_T2CH = 0x09; // Timer 2 Counter High
+VIA.VIA_SR = 0x0A; // Shift Register
+VIA.VIA_ACR = 0x0B; // Auxiliary Control Register
+VIA.VIA_PCR = 0x0C; // Peripheral Control Register
+VIA.VIA_IFR = 0x0D; // Interrupt Flag Register
+VIA.VIA_IER = 0x0E; // Interrupt Enable Register
+VIA.VIA_ORA_NH = 0x0F; // Output Register A (No Handshake)
+// Interrupt flags
+VIA.IRQ_CA2 = 0x01;
+VIA.IRQ_CA1 = 0x02;
+VIA.IRQ_SR = 0x04;
+VIA.IRQ_CB2 = 0x08;
+VIA.IRQ_CB1 = 0x10;
+VIA.IRQ_T2 = 0x20;
+VIA.IRQ_T1 = 0x40;
+VIA.IRQ_IRQ = 0x80; // Master IRQ flag
+VIA.MAX_ATTACHMENTS_PER_PORT = 8;
+//# sourceMappingURL=VIA.js.map

package/dist/components/IO/VIA.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"VIA.js","sourceRoot":"","sources":["../../../src/components/IO/VIA.ts"],"names":[],"mappings":";;;AAGA;;;;;;;;GAQG;AACH,MAAa,GAAG;IAuEd;QAxCA,gBAAgB;QACR,WAAM,GAAW,IAAI,CAAA;QACrB,WAAM,GAAW,IAAI,CAAA;QACrB,YAAO,GAAW,IAAI,CAAA;QACtB,YAAO,GAAW,IAAI,CAAA;QACtB,WAAM,GAAW,MAAM,CAAA;QACvB,WAAM,GAAW,MAAM,CAAA;QACvB,WAAM,GAAW,MAAM,CAAA;QACvB,WAAM,GAAW,IAAI,CAAA;QACrB,UAAK,GAAW,IAAI,CAAA;QACpB,WAAM,GAAW,IAAI,CAAA;QACrB,WAAM,GAAW,IAAI,CAAA;QACrB,WAAM,GAAW,IAAI,CAAA;QACrB,WAAM,GAAW,IAAI,CAAA;QAE7B,gBAAgB;QACR,QAAG,GAAY,KAAK,CAAA;QACpB,QAAG,GAAY,KAAK,CAAA;QACpB,QAAG,GAAY,KAAK,CAAA;QACpB,QAAG,GAAY,KAAK,CAAA;QAE5B,eAAe;QACP,eAAU,GAAY,KAAK,CAAA;QAC3B,eAAU,GAAY,KAAK,CAAA;QAC3B,mBAAc,GAAY,KAAK,CAAA;QAC/B,mBAAc,GAAY,KAAK,CAAA;QAEvC,SAAS;QACD,gBAAW,GAAW,CAAC,CAAA;QACvB,wBAAmB,GAAW,CAAC,CAAA;QAEvC,cAAc;QACN,sBAAiB,GAA0B,EAAE,CAAA;QAC7C,sBAAiB,GAA0B,EAAE,CAAA;QAC7C,0BAAqB,GAAW,CAAC,CAAA;QACjC,0BAAqB,GAAW,CAAC,CAAA;QAEzC,aAAQ,GAAG,GAAG,EAAE,GAAE,CAAC,CAAA;QACnB,aAAQ,GAAG,GAAG,EAAE,GAAE,CAAC,CAAA;QAGjB,IAAI,CAAC,KAAK,CAAC,IAAI,CAAC,CAAA;IAClB,CAAC;IAED,KAAK,CAAC,SAAkB;QACtB,0BAA0B;QAC1B,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;QAClB,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;QAClB,IAAI,CAAC,OAAO,GAAG,IAAI,CAAA;QACnB,IAAI,CAAC,OAAO,GAAG,IAAI,CAAA;QACnB,IAAI,CAAC,MAAM,GAAG,MAAM,CAAA;QACpB,IAAI,CAAC,MAAM,GAAG,MAAM,CAAA;QACpB,IAAI,CAAC,MAAM,GAAG,MAAM,CAAA;QACpB,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;QAClB,IAAI,CAAC,KAAK,GAAG,IAAI,CAAA;QACjB,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;QAClB,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;QAClB,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;QAClB,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;QAElB,sBAAsB;QACtB,IAAI,CAAC,GAAG,GAAG,KAAK,CAAA;QAChB,IAAI,CAAC,GAAG,GAAG,KAAK,CAAA;QAChB,IAAI,CAAC,GAAG,GAAG,KAAK,CAAA;QAChB,IAAI,CAAC,GAAG,GAAG,KAAK,CAAA;QAEhB,qBAAqB;QACrB,IAAI,CAAC,UAAU,GAAG,KAAK,CAAA;QACvB,IAAI,CAAC,UAAU,GAAG,KAAK,CAAA;QACvB,IAAI,CAAC,cAAc,GAAG,KAAK,CAAA;QAC3B,IAAI,CAAC,cAAc,GAAG,KAAK,CAAA;QAE3B,+BAA+B;QAC/B,IAAI,CAAC,qBAAqB,GAAG,CAAC,CAAA;QAC9B,IAAI,CAAC,qBAAqB,GAAG,CAAC,CAAA;QAC9B,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,GAAG,CAAC,wBAAwB,EAAE,CAAC,EAAE,EAAE,CAAC;YACtD,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,GAAG,IAAI,CAAA;YAChC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,GAAG,IAAI,CAAA;QAClC,CAAC;QAED,wBAAwB;QACxB,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,KAAK,EAAE,CAAA;YACpC,CAAC;QACH,CAAC;QACD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,KAAK,EAAE,CAAA;YACpC,CAAC;QACH,CAAC;QAED,eAAe;QACf,IAAI,CAAC,WAAW,GAAG,CAAC,CAAA;QACpB,IAAI,CAAC,mBAAmB,GAAG,CAAC,CAAA;IAC9B,CAAC;IAED,IAAI,CAAC,OAAe;QAClB,MAAM,GAAG,GAAG,OAAO,GAAG,IAAI,CAAA;QAC1B,IAAI,KAAK,GAAG,IAAI,CAAA;QAEhB,QAAQ,GAAG,EAAE,CAAC;YACZ,KAAK,GAAG,CAAC,OAAO;gBACd,iDAAiD;gBACjD,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,OAAO,GAAG,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC5C,KAAK,GAAG,IAAI,CAAC,SAAS,EAAE,CAAA;gBACxB,kDAAkD;gBAClD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;oBACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;wBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,eAAe,CAAC,KAAK,EAAE,KAAK,EAAE,IAAI,EAAE,IAAI,CAAC,CAAA;oBACtE,CAAC;gBACH,CAAC;gBACD,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,iDAAiD;gBACjD,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,OAAO,GAAG,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC5C,KAAK,GAAG,IAAI,CAAC,SAAS,EAAE,CAAA;gBACxB,kDAAkD;gBAClD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;oBACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;wBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,eAAe,CAAC,IAAI,EAAE,IAAI,EAAE,KAAK,EAAE,KAAK,CAAC,CAAA;oBACtE,CAAC;gBACH,CAAC;gBACD,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,KAAK,GAAG,IAAI,CAAC,OAAO,CAAA;gBACpB,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,KAAK,GAAG,IAAI,CAAC,OAAO,CAAA;gBACpB,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,wCAAwC;gBACxC,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC7B,KAAK,GAAG,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;gBAC1B,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,KAAK,GAAG,CAAC,IAAI,CAAC,MAAM,IAAI,CAAC,CAAC,GAAG,IAAI,CAAA;gBACjC,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,KAAK,GAAG,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;gBAC1B,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,KAAK,GAAG,CAAC,IAAI,CAAC,MAAM,IAAI,CAAC,CAAC,GAAG,IAAI,CAAA;gBACjC,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,wCAAwC;gBACxC,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC7B,KAAK,GAAG,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA;gBAC1B,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,KAAK,GAAG,CAAC,IAAI,CAAC,MAAM,IAAI,CAAC,CAAC,GAAG,IAAI,CAAA;gBACjC,MAAK;YAEP,KAAK,GAAG,CAAC,MAAM;gBACb,sCAAsC;gBACtC,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC7B,KAAK,GAAG,IAAI,CAAC,KAAK,CAAA;gBAClB,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,KAAK,GAAG,IAAI,CAAC,MAAM,CAAA;gBACnB,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,KAAK,GAAG,IAAI,CAAC,MAAM,CAAA;gBACnB,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,KAAK,GAAG,IAAI,CAAC,MAAM,CAAA;gBACnB,kDAAkD;gBAClD,IAAI,IAAI,CAAC,MAAM,GAAG,IAAI,CAAC,MAAM,GAAG,IAAI,EAAE,CAAC;oBACrC,KAAK,IAAI,GAAG,CAAC,OAAO,CAAA;gBACtB,CAAC;gBACD,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,KAAK,GAAG,IAAI,CAAC,MAAM,GAAG,IAAI,CAAA,CAAE,0BAA0B;gBACtD,MAAK;YAEP,KAAK,GAAG,CAAC,UAAU;gBACjB,6DAA6D;gBAC7D,KAAK,GAAG,IAAI,CAAC,SAAS,EAAE,CAAA;gBACxB,MAAK;QACT,CAAC;QAED,OAAO,KAAK,GAAG,IAAI,CAAA;IACrB,CAAC;IAED,KAAK,CAAC,OAAe,EAAE,IAAY;QACjC,MAAM,GAAG,GAAG,OAAO,GAAG,IAAI,CAAA;QAC1B,MAAM,KAAK,GAAG,IAAI,GAAG,IAAI,CAAA;QAEzB,QAAQ,GAAG,EAAE,CAAC;YACZ,KAAK,GAAG,CAAC,OAAO;gBACd,iDAAiD;gBACjD,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,OAAO,GAAG,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC5C,IAAI,CAAC,MAAM,GAAG,KAAK,CAAA;gBACnB,IAAI,CAAC,UAAU,CAAC,KAAK,CAAC,CAAA;gBACtB,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,iDAAiD;gBACjD,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,OAAO,GAAG,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC5C,IAAI,CAAC,MAAM,GAAG,KAAK,CAAA;gBACnB,IAAI,CAAC,UAAU,CAAC,KAAK,CAAC,CAAA;gBACtB,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;gBACpB,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;gBACpB,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ,CAAC;YAClB,KAAK,GAAG,CAAC,QAAQ;gBACf,wBAAwB;gBACxB,IAAI,CAAC,MAAM,GAAG,CAAC,IAAI,CAAC,MAAM,GAAG,MAAM,CAAC,GAAG,KAAK,CAAA;gBAC5C,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,uEAAuE;gBACvE,IAAI,CAAC,MAAM,GAAG,CAAC,IAAI,CAAC,MAAM,GAAG,MAAM,CAAC,GAAG,CAAC,KAAK,IAAI,CAAC,CAAC,CAAA;gBACnD,IAAI,CAAC,MAAM,GAAG,IAAI,CAAC,MAAM,CAAA;gBACzB,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC7B,IAAI,CAAC,UAAU,GAAG,IAAI,CAAA;gBACtB,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,yBAAyB;gBACzB,IAAI,CAAC,MAAM,GAAG,CAAC,IAAI,CAAC,MAAM,GAAG,MAAM,CAAC,GAAG,CAAC,KAAK,IAAI,CAAC,CAAC,CAAA;gBACnD,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC7B,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,wBAAwB;gBACxB,IAAI,CAAC,MAAM,GAAG,KAAK,CAAA;gBACnB,MAAK;YAEP,KAAK,GAAG,CAAC,QAAQ;gBACf,uEAAuE;gBACvE,IAAI,CAAC,MAAM,GAAG,CAAC,KAAK,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,MAAM,CAAA;gBACxC,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC7B,IAAI,CAAC,UAAU,GAAG,IAAI,CAAA;gBACtB,MAAK;YAEP,KAAK,GAAG,CAAC,MAAM;gBACb,IAAI,CAAC,KAAK,GAAG,KAAK,CAAA;gBAClB,IAAI,CAAC,YAAY,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC7B,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,IAAI,CAAC,MAAM,GAAG,KAAK,CAAA;gBACnB,yDAAyD;gBACzD,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,IAAI,CAAC,MAAM,GAAG,KAAK,CAAA;gBACnB,2CAA2C;gBAC3C,IAAI,CAAC,SAAS,EAAE,CAAA;gBAChB,IAAI,CAAC,SAAS,EAAE,CAAA;gBAChB,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,0DAA0D;gBAC1D,IAAI,CAAC,MAAM,IAAI,CAAC,CAAC,KAAK,GAAG,IAAI,CAAC,CAAA;gBAC9B,IAAI,CAAC,SAAS,EAAE,CAAA;gBAChB,MAAK;YAEP,KAAK,GAAG,CAAC,OAAO;gBACd,wCAAwC;gBACxC,IAAI,KAAK,GAAG,IAAI,EAAE,CAAC;oBACjB,IAAI,CAAC,MAAM,IAAI,CAAC,KAAK,GAAG,IAAI,CAAC,CAAA;gBAC/B,CAAC;qBAAM,CAAC;oBACN,IAAI,CAAC,MAAM,IAAI,CAAC,CAAC,KAAK,GAAG,IAAI,CAAC,CAAA;gBAChC,CAAC;gBACD,IAAI,CAAC,SAAS,EAAE,CAAA;gBAChB,MAAK;YAEP,KAAK,GAAG,CAAC,UAAU;gBACjB,6DAA6D;gBAC7D,IAAI,CAAC,MAAM,GAAG,KAAK,CAAA;gBACnB,IAAI,CAAC,UAAU,CAAC,KAAK,CAAC,CAAA;gBACtB,MAAK;QACT,CAAC;IACH,CAAC;IAED,IAAI,CAAC,SAAiB;QACpB,IAAI,CAAC,WAAW,EAAE,CAAA;QAElB,iBAAiB;QACjB,IAAI,IAAI,CAAC,UAAU,IAAI,IAAI,CAAC,MAAM,GAAG,CAAC,EAAE,CAAC;YACvC,IAAI,CAAC,MAAM,EAAE,CAAA;YACb,IAAI,IAAI,CAAC,MAAM,KAAK,CAAC,EAAE,CAAC;gBACtB,IAAI,CAAC,UAAU,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAE3B,iDAAiD;gBACjD,IAAI,IAAI,CAAC,MAAM,GAAG,IAAI,EAAE,CAAC;oBACvB,IAAI,CAAC,MAAM,GAAG,IAAI,CAAC,MAAM,CAAA,CAAE,oBAAoB;gBACjD,CAAC;qBAAM,CAAC;oBACN,IAAI,CAAC,UAAU,GAAG,KAAK,CAAA;gBACzB,CAAC;gBAED,oCAAoC;gBACpC,IAAI,IAAI,CAAC,MAAM,GAAG,IAAI,EAAE,CAAC;oBACvB,IAAI,CAAC,MAAM,IAAI,IAAI,CAAA;gBACrB,CAAC;YACH,CAAC;QACH,CAAC;QAED,iBAAiB;QACjB,IAAI,IAAI,CAAC,UAAU,IAAI,IAAI,CAAC,MAAM,GAAG,CAAC,EAAE,CAAC;YACvC,IAAI,CAAC,MAAM,EAAE,CAAA;YACb,IAAI,IAAI,CAAC,MAAM,KAAK,CAAC,EAAE,CAAC;gBACtB,IAAI,CAAC,UAAU,CAAC,GAAG,CAAC,MAAM,CAAC,CAAA;gBAC3B,IAAI,CAAC,UAAU,GAAG,KAAK,CAAA;YACzB,CAAC;QACH,CAAC;QAED,uBAAuB;QACvB,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,IAAI,CAAC,SAAS,CAAC,CAAA;YAC5C,CAAC;QACH,CAAC;QACD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,IAAI,CAAC,SAAS,CAAC,CAAA;YAC5C,CAAC;QACH,CAAC;QAED,kCAAkC;QAClC,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,eAAe,EAAE,EAAE,CAAC;oBACjD,IAAI,CAAC,UAAU,CAAC,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC9B,CAAC;gBACD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,eAAe,EAAE,EAAE,CAAC;oBACjD,IAAI,CAAC,UAAU,CAAC,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC9B,CAAC;YACH,CAAC;QACH,CAAC;QACD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,eAAe,EAAE,EAAE,CAAC;oBACjD,IAAI,CAAC,UAAU,CAAC,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC9B,CAAC;gBACD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,eAAe,EAAE,EAAE,CAAC;oBACjD,IAAI,CAAC,UAAU,CAAC,GAAG,CAAC,OAAO,CAAC,CAAA;gBAC9B,CAAC;YACH,CAAC;QACH,CAAC;QAED,+CAA+C;QAC/C,IAAI,IAAI,CAAC,MAAM,GAAG,IAAI,CAAC,MAAM,GAAG,IAAI,EAAE,CAAC;YACrC,IAAI,CAAC,QAAQ,EAAE,CAAA;QACjB,CAAC;IACH,CAAC;IAEO,SAAS;QACf,kDAAkD;QAClD,IAAI,IAAI,CAAC,MAAM,GAAG,IAAI,CAAC,MAAM,GAAG,IAAI,EAAE,CAAC;YACrC,IAAI,CAAC,MAAM,IAAI,GAAG,CAAC,OAAO,CAAA;QAC5B,CAAC;aAAM,CAAC;YACN,IAAI,CAAC,MAAM,IAAI,CAAC,GAAG,CAAC,OAAO,CAAA;QAC7B,CAAC;IACH,CAAC;IAEO,UAAU,CAAC,IAAY;QAC7B,IAAI,CAAC,MAAM,IAAI,IAAI,CAAA;QACnB,IAAI,CAAC,SAAS,EAAE,CAAA;IAClB,CAAC;IAEO,YAAY,CAAC,IAAY;QAC/B,IAAI,CAAC,MAAM,IAAI,CAAC,IAAI,CAAA;QACpB,IAAI,CAAC,SAAS,EAAE,CAAA;IAClB,CAAC;IAEO,SAAS;QACf,IAAI,KAAK,GAAG,IAAI,CAAA;QAEhB,yEAAyE;QACzE,IAAI,aAAa,GAAG,IAAI,CAAA;QAExB,iDAAiD;QACjD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,SAAS,EAAE,EAAE,CAAC;gBACjF,MAAM,cAAc,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,SAAS,CAAC,IAAI,CAAC,OAAO,EAAE,IAAI,CAAC,MAAM,CAAC,CAAA;gBACtF,iFAAiF;gBACjF,aAAa,IAAI,cAAc,CAAA;YACjC,CAAC;QACH,CAAC;QAED,0EAA0E;QAC1E,KAAK,IAAI,GAAG,GAAG,CAAC,EAAE,GAAG,GAAG,CAAC,EAAE,GAAG,EAAE,EAAE,CAAC;YACjC,IAAI,IAAI,CAAC,OAAO,GAAG,CAAC,CAAC,IAAI,GAAG,CAAC,EAAE,CAAC;gBAC9B,mCAAmC;gBACnC,IAAI,IAAI,CAAC,MAAM,GAAG,CAAC,CAAC,IAAI,GAAG,CAAC,EAAE,CAAC;oBAC7B,KAAK,IAAI,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACrB,CAAC;qBAAM,CAAC;oBACN,KAAK,IAAI,CAAC,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACtB,CAAC;YACH,CAAC;iBAAM,CAAC;gBACN,yCAAyC;gBACzC,IAAI,aAAa,GAAG,CAAC,CAAC,IAAI,GAAG,CAAC,EAAE,CAAC;oBAC/B,KAAK,IAAI,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACrB,CAAC;qBAAM,CAAC;oBACN,KAAK,IAAI,CAAC,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACtB,CAAC;YACH,CAAC;QACH,CAAC;QAED,OAAO,KAAK,GAAG,IAAI,CAAA;IACrB,CAAC;IAEO,SAAS;QACf,IAAI,KAAK,GAAG,IAAI,CAAA;QAEhB,yEAAyE;QACzE,IAAI,aAAa,GAAG,IAAI,CAAA;QAExB,iDAAiD;QACjD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,SAAS,EAAE,EAAE,CAAC;gBACjF,MAAM,cAAc,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,SAAS,CAAC,IAAI,CAAC,OAAO,EAAE,IAAI,CAAC,MAAM,CAAC,CAAA;gBACtF,iFAAiF;gBACjF,aAAa,IAAI,cAAc,CAAA;YACjC,CAAC;QACH,CAAC;QAED,0EAA0E;QAC1E,KAAK,IAAI,GAAG,GAAG,CAAC,EAAE,GAAG,GAAG,CAAC,EAAE,GAAG,EAAE,EAAE,CAAC;YACjC,IAAI,IAAI,CAAC,OAAO,GAAG,CAAC,CAAC,IAAI,GAAG,CAAC,EAAE,CAAC;gBAC9B,mCAAmC;gBACnC,IAAI,IAAI,CAAC,MAAM,GAAG,CAAC,CAAC,IAAI,GAAG,CAAC,EAAE,CAAC;oBAC7B,KAAK,IAAI,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACrB,CAAC;qBAAM,CAAC;oBACN,KAAK,IAAI,CAAC,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACtB,CAAC;YACH,CAAC;iBAAM,CAAC;gBACN,yCAAyC;gBACzC,IAAI,aAAa,GAAG,CAAC,CAAC,IAAI,GAAG,CAAC,EAAE,CAAC;oBAC/B,KAAK,IAAI,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACrB,CAAC;qBAAM,CAAC;oBACN,KAAK,IAAI,CAAC,CAAC,CAAC,IAAI,GAAG,CAAC,CAAA;gBACtB,CAAC;YACH,CAAC;QACH,CAAC;QAED,OAAO,KAAK,GAAG,IAAI,CAAA;IACrB,CAAC;IAEO,UAAU,CAAC,KAAa;QAC9B,6CAA6C;QAC7C,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,UAAU,CAAC,KAAK,EAAE,IAAI,CAAC,OAAO,CAAC,CAAA;YAC5D,CAAC;QACH,CAAC;IACH,CAAC;IAEO,UAAU,CAAC,KAAa;QAC9B,6CAA6C;QAC7C,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,UAAU,CAAC,KAAK,EAAE,IAAI,CAAC,OAAO,CAAC,CAAA;YAC5D,CAAC;QACH,CAAC;IACH,CAAC;IAEO,SAAS;QACf,oCAAoC;QACpC,MAAM,WAAW,GAAG,CAAC,IAAI,CAAC,MAAM,IAAI,CAAC,CAAC,GAAG,IAAI,CAAA;QAE7C,QAAQ,WAAW,EAAE,CAAC;YACpB,KAAK,IAAI,CAAC,CAAE,6BAA6B;YACzC,KAAK,IAAI,CAAC,CAAE,8CAA8C;YAC1D,KAAK,IAAI,CAAC,CAAE,6BAA6B;YACzC,KAAK,IAAI,EAAG,8CAA8C;gBACxD,cAAc;gBACd,MAAK;YAEP,KAAK,IAAI,CAAC,CAAE,mBAAmB;YAC/B,KAAK,IAAI,EAAG,eAAe;gBACzB,eAAe;gBACf,MAAK;YAEP,KAAK,IAAI,EAAG,oBAAoB;gBAC9B,IAAI,CAAC,GAAG,GAAG,KAAK,CAAA;gBAChB,MAAK;YAEP,KAAK,IAAI,EAAG,qBAAqB;gBAC/B,IAAI,CAAC,GAAG,GAAG,IAAI,CAAA;gBACf,MAAK;QACT,CAAC;QAED,iDAAiD;QACjD,IAAI,CAAC,6BAA6B,EAAE,CAAA;IACtC,CAAC;IAEO,SAAS;QACf,oCAAoC;QACpC,MAAM,WAAW,GAAG,CAAC,IAAI,CAAC,MAAM,IAAI,CAAC,CAAC,GAAG,IAAI,CAAA;QAE7C,QAAQ,WAAW,EAAE,CAAC;YACpB,KAAK,IAAI,CAAC,CAAE,6BAA6B;YACzC,KAAK,IAAI,CAAC,CAAE,8CAA8C;YAC1D,KAAK,IAAI,CAAC,CAAE,6BAA6B;YACzC,KAAK,IAAI,EAAG,8CAA8C;gBACxD,cAAc;gBACd,MAAK;YAEP,KAAK,IAAI,CAAC,CAAE,mBAAmB;YAC/B,KAAK,IAAI,EAAG,eAAe;gBACzB,eAAe;gBACf,MAAK;YAEP,KAAK,IAAI,EAAG,oBAAoB;gBAC9B,IAAI,CAAC,GAAG,GAAG,KAAK,CAAA;gBAChB,MAAK;YAEP,KAAK,IAAI,EAAG,qBAAqB;gBAC/B,IAAI,CAAC,GAAG,GAAG,IAAI,CAAA;gBACf,MAAK;QACT,CAAC;QAED,iDAAiD;QACjD,IAAI,CAAC,6BAA6B,EAAE,CAAA;IACtC,CAAC;IAEO,6BAA6B;QACnC,uDAAuD;QACvD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,kBAAkB,CAAC,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,CAAC,CAAA;YACvF,CAAC;QACH,CAAC;QACD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC,EAAE,EAAE,CAAC;YACpD,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;gBACvC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,kBAAkB,CAAC,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,CAAC,CAAA;YACvF,CAAC;QACH,CAAC;IACH,CAAC;IAEO,yBAAyB;QAC/B,kFAAkF;QAClF,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,GAAG,CAAC,EAAE,CAAC,EAAE,EAAE,CAAC;YACxD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,GAAG,CAAC,GAAG,CAAC,EAAE,CAAC,EAAE,EAAE,CAAC;gBAC5D,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;oBACjF,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,WAAW,EAAE,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAE,CAAC,WAAW,EAAE,EAAE,CAAC;wBAC5F,OAAO;wBACP,MAAM,IAAI,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,CAAA;wBACtC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAC,CAAA;wBACzD,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAA;oBACtC,CAAC;gBACH,CAAC;YACH,CAAC;QACH,CAAC;QAED,wDAAwD;QACxD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,GAAG,CAAC,EAAE,CAAC,EAAE,EAAE,CAAC;YACxD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,qBAAqB,GAAG,CAAC,GAAG,CAAC,EAAE,CAAC,EAAE,EAAE,CAAC;gBAC5D,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,KAAK,IAAI,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAC,KAAK,IAAI,EAAE,CAAC;oBACjF,IAAI,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAE,CAAC,WAAW,EAAE,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAE,CAAC,WAAW,EAAE,EAAE,CAAC;wBAC5F,OAAO;wBACP,MAAM,IAAI,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,CAAA;wBACtC,IAAI,CAAC,iBAAiB,CAAC,CAAC,CAAC,GAAG,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAC,CAAA;wBACzD,IAAI,CAAC,iBAAiB,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAA;oBACtC,CAAC;gBACH,CAAC;YACH,CAAC;QACH,CAAC;IACH,CAAC;IAED;;;OAGG;IACH,aAAa,CAAC,UAAsB;QAClC,IAAI,UAAU,KAAK,IAAI,IAAI,IAAI,CAAC,qBAAqB,GAAG,GAAG,CAAC,wBAAwB,EAAE,CAAC;YACrF,IAAI,CAAC,iBAAiB,CAAC,IAAI,CAAC,qBAAqB,EAAE,CAAC,GAAG,UAAU,CAAA;YACjE,IAAI,CAAC,yBAAyB,EAAE,CAAA;YAChC,uDAAuD;YACvD,UAAU,CAAC,kBAAkB,CAAC,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,CAAC,CAAA;QACvE,CAAC;IACH,CAAC;IAED;;;OAGG;IACH,aAAa,CAAC,UAAsB;QAClC,IAAI,UAAU,KAAK,IAAI,IAAI,IAAI,CAAC,qBAAqB,GAAG,GAAG,CAAC,wBAAwB,EAAE,CAAC;YACrF,IAAI,CAAC,iBAAiB,CAAC,IAAI,CAAC,qBAAqB,EAAE,CAAC,GAAG,UAAU,CAAA;YACjE,IAAI,CAAC,yBAAyB,EAAE,CAAA;YAChC,uDAAuD;YACvD,UAAU,CAAC,kBAAkB,CAAC,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,EAAE,IAAI,CAAC,GAAG,CAAC,CAAA;QACvE,CAAC;IACH,CAAC;IAED;;;;OAIG;IACH,kBAAkB,CAAC,KAAa;QAC9B,IAAI,KAAK,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC;YACvC,OAAO,IAAI,CAAC,iBAAiB,CAAC,KAAK,CAAC,CAAA;QACtC,CAAC;QACD,OAAO,IAAI,CAAA;IACb,CAAC;IAED;;;;OAIG;IACH,kBAAkB,CAAC,KAAa;QAC9B,IAAI,KAAK,GAAG,IAAI,CAAC,qBAAqB,EAAE,CAAC;YACvC,OAAO,IAAI,CAAC,iBAAiB,CAAC,KAAK,CAAC,CAAA;QACtC,CAAC;QACD,OAAO,IAAI,CAAA;IACb,CAAC;;AAvpBH,kBAwpBC;AAvpBC,oDAAoD;AAC5B,WAAO,GAAG,IAAI,AAAP,CAAO,CAAM,oBAAoB;AACxC,WAAO,GAAG,IAAI,AAAP,CAAO,CAAM,oBAAoB;AACxC,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,4BAA4B;AAChD,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,4BAA4B;AAChD,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,sBAAsB;AAC1C,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,uBAAuB;AAC3C,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,oBAAoB;AACxC,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,qBAAqB;AACzC,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,sBAAsB;AAC1C,YAAQ,GAAG,IAAI,AAAP,CAAO,CAAK,uBAAuB;AAC3C,UAAM,GAAG,IAAI,AAAP,CAAO,CAAO,iBAAiB;AACrC,WAAO,GAAG,IAAI,AAAP,CAAO,CAAM,6BAA6B;AACjD,WAAO,GAAG,IAAI,AAAP,CAAO,CAAM,8BAA8B;AAClD,WAAO,GAAG,IAAI,AAAP,CAAO,CAAM,0BAA0B;AAC9C,WAAO,GAAG,IAAI,AAAP,CAAO,CAAM,4BAA4B;AAChD,cAAU,GAAG,IAAI,AAAP,CAAO,CAAG,mCAAmC;AAE/E,kBAAkB;AACM,WAAO,GAAG,IAAI,AAAP,CAAO;AACd,WAAO,GAAG,IAAI,AAAP,CAAO;AACd,UAAM,GAAG,IAAI,AAAP,CAAO;AACb,WAAO,GAAG,IAAI,AAAP,CAAO;AACd,WAAO,GAAG,IAAI,AAAP,CAAO;AACd,UAAM,GAAG,IAAI,AAAP,CAAO;AACb,UAAM,GAAG,IAAI,AAAP,CAAO;AACb,WAAO,GAAG,IAAI,AAAP,CAAO,CAAM,kBAAkB;AAEtC,4BAAwB,GAAG,CAAC,AAAJ,CAAI"}