ac6502 1.0.0

package/src/tests/IO/RAMCard.test.ts

@@ -0,0 +1,284 @@
+import { RAMCard } from '../../components/IO/RAMCard'
+
+describe('RAMCard', () => {
+  let ramCard: RAMCard
+
+  beforeEach(() => {
+    ramCard = new RAMCard()
+  })
+
+  describe('Static Properties', () => {
+    it('should have correct total size', () => {
+      expect(RAMCard.TOTAL_SIZE).toBe(256 * 1024)
+    })
+
+    it('should have correct bank size', () => {
+      expect(RAMCard.BANK_SIZE).toBe(1024)
+    })
+
+    it('should have correct number of banks', () => {
+      expect(RAMCard.NUM_BANKS).toBe(256)
+    })
+
+    it('should have correct bank control register address', () => {
+      expect(RAMCard.BANK_CONTROL_REGISTER).toBe(0x3FF)
+    })
+  })
+
+  describe('Initialization', () => {
+    it('should initialize with all data as 0x00', () => {
+      for (let i = 0; i < RAMCard.TOTAL_SIZE; i++) {
+        expect(ramCard.data[i]).toBe(0x00)
+      }
+    })
+
+    it('should start on bank 0', () => {
+      expect(ramCard.currentBank).toBe(0)
+    })
+
+    it('should have IRQ and NMI callbacks', () => {
+      expect(typeof ramCard.raiseIRQ).toBe('function')
+      expect(typeof ramCard.raiseNMI).toBe('function')
+    })
+  })
+
+  describe('Reading', () => {
+    it('should read data from current bank', () => {
+      ramCard.data[100] = 0x42
+      expect(ramCard.read(100)).toBe(0x42)
+    })
+
+    it('should read from address 0', () => {
+      ramCard.data[0] = 0xAB
+      expect(ramCard.read(0)).toBe(0xAB)
+    })
+
+    it('should read from address 0x3FE (last data address)', () => {
+      ramCard.write(0x3FE, 0xCD)
+      expect(ramCard.read(0x3FE)).toBe(0xCD)
+    })
+
+    it('should read bank control register and return current bank', () => {
+      ramCard.currentBank = 0
+      expect(ramCard.read(RAMCard.BANK_CONTROL_REGISTER)).toBe(0)
+
+      ramCard.currentBank = 42
+      expect(ramCard.read(RAMCard.BANK_CONTROL_REGISTER)).toBe(42)
+
+      ramCard.currentBank = 255
+      expect(ramCard.read(RAMCard.BANK_CONTROL_REGISTER)).toBe(255)
+    })
+  })
+
+  describe('Writing', () => {
+    it('should write data to current bank', () => {
+      ramCard.write(100, 0x42)
+      expect(ramCard.data[100]).toBe(0x42)
+    })
+
+    it('should write to address 0', () => {
+      ramCard.write(0, 0xAB)
+      expect(ramCard.data[0]).toBe(0xAB)
+    })
+
+    it('should write to address 0x3FE', () => {
+      ramCard.write(0x3FE, 0xCD)
+      expect(ramCard.read(0x3FE)).toBe(0xCD)
+    })
+
+    it('should mask data to 0xFF', () => {
+      ramCard.write(100, 0x1FF)
+      expect(ramCard.data[100]).toBe(0xFF)
+
+      ramCard.write(101, 0x100)
+      expect(ramCard.data[101]).toBe(0x00)
+
+      ramCard.write(102, 0x142)
+      expect(ramCard.data[102]).toBe(0x42)
+    })
+
+    it('should switch banks via bank control register', () => {
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 5)
+      expect(ramCard.currentBank).toBe(5)
+    })
+
+    it('should mask bank number to 0xFF', () => {
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 0x1FF)
+      expect(ramCard.currentBank).toBe(0xFF)
+
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 0x100)
+      expect(ramCard.currentBank).toBe(0x00)
+    })
+  })
+
+  describe('Bank Switching', () => {
+    it('should isolate data between banks', () => {
+      // Write to address 50 in bank 0
+      ramCard.write(50, 0x11)
+      expect(ramCard.read(50)).toBe(0x11)
+
+      // Switch to bank 1
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 1)
+      expect(ramCard.read(50)).toBe(0x00)
+
+      // Write different value to address 50 in bank 1
+      ramCard.write(50, 0x22)
+      expect(ramCard.read(50)).toBe(0x22)
+
+      // Switch back to bank 0
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 0)
+      expect(ramCard.read(50)).toBe(0x11)
+    })
+
+    it('should persist data in each bank', () => {
+      // Bank 0
+      ramCard.write(100, 0xAA)
+      ramCard.write(200, 0xBB)
+
+      // Switch to bank 1
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 1)
+      ramCard.write(100, 0xCC)
+      ramCard.write(200, 0xDD)
+
+      // Switch to bank 2
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 2)
+      ramCard.write(100, 0xEE)
+
+      // Verify data in bank 2
+      expect(ramCard.read(100)).toBe(0xEE)
+
+      // Switch to bank 1
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 1)
+      expect(ramCard.read(100)).toBe(0xCC)
+      expect(ramCard.read(200)).toBe(0xDD)
+
+      // Switch to bank 0
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 0)
+      expect(ramCard.read(100)).toBe(0xAA)
+      expect(ramCard.read(200)).toBe(0xBB)
+    })
+
+    it('should switch between all 256 banks', () => {
+      // Write unique val to each bank at address 0
+      for (let bank = 0; bank < RAMCard.NUM_BANKS; bank++) {
+        ramCard.write(RAMCard.BANK_CONTROL_REGISTER, bank)
+        ramCard.write(0, bank & 0xFF)
+      }
+
+      // Verify each bank has correct value
+      for (let bank = 0; bank < RAMCard.NUM_BANKS; bank++) {
+        ramCard.write(RAMCard.BANK_CONTROL_REGISTER, bank)
+        expect(ramCard.read(0)).toBe(bank & 0xFF)
+      }
+    })
+  })
+
+  describe('Reset', () => {
+    it('should not reset on warm start', () => {
+      ramCard.write(100, 0x42)
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 42)
+
+      ramCard.reset(false)
+
+      expect(ramCard.data[100]).toBe(0x42)
+      expect(ramCard.currentBank).toBe(42)
+    })
+
+    it('should reset all data on cold start', () => {
+      ramCard.write(100, 0x42)
+      ramCard.write(500, 0xAB)
+      ramCard.write(RAMCard.TOTAL_SIZE - 1, 0xFF)
+
+      ramCard.reset(true)
+
+      expect(ramCard.data[100]).toBe(0x00)
+      expect(ramCard.data[500]).toBe(0x00)
+      expect(ramCard.data[RAMCard.TOTAL_SIZE - 1]).toBe(0x00)
+    })
+
+    it('should reset to bank 0 on cold start', () => {
+      ramCard.write(RAMCard.BANK_CONTROL_REGISTER, 100)
+      expect(ramCard.currentBank).toBe(100)
+
+      ramCard.reset(true)
+
+      expect(ramCard.currentBank).toBe(0)
+    })
+
+    it('should clear all RAM on cold start', () => {
+      // Fill multiple banks with data
+      for (let bank = 0; bank < 10; bank++) {
+        ramCard.write(RAMCard.BANK_CONTROL_REGISTER, bank)
+        for (let addr = 0; addr < RAMCard.BANK_SIZE; addr++) {
+          ramCard.write(addr, bank)
+        }
+      }
+
+      ramCard.reset(true)
+
+      // Verify all data is cleared
+      for (let i = 0; i < RAMCard.TOTAL_SIZE; i++) {
+        expect(ramCard.data[i]).toBe(0x00)
+      }
+    })
+  })
+
+  describe('Tick', () => {
+    it('should have tick method that does nothing', () => {
+      expect(() => {
+        ramCard.tick(1000000)
+      }).not.toThrow()
+    })
+  })
+
+  describe('IO Interface Implementation', () => {
+    it('should implement IO interface methods', () => {
+      expect(typeof ramCard.read).toBe('function')
+      expect(typeof ramCard.write).toBe('function')
+      expect(typeof ramCard.tick).toBe('function')
+      expect(typeof ramCard.reset).toBe('function')
+    })
+
+    it('should have raiseIRQ and raiseNMI callbacks', () => {
+      expect(ramCard.raiseIRQ()).toBeUndefined()
+      expect(ramCard.raiseNMI()).toBeUndefined()
+    })
+  })
+
+  describe('Integration', () => {
+    it('should allow multiple write/read cycles', () => {
+      const testValues = [0x00, 0x42, 0xFF, 0x80, 0x01]
+
+      for (const value of testValues) {
+        ramCard.write(250, value)
+        expect(ramCard.read(250)).toBe(value)
+      }
+    })
+
+    it('should handle rapid bank switches', () => {
+      for (let i = 0; i < 100; i++) {
+        ramCard.write(RAMCard.BANK_CONTROL_REGISTER, i % 256)
+        ramCard.write(0, i & 0xFF)
+      }
+
+      // Check final state (last iteration i=99)
+      expect(ramCard.currentBank).toBe(99 % 256)
+      expect(ramCard.read(0)).toBe(99 & 0xFF)
+    })
+
+    it('should handle boundary addresses correctly', () => {
+      // Test address 0
+      ramCard.write(0, 0x11)
+      expect(ramCard.read(0)).toBe(0x11)
+
+      // Test address 0x3FE
+      ramCard.write(0x3FE, 0x22)
+      expect(ramCard.read(0x3FE)).toBe(0x22)
+
+      // Test bank control register
+      ramCard.write(0x3FF, 5)
+      expect(ramCard.currentBank).toBe(5)
+      expect(ramCard.read(0x3FF)).toBe(5)
+    })
+  })
+})

package/src/tests/IO/RTCCard.test.ts

@@ -0,0 +1,222 @@
+import { RTCCard } from '../../components/IO/RTCCard'
+
+const bcdToDecimal = (bcd: number): number => (((bcd >> 4) & 0x0f) * 10) + (bcd & 0x0f)
+
+const enableTransfers = (rtc: RTCCard): void => {
+	rtc.write(0x0f, 0x80)
+	rtc.tick(1)
+}
+
+const setTime = (rtc: RTCCard, values: {
+	seconds: number
+	minutes: number
+	hours: number
+	dayOfWeek: number
+	date: number
+	month: number
+	year: number
+	century: number
+}): void => {
+	enableTransfers(rtc)
+	rtc.write(0x00, values.seconds)
+	rtc.write(0x01, values.minutes)
+	rtc.write(0x02, values.hours)
+	rtc.write(0x03, values.dayOfWeek)
+	rtc.write(0x04, values.date)
+	rtc.write(0x05, values.month | 0x80)
+	rtc.write(0x06, values.year)
+	rtc.write(0x07, values.century)
+}
+
+describe('RTCCard', () => {
+	let rtc: RTCCard
+
+	beforeEach(() => {
+		rtc = new RTCCard()
+	})
+
+	describe('Initialization', () => {
+		it('should initialize with valid BCD time and EOSC enabled', () => {
+			const seconds = rtc.read(0x00)
+			const minutes = rtc.read(0x01)
+			const hours = rtc.read(0x02)
+			const dayOfWeek = rtc.read(0x03)
+			const date = rtc.read(0x04)
+			const month = rtc.read(0x05)
+			const year = rtc.read(0x06)
+			const century = rtc.read(0x07)
+
+			expect(dayOfWeek).toBeGreaterThanOrEqual(1)
+			expect(dayOfWeek).toBeLessThanOrEqual(7)
+
+			expect(bcdToDecimal(seconds)).toBeGreaterThanOrEqual(0)
+			expect(bcdToDecimal(seconds)).toBeLessThan(60)
+			expect(bcdToDecimal(minutes)).toBeGreaterThanOrEqual(0)
+			expect(bcdToDecimal(minutes)).toBeLessThan(60)
+			expect(bcdToDecimal(hours)).toBeGreaterThanOrEqual(0)
+			expect(bcdToDecimal(hours)).toBeLessThan(24)
+			expect(bcdToDecimal(date)).toBeGreaterThanOrEqual(1)
+			expect(bcdToDecimal(date)).toBeLessThanOrEqual(31)
+			expect(bcdToDecimal(month & 0x1f)).toBeGreaterThanOrEqual(1)
+			expect(bcdToDecimal(month & 0x1f)).toBeLessThanOrEqual(12)
+			expect(bcdToDecimal(year)).toBeGreaterThanOrEqual(0)
+			expect(bcdToDecimal(year)).toBeLessThanOrEqual(99)
+			expect(bcdToDecimal(century)).toBeGreaterThanOrEqual(0)
+			expect(bcdToDecimal(century)).toBeLessThanOrEqual(39)
+
+			expect(month & 0x80).toBe(0x80)
+		})
+	})
+
+	describe('Registers', () => {
+		it('should mask day of week reads to 3 bits', () => {
+			rtc.write(0x03, 0xff)
+			expect(rtc.read(0x03)).toBe(0x07)
+		})
+
+		it('should clear control flags on Control A read', () => {
+			rtc.reset(true)
+			const first = rtc.read(0x0e)
+			const second = rtc.read(0x0e)
+
+			expect(first & 0x04).toBe(0x04)
+			expect(second & 0x0f).toBe(0)
+		})
+
+		it('should raise IRQ when KSF is set and KIE enabled', () => {
+			const mockIRQ = jest.fn()
+			rtc.raiseIRQ = mockIRQ
+
+			rtc.reset(true)
+			rtc.write(0x0f, 0x04)
+
+			expect(mockIRQ).toHaveBeenCalledTimes(1)
+			const controlA = rtc.read(0x0e)
+			expect(controlA & 0x01).toBe(0x01)
+		})
+	})
+
+	describe('Extended RAM', () => {
+		it('should write and read RAM at the address pointer', () => {
+			rtc.write(0x10, 0x10)
+			rtc.write(0x13, 0x5a)
+			rtc.write(0x10, 0x10)
+
+			expect(rtc.read(0x13)).toBe(0x5a)
+		})
+
+		it('should auto-increment RAM address when enabled', () => {
+			rtc.write(0x0f, 0x20)
+			rtc.write(0x10, 0x10)
+			rtc.write(0x13, 0x11)
+			rtc.write(0x13, 0x22)
+
+			expect(rtc.read(0x10)).toBe(0x12)
+
+			rtc.write(0x10, 0x10)
+			expect(rtc.read(0x13)).toBe(0x11)
+			expect(rtc.read(0x13)).toBe(0x22)
+			expect(rtc.read(0x10)).toBe(0x12)
+		})
+	})
+
+	describe('Timekeeping', () => {
+		it('should advance time when TE is enabled', () => {
+			setTime(rtc, {
+				seconds: 0x00,
+				minutes: 0x00,
+				hours: 0x00,
+				dayOfWeek: 0x01,
+				date: 0x01,
+				month: 0x01,
+				year: 0x00,
+				century: 0x20
+			})
+
+			rtc.tick(1)
+
+			expect(rtc.read(0x00)).toBe(0x01)
+		})
+
+		it('should stop time when oscillator is disabled', () => {
+			setTime(rtc, {
+				seconds: 0x10,
+				minutes: 0x00,
+				hours: 0x00,
+				dayOfWeek: 0x01,
+				date: 0x01,
+				month: 0x01,
+				year: 0x00,
+				century: 0x20
+			})
+
+			rtc.write(0x05, 0x01)
+			rtc.tick(1)
+
+			expect(rtc.read(0x00)).toBe(0x10)
+		})
+	})
+
+	describe('Alarm', () => {
+		it('should set TDF and raise IRQ when alarm matches', () => {
+			const mockIRQ = jest.fn()
+			rtc.raiseIRQ = mockIRQ
+
+			setTime(rtc, {
+				seconds: 0x00,
+				minutes: 0x00,
+				hours: 0x00,
+				dayOfWeek: 0x01,
+				date: 0x01,
+				month: 0x01,
+				year: 0x00,
+				century: 0x20
+			})
+
+			rtc.write(0x08, 0x01)
+			rtc.write(0x09, 0x00)
+			rtc.write(0x0a, 0x00)
+			rtc.write(0x0b, 0x01)
+			rtc.write(0x0f, 0x88)
+
+			rtc.tick(1)
+
+			expect(mockIRQ).toHaveBeenCalledTimes(1)
+			const controlA = rtc.read(0x0e)
+			expect(controlA & 0x08).toBe(0x08)
+			expect(controlA & 0x01).toBe(0x01)
+		})
+	})
+
+	describe('Watchdog', () => {
+		it('should raise IRQ when watchdog expires with WDS=0', () => {
+			const mockIRQ = jest.fn()
+			rtc.raiseIRQ = mockIRQ
+
+			rtc.write(0x0f, 0x02)
+			rtc.write(0x0c, 0x01)
+			rtc.write(0x0d, 0x00)
+
+			rtc.tick(1)
+
+			expect(mockIRQ).toHaveBeenCalledTimes(1)
+			const controlA = rtc.read(0x0e)
+			expect(controlA & 0x02).toBe(0x02)
+			expect(controlA & 0x01).toBe(0x01)
+		})
+
+		it('should raise NMI and clear WDE when WDS=1', () => {
+			const mockNMI = jest.fn()
+			rtc.raiseNMI = mockNMI
+
+			rtc.write(0x0f, 0x03)
+			rtc.write(0x0c, 0x01)
+			rtc.write(0x0d, 0x00)
+
+			rtc.tick(1)
+
+			expect(mockNMI).toHaveBeenCalledTimes(1)
+			expect(rtc.read(0x0f) & 0x02).toBe(0)
+		})
+	})
+})