@zigc/lib 0.17.0-dev.607 → 0.17.0-dev.644

package/libc/include/m68k-netbsd-none/m68k/mmu_40.h

@@ -0,0 +1,232 @@
+/*	$NetBSD: mmu_40.h,v 1.4 2025/07/08 11:45:25 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 2023 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _M68K_MMU_40_H_
+#define	_M68K_MMU_40_H_
+
+/*
+ * Translation table structures for the 68040 MMU.
+ *
+ * The 68040 MMU uses a 3-level tree structure.  The root (L1) and
+ * and pointer (L2) tables contain the base addresses of the tables
+ * at the lext level, and the page (L3) tables contain the addresses
+ * of the page descriptors, which may either contain the address of
+ * a physical page (4K or 8K) directly, or point to an indirect
+ * descriptor which points to the physical page.
+ *
+ * The L1 and L2 tables contain 128 4-byte descriptors, and are thus 512
+ * bytes in size.  Each of the 128 L1 descriptors corresponds to a 32MB
+ * region of address space.  Each of the 128 L2 descriptors corresponds
+ * to a 256KB region of address space.
+ *
+ * For 8K pages, the L3 tables contain 32 4-byte descriptors, and are
+ * thus 128 bytes in size.
+ *
+ *  31          25 24          18 17      13 12                       0
+ * |              |              |          |                          |
+ *  11111111111111 22222222222222 3333333333 ..........................
+ *       Root         Pointer        Page               Page
+ *       Index         Index         Index             Offset
+ *
+ * For 4K pages, the L3 tables contain 64 4-byte descriptors, and are
+ * thus 256 bytes in size.
+ *
+ *  31          25 24          18 17        12 11                     0
+ * |              |              |            |                        |
+ *  11111111111111 22222222222222 333333333333 ........................
+ *       Root         Pointer         Page              Page
+ *       Index         Index          Index            Offset
+ *
+ *                       Logical Address Format
+ */
+
+#define	LA40_L1_NBITS	7U
+#define	LA40_L1_SHIFT	25
+#define	LA40_L2_NBITS	7U
+#define	LA40_L2_SHIFT	18
+#define	LA40_L3_NBITS	(32U - LA40_L1_NBITS - LA40_L2_NBITS - PGSHIFT)
+#define	LA40_L3_SHIFT	PGSHIFT
+
+#define	LA40_L1_COUNT	__BIT(LA40_L1_NBITS)
+#define	LA40_L2_COUNT	__BIT(LA40_L2_NBITS)
+#define	LA40_L3_COUNT	__BIT(LA40_L3_NBITS)
+
+#define	LA40_L1_MASK	(__BITS(0,(LA40_L1_NBITS - 1)) << LA40_L1_SHIFT)
+#define	LA40_L2_MASK	(__BITS(0,(LA40_L2_NBITS - 1)) << LA40_L2_SHIFT)
+#define	LA40_L3_MASK	(__BITS(0,(LA40_L3_NBITS - 1)) << LA40_L3_SHIFT)
+
+/* N.B. all tables must be aligned to their size */
+#define	TBL40_L1_SIZE	(LA40_L1_COUNT * sizeof(uint32_t))
+#define	TBL40_L2_SIZE	(LA40_L2_COUNT * sizeof(uint32_t))
+#define	TBL40_L3_SIZE	(LA40_L3_COUNT * sizeof(uint32_t))
+
+#define	LA40_RI(va)	__SHIFTOUT((va), LA40_L1_MASK)	/* root index */
+#define	LA40_PI(va)	__SHIFTOUT((va), LA40_L2_MASK)	/* pointer index */
+#define	LA40_PGI(va)	__SHIFTOUT((va), LA40_L3_MASK)	/* page index */
+
+#define	LA40_TRUNC_L1(va) (((vaddr_t)(va)) & LA40_L1_MASK)
+#define	LA40_TRUNC_L2(va) (((vaddr_t)(va)) & (LA40_L1_MASK | LA40_L2_MASK))
+
+/*
+ * The PTE format for L1 and L2 tables (Upper Tables).
+ */
+#define	UTE40_PTA	__BITS(9,31)	/* Pointer Table Address (L1 PTE) */
+					/* Page Table Address (L2 PTE) */
+#define	UTE40_PGTA	__BITS(8 - (13 - PGSHIFT),31)
+#define	UTE40_U		__BIT(3)	/* Used (referenced) */
+#define	UTE40_W		__BIT(2)	/* Write Protected */
+#define	UTE40_UDT	__BITS(0,1)	/* Upper Descriptor Type */
+					/* 00 or 01 -- Invalid */
+					/* 10 or 11 -- Resident */
+
+#define	UTE40_INVALID	__SHIFTIN(0, UTE_UDT)
+#define	UTE40_RESIDENT	__SHIFTIN(2, UTE_UDT)
+
+/*
+ * The PTE format for L3 tables.
+ *
+ * Some notes:
+ *
+ * - PFLUSH variants that specify non-global entries do not invalidate
+ *   global entries.  If these PFLUSH variants are not used, then the G
+ *   bit can be used as a software-defined bit.
+ *
+ * - The UR bits are "reserved for use by the user", so can be
+ *   used as software-defined bits.
+ *
+ * - The U0 and U1 "User Page Attribute" bits should *not* be used
+ *   as software-defined bits; they are reflected on the UPA0 and UPA1
+ *   CPU signals if an external bus transfer results from the access,
+ *   meaning that they may have system-specific side-effects.
+ */
+#define	PTE40_PGA	__BITS(PGSHIFT,31) /* Page Physical Address */
+#define	PTE40_UR_x	__BIT(12)	/* User Reserved (extra avail if 8K) */
+#define	PTE40_UR	__BIT(11)	/* User Reserved */
+#define	PTE40_G		__BIT(10)	/* Global */
+#define	PTE40_U1	__BIT(9)	/* User Page Attribute 1 */
+#define	PTE40_U0	__BIT(8)	/* User Page Attribute 0 */
+#define	PTE40_S		__BIT(7)	/* Supervisor Protected */
+#define	PTE40_CM	__BITS(5,6)	/* Cache Mode */
+					/* 00 -- write-through */
+					/* 01 -- copy-back */
+					/* 10 -- non-cacheable, serialized */
+					/* 11 -- non-cacheable */
+#define	PTE40_M		__BIT(4)	/* Modified */
+#define	PTE40_U		__BIT(3)	/* Used (referenced) */
+#define	PTE40_W		__BIT(2)	/* Write Protected */
+#define	PTE40_PDT	__BITS(0,1)	/* Page Descriptor Type */
+					/* 00       -- Invalid */
+					/* 01 or 11 -- Resident */
+					/* 10       -- Indirect */
+
+#define	PTE40_CM_WT	__SHIFTIN(0, PTE40_CM)
+#define	PTE40_CM_CB	__SHIFTIN(1, PTE40_CM)
+#define	PTE40_CM_NC_SER	__SHIFTIN(2, PTE40_CM)
+#define	PTE40_CM_NC	__SHIFTIN(3, PTE40_CM)
+
+#define	PTE40_INVALID	__SHIFTIN(0, PTE40_PDT)
+#define	PTE40_RESIDENT	__SHIFTIN(1, PTE40_PDT)
+#define	PTE40_INDIRECT	__SHIFTIN(2, PTE40_PDT)
+
+/*
+ * MMU registers (and the sections in the 68040 manual that
+ * describe them).
+ */
+
+/*
+ * 3.1.1 -- User and Supervisor Root Pointer Registers (32-bit)
+ *
+ * URP and SRP contain the physical address of the L1 table for
+ * user and supervisor space, respectively.  Bits 8-0 of the address
+ * must be 0.
+ */
+
+/*
+ * 3.1.2 -- Translation Control Register (16-bit)
+ */
+#define	TCR40_E		__BIT(15)	/* enable translation */
+#define	TCR40_P		__BIT(14)	/* page size: 0=4K 1=8K */
+
+/*
+ * 3.1.3 -- Transparent Translation Registers (32-bit)
+ *
+ * There are 2 data translation registers (DTTR0, DTTR1) and 2
+ * instruction translation registers (ITTR0, ITTR1).
+ */
+#define	TTR40_LAB	__BITS(24,31)	/* logical address base */
+#define	TTR40_LAM	__BITS(16,23)	/* logical address mask */
+#define	TTR40_E		__BIT(15)	/* enable TTR */
+#define	TTR40_SFIELD	__BITS(13,14)	/* Supervisor Mode field (see below) */
+#define	TTR40_U1	PTE40_U1
+#define	TTR40_U0	PTE40_U0
+#define	TTR40_CM	PTE40_CM
+#define	TTR40_W		PTE40_W
+
+#define	TTR40_USER	__SHIFTIN(0, TTR40_SFIELD)
+#define	TTR40_SUPER	__SHIFTIN(1, TTR40_SFIELD)
+#define	TTR40_BOTH	__SHIFTIN(2, TTR40_SFIELD)
+
+/*
+ * 3.1.4 -- MMU Status Register
+ *
+ * N.B. If 8K pages are in use, bit 12 of the PA field is **undefined**.
+ */
+#define	MMUSR40_PA	PTE40_PGA
+#define	MMUSR40_B	__BIT(11)	/* bus error */
+#define	MMUSR40_G	PTE40_G
+#define	MMUSR40_U1	PTE40_U1
+#define	MMUSR40_U0	PTE40_U0
+#define	MMUSR40_S	PTE40_S
+#define	MMUSR40_CM	PTE40_CM
+#define	MMUSR40_M	PTE40_M
+#define	MMUSR40_W	PTE40_W
+#define	MMUSR40_T	__BIT(1)	/* Transparent Translation hit */
+#define	MMUSR40_R	PTE40_RESIDENT
+
+#ifdef _KERNEL
+/*
+ * TT register value indices in the mmu_ttregs[] array.  Note that asm
+ * code makes assumptions about these indices, to change them at your
+ * peril.
+ */
+extern uint32_t mmu_tt40[];
+#define	MMU_TTREG_ITT0	0	/* same order as CPU reg numbers */
+#define	MMU_TTREG_ITT1	1
+#define	MMU_TTREG_DTT0	2
+#define	MMU_TTREG_DTT1	3
+#define	MMU_NTTREGS40
+
+void	mmu_load_urp40(paddr_t);
+void	mmu_load_urp60(paddr_t);
+void	mmu_load_tt40(uint32_t *);
+#endif /* _KERNEL */
+
+#endif /* _M68K_MMU_40_H_ */

package/libc/include/m68k-netbsd-none/m68k/mmu_51.h

@@ -0,0 +1,273 @@
+/*	$NetBSD: mmu_51.h,v 1.4 2024/02/08 20:11:56 andvar Exp $	*/
+
+/*-
+ * Copyright (c) 1997, 2023 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jeremy Cooper and by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _M68K_MMU_51_H_
+#define	_M68K_MMU_51_H_
+
+/*
+ * Translation table structures for the 68851 MMU.
+ *
+ * The 68851 MMU (as well as the 68030's built-in MMU) are pretty flexible and
+ * can use a 1, 2, 3, or 4-level tree structure and a number of page sizes.
+ *
+ * The logical address format is defined as:
+ *
+ *  31                                                                0
+ * |        |          |          |          |          |              |
+ *  SSSSSSSS AAAAAAAAAA BBBBBBBBBB CCCCCCCCCC DDDDDDDDDD PPPPPPPPPPPPPP
+ *  Initial   A Index    B Index    C Index    D Index    Page Offset
+ *   Shift
+ *
+ * The Initial Shift, and number of A, B, C, and D index bits are defined
+ * in the Translation Control register.  Once the MMU encounters a tree
+ * level where the number of index bits is 0, tree traversal stops.  The
+ * values of IS + TIA + TIB + TIC + TID + page offset must equal 32.  For
+ * example, for a 2-level arrangment using 4KB pages where all 32-bits of
+ * the address are significant:
+ *
+ *     IS  TIA  TIB  TIC  TID  page
+ *	0 + 10 + 10 +  0 +  0 +  12 == 32
+ */
+
+/*
+ * The 68851 has 3 descriptor formats:
+ *
+ *	Long Table Descriptors		(8 byte)
+ *	Short Table Descriptors		(4 byte)
+ *	Page Descriptors		(4 byte)
+ *
+ * These occupy the lower 2 bits of each descriptor and the root pointers.
+ */
+#define	DT51_INVALID	0
+#define	DT51_PAGE	1	/* points to a page */
+#define	DT51_SHORT	2	/* points to a short entry table */
+#define	DT51_LONG	3	/* points to a long entry table */
+
+/*
+ * Long Format Table Descriptor
+ *
+ *  63                                                             48
+ *  +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
+ *  |L/U|                 LIMIT                                     |
+ *  +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
+ *  |    RAL    |    WAL    |SG | S | 0 | 0 | 0 | 0 | U |WP |  DT   |
+ *  +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
+ *  |              TABLE PHYSICAL ADDRESS (BITS 31-16)              |
+ *  +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+
+ *  |       TABLE PHYSICAL ADDRESS (15-4)           |     UNUSED    |
+ *  +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+
+ *  15                                                              0
+ *
+ * DT is either 2 or 3, depending on what next table descriptor format is.
+ */
+struct mmu51_ldte {		/* 'dte' stands for 'descriptor table entry' */
+	uint32_t	ldte_attr;
+	uint32_t	ldte_addr;
+};
+#define	DTE51_ADDR	__BITS(4,31)	/* table address mask */
+#define	DTE51_LOWER	__BIT(31)	/* L: Index limit is lower limit */
+#define	DTE51_LIMIT	__BITS(16,30)	/* L: Index limit */
+#define	DTE51_RAL	__BITS(13,15)	/* L: Read Access Level */
+#define	DTE51_WAL	__BITS(10,12)	/* L: Write Access Level */
+#define	DTE51_SG	__BIT(9)	/* L: Shared Globally */
+#define	DTE51_S		__BIT(8)	/* L: Supervisor protected */
+#define	DTE51_U		__BIT(3)	/* Used */
+#define	DTE51_WP	__BIT(2)	/* Write Protected */
+
+/*
+ * Short Format Table Descriptor
+ *
+ * 31                                                             16
+ * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
+ * |           TABLE PHYSICAL BASE ADDRESS (BITS 31-16)            |
+ * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+
+ * | TABLE PHYSICAL BASE ADDRESS (15-4)            | U |WP |  DT   |
+ * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+
+ * 15                                                              0
+ *
+ * DT is either 2 or 3, depending on what next table descriptor format is.
+ */
+
+/*
+ * Long Format Page Descriptor (Level A table only)
+ *
+ *  63                                                             48
+ *  +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
+ *  |                          UNUSED                               |
+ *  +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
+ *  |    RAL    |    WAL    |SG | S | G |CI | L | M | U |WP |DT (01)|
+ *  +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
+ *  |               PAGE PHYSICAL ADDRESS (BITS 31-16)              |
+ *  +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
+ *  | PAGE PHYS. ADDRESS (15-8)     |            UNUSED             |
+ *  +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
+ *  15                                                              0
+ *
+ * N.B. Unused bits of the page address (if the page size is larger
+ * than 256 bytes) can be used as software-defined PTE bits.
+ */
+struct mmu51_lpte {		/* 'pte' stands for 'page table entry' */
+	uint32_t	lpte_attr;
+	uint32_t	lpte_addr;
+};
+#define	PTE51_ADDR	__BITS(8,31)	/* page address mask */
+#define	PTE51_RAL	__BITS(13,15)	/* L: Read Access Level */
+#define	PTE51_WAL	__BITS(10,12)	/* L: Write Access Level */
+#define	PTE51_SG	__BIT(9)	/* L: Shared Globally */
+#define	PTE51_S		__BIT(8)	/* L: Supervisor protected */
+#define	PTE51_G		__BIT(7)	/* Gate allowed */
+#define	PTE51_CI	__BIT(6)	/* Cache inhibit */
+#define	PTE51_L		__BIT(5)	/* Lock entry */
+#define	PTE51_M		__BIT(4)	/* Modified */
+#define	PTE51_U		__BIT(3)	/* Used */
+#define	PTE51_WP	__BIT(2)	/* Write Protected */
+
+/*
+ * Short Format Page Descriptor
+ *
+ * 31                                                             16
+ * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
+ * |            PAGE PHYSICAL BASE ADDRESS (BITS 31-16)            |
+ * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+
+ * | PAGE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (01)|
+ * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+
+ * 15                                                              0
+ *
+ * N.B. Unused bits of the page address (if the page size is larger
+ * than 256 bytes) can be used as software-defined PTE bits.
+ */
+
+/*
+ * MMU registers (and the sections in the 68851 manual that
+ * describe them).
+ */
+
+/*
+ * 5.1.4 -- Root Pointer
+ * (and also 6.1.1)
+ *
+ * This is a 64-bit register.  The upper 32 bits contain configuration
+ * information, and the lower 32 bits contain the A table address.
+ * Bits 3-0 of the address must be 0.  The root pointer is essentially
+ * a long format table descriptor with only the U/L, limit, and SG bits.
+ *
+ * The 68851 has 3 root pointers:
+ *
+ * CRP		CPU root pointer, for user accesses
+ * SRP		Supervisor root pointer
+ * DRP		DMA root pointer, for IOMMU functionality (not on '030)
+ *
+ * Selection of root pointer is as follows:
+ *
+ *	FC3	FC2	SRE		Root pointer used
+ *	 0	 0	 0		      CRP
+ *	 0	 0	 1		      CRP
+ *	 0	 1	 0		      CRP
+ *	 0	 1	 1		      SRP
+ *	 1	 x	 x		      DRP
+ */
+struct mmu51_rootptr {
+	unsigned long	rp_attr;	/* Lower/Upper Limit and access flags */
+	unsigned long	rp_addr;	/* Physical Base Address */
+};
+
+/*
+ * 6.1.2 -- PMMU Cache Status (PCSR) (16-bit)
+ */
+#define	PCSR51_F	__BIT(15)	/* Flush(ed) */
+#define	PCSR51_LW	__BIT(14)	/* Lock Warning */
+#define	PCSR51_TA	__BITS(0,2)	/* Task Alias (not '030) */
+
+/*
+ * 6.1.3 -- Translation Control (TCR) (32-bit)
+ */
+#define	TCR51_E		__BIT(31)	/* Enable translation */
+#define	TCR51_SRE	__BIT(25)	/* Supervisor Root Enable */
+#define	TCR51_FCL	__BIT(24)	/* Function Code Lookup */
+#define	TCR51_PS	__BITS(20,23)	/* Page Size (see below) */
+#define	TCR51_IS	__BITS(16,19)	/* Initial Shift */
+#define	TCR51_TIA	__BITS(12,15)	/* Table A Index bits */
+#define	TCR51_TIB	__BITS(8,11)	/* Table B Index bits */
+#define	TCR51_TIC	__BITS(4,7)	/* Table C Index bits */
+#define	TCR51_TID	__BITS(0,3)	/* Table D Index bits */
+
+/*
+ * Astute readers will note that the value in the PS field is
+ * log2(PAGE_SIZE).
+ */
+#define	TCR51_PS_256	__SHIFTIN(0x8, TCR51_PS)
+#define	TCR51_PS_512	__SHIFTIN(0x9, TCR51_PS)
+#define	TCR51_PS_1K	__SHIFTIN(0xa, TCR51_PS)
+#define	TCR51_PS_2K	__SHIFTIN(0xb, TCR51_PS)
+#define	TCR51_PS_4K	__SHIFTIN(0xc, TCR51_PS)
+#define	TCR51_PS_8K	__SHIFTIN(0xd, TCR51_PS)
+#define	TCR51_PS_16K	__SHIFTIN(0xe, TCR51_PS)
+#define	TCR51_PS_32K	__SHIFTIN(0xf, TCR51_PS)
+
+/*
+ * 6.1.4 -- Current Access Level (8-bit)
+ * 6.1.5 -- Validate Access Level
+ */
+#define	CAL51_AL	__BITS(5,7)
+
+/*
+ * 6.1.6 -- Stack Change Control (8-bit)
+ */
+
+/*
+ * 6.1.7 -- Access Control (16-bit)
+ */
+#define	AC51_MC		__BIT(7)	/* Module Control */
+#define	AC51_ALC	__BITS(4,5)	/* Access Level Control */
+#define	AC51_MDS	__BITS(0,1)	/* Module Descriptor Size */
+
+/*
+ * 6.1.8 -- PMMU Status Register (PSR) (16-bit)
+ */
+#define	PSR51_B		__BIT(15)	/* Bus Error */
+#define	PSR51_L		__BIT(14)	/* Limit Violation */
+#define	PSR51_S		__BIT(13)	/* Supervisor Violation */
+#define	PSR51_A		__BIT(12)	/* Access Level Violation */
+#define	PSR51_W		__BIT(11)	/* Write Protected */
+#define	PSR51_I		__BIT(10)	/* Invalid */
+#define	PSR51_M		__BIT(9)	/* Modified */
+#define	PSR51_G		__BIT(8)	/* Gate */
+#define	PSR51_C		__BIT(7)	/* Globally Shareable */
+#define	PSR51_N		__BITS(0,2)	/* Number of levels */
+
+#ifdef _KERNEL
+extern unsigned int protorp[2];
+
+void	mmu_load_urp51(paddr_t);
+void	mmu_load_urp20hp(paddr_t);	/* for convenience */
+#endif /* _KERNEL */
+
+#endif /* _M68K_MMU_51_H_ */

package/libc/include/m68k-netbsd-none/m68k/mutex.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: mutex.h,v 1.11.4.1 2023/08/09 17:42:01 martin Exp $	*/
+/*	$NetBSD: mutex.h,v 1.13 2023/07/12 12:50:12 riastradh Exp $	*/
 
 /*-
  * Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.

package/libc/include/m68k-netbsd-none/m68k/pcb.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: pcb.h,v 1.10 2011/02/08 20:20:16 rmind Exp $	*/
+/*	$NetBSD: pcb.h,v 1.11 2023/09/26 14:33:55 tsutsui Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -49,7 +49,7 @@
  */
 struct pcb {
 	short	pcb_flags;	/* misc. process flags */
-	short	pcb_ps; 	/* processor status word */
+	short	pcb_ps;		/* processor status word */
 	int	__pcb_spare0;
 	int	pcb_usp;	/* user stack pointer */
 	int	pcb_regs[12];	/* D2-D7, A2-A7 */

package/libc/include/m68k-netbsd-none/m68k/pmap_motorola.h

@@ -1,6 +1,6 @@
-/*	$NetBSD: pmap_motorola.h,v 1.37 2021/09/19 10:34:09 andvar Exp $	*/
+/*	$NetBSD: pmap_motorola.h,v 1.43 2023/12/31 21:59:24 thorpej Exp $	*/
 
-/* 
+/*
  * Copyright (c) 1991, 1993
  *	The Regents of the University of California.  All rights reserved.
  *
@@ -35,7 +35,7 @@
  *	@(#)pmap.h	8.1 (Berkeley) 6/10/93
  */
 
-/* 
+/*
  * Copyright (c) 1987 Carnegie-Mellon University
  *
  * This code is derived from software contributed to Berkeley by
@@ -97,6 +97,21 @@ struct pmap {
 	int			pm_ptpages;	/* more stats: PT pages */
 };
 
+/*
+ * Root Pointer attributes for Supervisor and User modes.
+ *
+ * Supervisor:
+ * - No index limit (Lower limit == 0)
+ * - Points to Short format descriptor table.
+ * - Shared Globally
+ *
+ * User:
+ * - No index limit (Lower limit == 0)
+ * - Points to Short format descriptor table.
+ */
+#define	MMU51_SRP_BITS	(DTE51_LOWER | DTE51_SG | DT51_SHORT)
+#define	MMU51_CRP_BITS	(DTE51_LOWER |            DT51_SHORT)
+
 /*
  * MMU specific segment values
  *
@@ -108,7 +123,7 @@ struct pmap {
  *
  * 68020/030 l2 size is chosen per NPTEPG, a number of page table entries
  * per page, to use one whole page for PTEs per one segment table entry,
- * and maybe also because 68020 HP MMU machines use simlar structures.
+ * and maybe also because 68020 HP MMU machines use similar structures.
  *
  * 68040/060 layout is defined by hardware design and not configurable,
  * as defined in <m68k/pte_motorola.h>.
@@ -122,12 +137,19 @@ struct pmap {
  * so they have different values between 020/030 and 040/060.
  */
 							/*  8KB /  4KB	*/
-#define TIB_SHIFT	(PG_SHIFT - 2)			/*   11 /   10	*/
+#define TIB_SHIFT	(PGSHIFT - 2)			/*   11 /   10	*/
 #define TIB_SIZE	(1U << TIB_SHIFT)		/* 2048 / 1024	*/
-#define TIA_SHIFT	(32 - TIB_SHIFT - PG_SHIFT)	/*    8 /   10	*/
+#define TIA_SHIFT	(32 - TIB_SHIFT - PGSHIFT)	/*    8 /   10	*/
 #define TIA_SIZE	(1U << TIA_SHIFT)		/*  256 / 1024	*/
 
-#define SEGSHIFT	(TIB_SHIFT + PG_SHIFT)		/*   24 /   22	*/
+#define	MMU51_TCR_BITS	(TCR51_E | TCR51_SRE |				\
+			 __SHIFTIN(PGSHIFT, TCR51_PS) |			\
+			 __SHIFTIN(TIA_SHIFT, TCR51_TIA) |		\
+			 __SHIFTIN(TIB_SHIFT, TCR51_TIB))
+#define	MMU40_TCR_BITS	(TCR40_E |					\
+			 __SHIFTIN(PGSHIFT - 12, TCR40_P))
+
+#define SEGSHIFT	(TIB_SHIFT + PGSHIFT)		/*   24 /   22	*/
 
 #define NBSEG30		(1U << SEGSHIFT)
 #define NBSEG40		(1U << SG4_SHIFT2)
@@ -142,7 +164,7 @@ struct pmap {
 #define NBSEG		((mmutype == MMU_68040) ? NBSEG40 : NBSEG30)
 #endif
 
-#define SEGOFSET	(NBSEG - 1)	/* byte offset into segment */ 
+#define SEGOFSET	(NBSEG - 1)	/* byte offset into segment */
 
 #define	m68k_round_seg(x)	((((vaddr_t)(x)) + SEGOFSET) & ~SEGOFSET)
 #define	m68k_trunc_seg(x)	((vaddr_t)(x) & ~SEGOFSET)
@@ -170,15 +192,6 @@ struct pmap {
 #define l2tobm(n)	(1U << (n))
 #define bmtol2(n)	(ffs(n) - 1)
 
-/*
- * Macros for speed
- */
-#define	PMAP_ACTIVATE(pmap, loadhw)					\
-{									\
-	if ((loadhw))							\
-		loadustp(m68k_btop((paddr_t)(pmap)->pm_stpa));		\
-}
-
 /*
  * For each struct vm_page, there is a list of all currently valid virtual
  * mappings of that page.  An entry is a pv_entry, the list is pv_table.
@@ -191,12 +204,6 @@ struct pv_entry {
 	struct pmap	*pv_ptpmap;	/* if pv_ptste, pmap for PT page */
 };
 
-#define	active_pmap(pm) \
-	((pm) == pmap_kernel() || (pm) == curproc->p_vmspace->vm_map.pmap)
-#define	active_user_pmap(pm) \
-	(curproc && \
-	 (pm) != pmap_kernel() && (pm) == curproc->p_vmspace->vm_map.pmap)
-
 extern struct pv_header	*pv_table;	/* array of entries, one per page */
 
 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
@@ -247,4 +254,6 @@ void	_pmap_set_page_cacheable(struct pmap *, vaddr_t);
 void	_pmap_set_page_cacheinhibit(struct pmap *, vaddr_t);
 int	_pmap_page_is_cacheable(struct pmap *, vaddr_t);
 
+paddr_t	vtophys(vaddr_t va);
+
 #endif /* !_M68K_PMAP_MOTOROLA_H_ */