@zigc/lib 0.17.0-dev.607 → 0.17.0-dev.644

package/libc/include/generic-netbsd/riscv/profile.h

@@ -0,0 +1,117 @@
+/* $NetBSD: profile.h,v 1.1.60.1 2026/04/02 15:59:59 martin Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RISCV_PROFILE_H_
+#define _RISCV_PROFILE_H_
+
+#include <machine/sysreg.h>
+
+#define	_MCOUNT_DECL void mcount
+
+#define MCOUNT_ASM_NAME "_mcount"
+#define	PLTSYM
+
+#ifdef _LP64
+#define	MCOUNT	MCOUNT_ARCH("8", "sd", "ld")
+#else
+#define	MCOUNT	MCOUNT_ARCH("4", "sw", "lw")
+#endif
+
+#ifdef __PIC__
+#define	_PLT	"@plt"
+#else
+#define	_PLT	/* nothing */	
+#endif
+
+
+#define	MCOUNT_ARCH(_SZREG, _REG_S, _REG_L)	__asm(			\
+"	.text\n"							\
+"	.align	2\n"							\
+"	.type	" MCOUNT_ASM_NAME ",@function\n"			\
+"	.global	" MCOUNT_ASM_NAME "\n"					\
+MCOUNT_ASM_NAME ":\n"							\
+	/*								\
+	 * Preserve registers that could be trashed during mcount, i.e.	\
+	 * caller saved registers.					\
+	 */								\
+"	addi	sp, sp, -(16 * " _SZREG ")\n"				\
+"	" _REG_S "	ra, ( 0 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	t0, ( 1 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	t1, ( 2 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	t2, ( 3 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a0, ( 4 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a1, ( 5 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a2, ( 6 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a3, ( 7 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a4, ( 8 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a5, ( 9 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a6, (10 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	a7, (11 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	t3, (12 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	t4, (13 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	t5, (14 * " _SZREG ")(sp)\n" 			\
+"	" _REG_S "	t6, (15 * " _SZREG ")(sp)\n" 			\
+"	mv	a1, ra\n"						\
+"	call	mcount " _PLT "\n"					\
+	 /* restore caller saved registers */				\
+"	" _REG_L "	ra, ( 0 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	t0, ( 1 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	t1, ( 2 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	t2, ( 3 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a0, ( 4 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a1, ( 5 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a2, ( 6 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a3, ( 7 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a4, ( 8 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a5, ( 9 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a6, (10 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	a7, (11 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	t3, (12 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	t4, (13 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	t5, (14 * " _SZREG ")(sp)\n"			\
+"	" _REG_L "	t6, (15 * " _SZREG ")(sp)\n"			\
+"	addi	sp, sp, (16 * " _SZREG ")\n"				\
+"	jr	ra\n");
+
+
+#ifdef _KERNEL
+
+#define MCOUNT_ENTER						\
+   s = (csr_sstatus_read() & SR_SIE) != 0;			\
+   csr_sstatus_clear(SR_SIE);	// DISABLE_INTERRUPTS
+
+#define	MCOUNT_EXIT						\
+   if (s)							\
+   	csr_sstatus_set(SR_SIE); // ENABLE_INTERRUPTS
+
+#endif
+
+#endif /* _RISCV_PROFILE_H_ */

package/libc/include/generic-netbsd/riscv/pte.h

@@ -0,0 +1,347 @@
+/* $NetBSD: pte.h,v 1.14.2.2 2025/10/26 12:28:36 martin Exp $ */
+
+/*
+ * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas (of 3am Software Foundry), Maxime Villard, and
+ * Nick Hudson.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RISCV_PTE_H_
+#define	_RISCV_PTE_H_
+
+#ifdef _LP64	/* Sv39 */
+#define	PTE_PPN		__BITS(53, 10)
+#define	PTE_PPN0	__BITS(18, 10)
+#define	PTE_PPN1	__BITS(27, 19)
+#define	PTE_PPN2	__BITS(53, 28)
+typedef uint64_t pt_entry_t;
+typedef uint64_t pd_entry_t;
+#define	atomic_cas_pte	atomic_cas_64
+#else		/* Sv32 */
+#define	PTE_PPN		__BITS(31, 10)
+#define	PTE_PPN0	__BITS(19, 10)
+#define	PTE_PPN1	__BITS(31, 20)
+typedef uint32_t pt_entry_t;
+typedef uint32_t pd_entry_t;
+#define	atomic_cas_pte	atomic_cas_32
+#endif
+
+#define	PTE_PPN_SHIFT	10
+
+#define	NPTEPG		(NBPG / sizeof(pt_entry_t))
+#define	NSEGPG		NPTEPG
+#define	NPDEPG		NPTEPG
+
+
+/* HardWare PTE bits SV39 */
+#define PTE_N		__BIT(63)	// Svnapot
+#define PTE_PBMT	__BITS(62, 61)	// Svpbmt
+#define PTE_reserved0	__BITS(60, 54)	//
+
+/*
+ * Svpbmt (Page Based Memory Types) extension:
+ *
+ * PMA --> adhere to physical memory attributes
+ * NC  --> non-cacheable, idempotent, weakly-ordered
+ * IO  --> non-cacheable, non-idempotent, strongly-ordered
+ */
+#define PTE_PBMT_PMA	__SHIFTIN(0, PTE_PBMT)
+#define PTE_PBMT_NC	__SHIFTIN(1, PTE_PBMT)
+#define PTE_PBMT_IO	__SHIFTIN(2, PTE_PBMT)
+
+/* XTheadMae (Memory Attribute Extensions) */
+#define PTE_XMAE	__BITS(63,59)
+#define PTE_XMAE_SO	__BIT(63)	// Strong Order
+#define PTE_XMAE_C	__BIT(62)	// Cacheable
+#define PTE_XMAE_B	__BIT(61)	// Bufferable
+#define PTE_XMAE_SH	__BIT(60)	// Shareable
+#define PTE_XMAE_T	__BIT(59)	// Trustable
+
+/*
+ * Map to the rough PBMT equivalent:
+ *
+ * PMA (i.e. no specific attribute) -->     C  B  SH
+ * NC                               -->        B  SH
+ * IO                               --> SO        SH
+ */
+#define PTE_XMAE_PMA	(              PTE_XMAE_C | PTE_XMAE_B | PTE_XMAE_SH)
+#define PTE_XMAE_NC	(                           PTE_XMAE_B | PTE_XMAE_SH)
+#define PTE_XMAE_IO	(PTE_XMAE_SO                           | PTE_XMAE_SH)
+
+/* Software PTE bits. */
+#define	PTE_RSW		__BITS(9, 8)
+#define	PTE_WIRED	__BIT(9)
+
+/* Hardware PTE bits. */
+// These are hardware defined bits
+#define	PTE_D		__BIT(7)	// Dirty
+#define	PTE_A		__BIT(6)	// Accessed
+#define	PTE_G		__BIT(5)	// Global
+#define	PTE_U		__BIT(4)	// User
+#define	PTE_X		__BIT(3)	// eXecute
+#define	PTE_W		__BIT(2)	// Write
+#define	PTE_R		__BIT(1)	// Read
+#define	PTE_V		__BIT(0)	// Valid
+
+#define	PTE_HARDWIRED	(PTE_A | PTE_D)
+#define	PTE_USER	(PTE_V | PTE_U)
+#define	PTE_KERN	(PTE_V | PTE_G)
+#define	PTE_RW		(PTE_R | PTE_W)
+#define	PTE_RX		(PTE_R | PTE_X)
+#define	PTE_RWX		(PTE_R | PTE_W | PTE_X)
+
+#define	PTE_ISLEAF_P(pte) (((pte) & PTE_RWX) != 0)
+
+#define	PA_TO_PTE(pa)	(((pa) >> PGSHIFT) << PTE_PPN_SHIFT)
+#define	PTE_TO_PA(pte)	(__SHIFTOUT((pte), PTE_PPN) << PGSHIFT)
+
+#if defined(_KERNEL)
+
+static inline bool
+pte_valid_p(pt_entry_t pte)
+{
+	return (pte & PTE_V) != 0;
+}
+
+static inline bool
+pte_wired_p(pt_entry_t pte)
+{
+	return (pte & PTE_WIRED) != 0;
+}
+
+static inline bool
+pte_modified_p(pt_entry_t pte)
+{
+	return (pte & PTE_D) != 0;
+}
+
+static inline bool
+pte_cached_p(pt_entry_t pte)
+{
+	/* TODO: This seems wrong... */
+	return true;
+}
+
+static inline bool
+pte_deferred_exec_p(pt_entry_t pte)
+{
+	return false;
+}
+
+static inline pt_entry_t
+pte_wire_entry(pt_entry_t pte)
+{
+	return pte | PTE_HARDWIRED | PTE_WIRED;
+}
+
+static inline pt_entry_t
+pte_unwire_entry(pt_entry_t pte)
+{
+	return pte & ~(PTE_HARDWIRED | PTE_WIRED);
+}
+
+static inline paddr_t
+pte_to_paddr(pt_entry_t pte)
+{
+	return PTE_TO_PA(pte);
+}
+
+static inline pt_entry_t
+pte_nv_entry(bool kernel_p)
+{
+	return 0;
+}
+
+static inline pt_entry_t
+pte_prot_nowrite(pt_entry_t pte)
+{
+	return pte & ~PTE_W;
+}
+
+static inline pt_entry_t
+pte_prot_downgrade(pt_entry_t pte, vm_prot_t newprot)
+{
+	if ((newprot & VM_PROT_READ) == 0)
+		pte &= ~PTE_R;
+	if ((newprot & VM_PROT_WRITE) == 0)
+		pte &= ~PTE_W;
+	if ((newprot & VM_PROT_EXECUTE) == 0)
+		pte &= ~PTE_X;
+	return pte;
+}
+
+static inline pt_entry_t
+pte_prot_bits(struct vm_page_md *mdpg, vm_prot_t prot, bool kernel_p)
+{
+	KASSERT(prot & VM_PROT_READ);
+	pt_entry_t pte = PTE_R;
+
+	if (prot & VM_PROT_EXECUTE) {
+		pte |= PTE_X;
+	}
+	if (prot & VM_PROT_WRITE) {
+		pte |= PTE_W;
+	}
+
+	return pte;
+}
+
+static inline pt_entry_t
+pte_flag_bits(struct vm_page_md *mdpg, int flags, bool kernel_p)
+{
+	return 0;
+}
+
+#ifdef _LP64
+pt_entry_t	pte_enter_flags_to_pbmt(int);
+#else
+static inline pt_entry_t
+pte_enter_flags_to_pbmt(int flags)
+{
+	return 0;
+};
+#endif
+
+static inline pt_entry_t
+pte_make_enter(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot,
+    int flags, bool kernel_p)
+{
+	pt_entry_t pte = (pt_entry_t)PA_TO_PTE(pa);
+
+	pte |= kernel_p ? PTE_KERN : PTE_USER;
+	pte |= pte_flag_bits(mdpg, flags, kernel_p);
+	pte |= pte_prot_bits(mdpg, prot, kernel_p);
+	pte |= pte_enter_flags_to_pbmt(flags);
+
+	if (mdpg != NULL) {
+
+		if ((prot & VM_PROT_WRITE) != 0 &&
+		    ((flags & VM_PROT_WRITE) != 0 || VM_PAGEMD_MODIFIED_P(mdpg))) {
+			/*
+			* This is a writable mapping, and the page's mod state
+			* indicates it has already been modified.  No need for
+			* modified emulation.
+			*/
+			pte |= PTE_A | PTE_D;
+		} else if ((flags & VM_PROT_ALL) || VM_PAGEMD_REFERENCED_P(mdpg)) {
+			/*
+			* - The access type indicates that we don't need to do
+			*   referenced emulation.
+			* OR
+			* - The physical page has already been referenced so no need
+			*   to re-do referenced emulation here.
+			*/
+			pte |= PTE_A;
+		}
+	} else {
+		pte |= PTE_A | PTE_D;
+	}
+
+	return pte;
+}
+
+static inline pt_entry_t
+pte_make_kenter_pa(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot,
+    int flags)
+{
+	pt_entry_t pte = (pt_entry_t)PA_TO_PTE(pa);
+
+	pte |= PTE_KERN | PTE_HARDWIRED | PTE_WIRED;
+	pte |= pte_flag_bits(NULL, flags, true);
+	pte |= pte_prot_bits(NULL, prot, true);
+	pte |= pte_enter_flags_to_pbmt(flags);
+
+	return pte;
+}
+
+static inline void
+pte_set(pt_entry_t *ptep, pt_entry_t pte)
+{
+	*ptep = pte;
+}
+
+static inline pd_entry_t
+pte_invalid_pde(void)
+{
+	return 0;
+}
+
+static inline pd_entry_t
+pte_pde_pdetab(paddr_t pa, bool kernel_p)
+{
+	return PTE_V | PA_TO_PTE(pa);
+}
+
+static inline pd_entry_t
+pte_pde_ptpage(paddr_t pa, bool kernel_p)
+{
+	return PTE_V | PA_TO_PTE(pa);
+}
+
+static inline bool
+pte_pde_valid_p(pd_entry_t pde)
+{
+	return (pde & (PTE_X | PTE_W | PTE_R | PTE_V)) == PTE_V;
+}
+
+static inline paddr_t
+pte_pde_to_paddr(pd_entry_t pde)
+{
+	return pte_to_paddr((pt_entry_t)pde);
+}
+
+static inline pd_entry_t
+pte_pde_cas(pd_entry_t *pdep, pd_entry_t opde, pt_entry_t npde)
+{
+#ifdef MULTIPROCESSOR
+#ifdef _LP64
+	return atomic_cas_64(pdep, opde, npde);
+#else
+	return atomic_cas_32(pdep, opde, npde);
+#endif
+#else
+	*pdep = npde;
+	return 0;
+#endif
+}
+
+static inline void
+pte_pde_set(pd_entry_t *pdep, pd_entry_t npde)
+{
+
+	*pdep = npde;
+}
+
+static inline pt_entry_t
+pte_value(pt_entry_t pte)
+{
+	return pte;
+}
+
+#endif /* _KERNEL */
+
+#endif /* _RISCV_PTE_H_ */

package/libc/include/generic-netbsd/riscv/ptrace.h

@@ -0,0 +1,63 @@
+/* $NetBSD: ptrace.h,v 1.6 2024/05/03 07:11:14 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RISCV_PTRACE_H_
+#define _RISCV_PTRACE_H_
+
+/*
+ * RISCV-dependent ptrace definitions.
+ * Note that PT_STEP is _not_ supported.
+ */
+#define PT_GETREGS	(PT_FIRSTMACH + 0)
+#define PT_SETREGS	(PT_FIRSTMACH + 1)
+#define PT_GETFPREGS	(PT_FIRSTMACH + 2)
+#define PT_SETFPREGS	(PT_FIRSTMACH + 3)
+
+#define PT_MACHDEP_STRINGS \
+	"PT_GETREGS", \
+	"PT_SETREGS", \
+	"PT_GETFPREGS", \
+	"PT_SETFPREGS"
+
+#include <machine/reg.h>
+#define PTRACE_REG_PC(r)	(r)->r_pc
+#define PTRACE_REG_FP(r)	(r)->r_reg[_X_S0]
+#define PTRACE_REG_SET_PC(r, v)	(r)->r_pc = (v)
+#define PTRACE_REG_SP(r)	(r)->r_reg[_X_SP]
+#define PTRACE_REG_INTRV(r)	(r)->r_reg[_X_A0]
+
+#define PTRACE_ILLEGAL_ASM	__asm __volatile("c.unimp" ::: "memory")
+
+#define PTRACE_BREAKPOINT	((const uint8_t[]) { 0x02, 0x90 })
+#define PTRACE_BREAKPOINT_ASM	__asm __volatile("c.ebreak" ::: "memory")
+#define PTRACE_BREAKPOINT_SIZE	2
+
+#endif /* _RISCV_PTRACE_H_ */

package/libc/include/generic-netbsd/riscv/reg.h

@@ -0,0 +1,125 @@
+/* $NetBSD: reg.h,v 1.10 2022/12/13 22:25:08 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RISCV_REG_H_
+#define _RISCV_REG_H_
+
+// x0		= 0
+// x1		= ra		(return address)		  Caller
+// x2		= sp		(stack pointer)			  Callee
+// x3		= gp		(global pointer)
+// x4		= tp		(thread pointer)
+// x5 - x7	= t0 - t2	(temporary)			  Caller
+// x8		= s0/fp		(saved register / frame pointer)  Callee
+// x9		= s1		(saved register)		  Callee
+// x10 - x11	= a0 - a1	(arguments/return values)	  Caller
+// x12 - x17	= a2 - a7	(arguments)			  Caller
+// x18 - x27	= s2 - s11	(saved registers)		  Callee
+// x28 - x31	= t3 - t6	(temporaries)			  Caller
+
+struct reg {	// synced with register_t in <riscv/types.h>
+#ifdef _LP64
+	__uint64_t r_reg[31]; /* x0 is always 0 */
+	__uint64_t r_pc;
+#else
+	__uint32_t r_reg[31]; /* x0 is always 0 */
+	__uint32_t r_pc;
+#endif
+};
+
+#ifdef _LP64
+struct reg32 {	// synced with register_t in <riscv/types.h>
+	__uint32_t r_reg[31]; /* x0 is always 0 */
+	__uint32_t r_pc;
+};
+#endif
+
+#define _XREG(n)	((n) - 1)
+#define _X_RA		_XREG(1)
+#define _X_SP		_XREG(2)
+#define _X_GP		_XREG(3)
+#define _X_TP		_XREG(4)
+#define _X_T0		_XREG(5)
+#define _X_T1		_XREG(6)
+#define _X_T2		_XREG(7)
+#define _X_S0		_XREG(8)
+#define _X_S1		_XREG(9)
+#define _X_A0		_XREG(10)
+#define _X_A1		_XREG(11)
+#define _X_A2		_XREG(12)
+#define _X_A3		_XREG(13)
+#define _X_A4		_XREG(14)
+#define _X_A5		_XREG(15)
+#define _X_A6		_XREG(16)
+#define _X_A7		_XREG(17)
+#define _X_S2		_XREG(18)
+#define _X_S3		_XREG(19)
+#define _X_S4		_XREG(20)
+#define _X_S5		_XREG(21)
+#define _X_S6		_XREG(22)
+#define _X_S7		_XREG(23)
+#define _X_S8		_XREG(24)
+#define _X_S9		_XREG(25)
+#define _X_S10		_XREG(26)
+#define _X_S11		_XREG(27)
+#define _X_T3		_XREG(28)
+#define _X_T4		_XREG(29)
+#define _X_T5		_XREG(30)
+#define _X_T6		_XREG(31)
+
+// f0 - f7	= ft0 - ft7	(FP temporaries)		  Caller
+// following layout is similar to integer registers above
+// f8 - f9	= fs0 - fs1	(FP saved registers)		  Callee
+// f10 - f11	= fa0 - fa1	(FP arguments/return values)	  Caller
+// f12 - f17	= fa2 - fa7	(FP arguments)			  Caller
+// f18 - f27	= fs2 - fa11	(FP saved registers)		  Callee
+// f28 - f31	= ft8 - ft11	(FP temporaries)		  Caller
+
+/*
+ * This fragment is common to <riscv/mcontext.h> and <riscv/reg.h>
+ */
+#ifndef _BSD_FPREG_T_
+union __fpreg {
+	__uint64_t u_u64;
+	double u_d;
+};
+#define _BSD_FPREG_T_	union __fpreg
+#endif
+
+/*
+ * 32 double precision floating point, 1 CSR
+ */
+struct fpreg {
+	_BSD_FPREG_T_	r_fpreg[33];
+};
+#define r_fcsr		r_fpreg[32].u_u64
+
+#endif /* _RISCV_REG_H_ */

package/libc/include/generic-netbsd/riscv/rwlock.h

@@ -0,0 +1 @@
+/*	$NetBSD: rwlock.h,v 1.2 2019/11/29 20:04:53 riastradh Exp $	*/