@zigc/lib 0.17.0-dev.607 → 0.17.0-dev.644

package/libc/include/m68k-netbsd-none/m68k/intr.h

@@ -0,0 +1,211 @@
+/*	$NetBSD: intr.h,v 1.9 2024/02/08 20:11:56 andvar Exp $	*/
+
+/*-
+ * Copyright (c) 2023, 2024 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */     
+
+#ifndef _M68k_INTR_H_
+#define	_M68k_INTR_H_
+
+#include <machine/psl.h>
+
+#if (defined(_KERNEL) && !defined(_LOCORE)) || defined(_KMEMUSER)
+typedef struct {
+	uint16_t _psl;		/* physical manifestation of logical IPL_* */
+} ipl_cookie_t;
+#endif
+
+#ifdef _KERNEL
+
+/*
+ * Logical interrupt priority levels -- these are distinct from
+ * the hardware interrupt priority levels of the m68k.
+ */
+#define	IPL_NONE	0
+#define	IPL_SOFTCLOCK	1	/* clock software interrupts */
+#define	IPL_SOFTBIO	2	/* block device software interrupts */
+#define	IPL_SOFTNET	3	/* network software interrupts */
+#define	IPL_SOFTSERIAL	4	/* serial device software interrupts */
+#define	IPL_VM		5	/* all interrupts that can allocate memory */
+#define	IPL_SCHED	6	/* scheduler / hard clock interrupts */
+#define	IPL_HIGH	7	/* blocks all interrupts */
+#define	NIPL		8
+
+/*
+ * Abstract ISR priorities.  These allow sorting of latency-sensitive
+ * devices earlier on the shared auto-vectored interrupt lists.
+ */
+#define	ISRPRI_BIO		0	/* a block I/O device */
+#define	ISRPRI_MISC		0	/* misc. devices */
+#define	ISRPRI_NET		1	/* a network interface */
+#define	ISRPRI_TTY		2	/* a serial port */
+#define	ISRPRI_DISPLAY		2	/* display devices / framebuffers */
+#define	ISRPRI_TTYNOBUF		3	/* a particularly bad serial port */
+#define	ISRPRI_AUDIO		4	/* audio devices */
+
+#ifndef _LOCORE
+
+extern volatile unsigned int intr_depth;/* interrupt depth */
+extern const uint16_t ipl2psl_table[NIPL];
+
+typedef int ipl_t;		/* logical IPL_* value */
+
+static inline bool
+cpu_intr_p(void)
+{
+	return intr_depth != 0;
+}
+
+static inline ipl_cookie_t
+makeiplcookie(ipl_t ipl)
+{
+	return (ipl_cookie_t){._psl = ipl2psl_table[ipl]};
+}
+
+static inline int
+splraiseipl(ipl_cookie_t icookie)
+{
+	return _splraise(icookie._psl);
+}
+
+/*
+ * These are essentially constant equivalents of what's in
+ * ipl2psl_table[] to avoid the memory reference.
+ */
+#define	splsoftclock()	_splraise(PSL_S | MACHINE_PSL_IPL_SOFTCLOCK)
+#define	splsoftbio()	_splraise(PSL_S | MACHINE_PSL_IPL_SOFTBIO)
+#define	splsoftnet()	_splraise(PSL_S | MACHINE_PSL_IPL_SOFTNET)
+#define	splsoftserial()	_splraise(PSL_S | MACHINE_PSL_IPL_SOFTSERIAL)
+#define	splvm()		_splraise(PSL_S | MACHINE_PSL_IPL_VM)
+#define	splsched()	_splraise(PSL_S | MACHINE_PSL_IPL_SCHED)
+#define	splhigh()	spl7()
+
+/*
+ * XXX TODO: Support for hardware-assisted soft interrupts (sun68k)
+ * XXX and fast-soft-interrupts (others).
+ */
+#define	spl0()		_spl0()
+#define	splx(s)		_splx(s)
+
+#ifdef _M68K_INTR_PRIVATE
+#include <sys/queue.h>
+
+struct m68k_intrhand {
+	LIST_ENTRY(m68k_intrhand)	ih_link;
+	int				(*ih_func)(void *);
+	void				*ih_arg;
+	struct evcnt			*ih_evcnt;
+	int				ih_ipl;	/* m68k IPL, not IPL_* */
+	int				ih_vec;
+	int				ih_isrpri;
+};
+LIST_HEAD(m68k_intrhand_list, m68k_intrhand);
+
+struct m68k_ih_allocfuncs {
+	struct m68k_intrhand *	(*alloc)(int km_flag);
+	void			(*free)(struct m68k_intrhand *);
+};
+#else
+struct m68k_ih_allocfuncs;
+#endif /* _M68K_INTR_PRIVATE */
+
+#include <sys/evcnt.h>
+
+#ifdef __HAVE_LEGACY_INTRCNT
+#define	m68k_count_intr(x)						\
+do {									\
+	extern u_int intrcnt[];						\
+	intrcnt[(x)]++;							\
+	curcpu()->ci_data.cpu_nintr++;					\
+} while (/*CONSTCOND*/0)
+#else
+/*
+ * This is exposed here so that platform-specific interrupt handlers
+ * can access it.
+ */
+extern struct evcnt m68k_intr_evcnt[];
+
+#define	m68k_count_intr(x)						\
+do {									\
+	/* 32-bit counter should be sufficient for m68k. */		\
+	m68k_intr_evcnt[(x)].ev_count32++;				\
+	curcpu()->ci_data.cpu_nintr++;					\
+} while (/*CONSTCOND*/0)
+#endif /* __HAVE_LEGACY_INTRCNT */
+
+/*
+ * Common m68k interrupt dispatch:
+ *
+ * ==> m68k_intr_init(const struct m68k_ih_allocfuncs *allocfuncs)
+ *
+ * Initialize the interrupt system.  If the platform needs to store
+ * additional information in the interrupt handle, then it can provide
+ * its own alloc/free routines.  Otherwise, pass NULL to get the default.
+ * If a platform doesn't want the special allocator behavior, calling
+ * this function is optional; it will be done for you on the first call
+ * to m68k_intr_establish().
+ *
+ * ==> m68k_intr_establish(int (*func)(void *), void *arg,
+ *         struct evcnt *ev, int vec, int ipl, int flags)
+ *
+ * Establish an interrupt handler.  If vec is 0, then the handler is
+ * registered in the auto-vector list corresponding to the specified
+ * m68k interrupt priroity level (this is NOT an IPL_* value).  Otherwise.
+ * the handler is registered at the specified vector.
+ *
+ * Vectored interrupts are not shareable.  The interrupt vector must be
+ * within the platform's "user vector" region, which is generally defined
+ * as vectors 64-255, although some platforms may use vectors that start
+ * below 64 (in which case, that platform must define MACHINE_USERVEC_START
+ * to override the default).
+ *
+ * Vectored interrupt support is not included by default in order to reduce
+ * the memory footprint.  If a platform wishes to enable vectored interrupts,
+ * then it should define __HAVE_M68K_INTR_VECTORED in its <machine/types.h>
+ * and genassym.cf.
+ *
+ * ==> m68k_intr_disestablish(void *ih)
+ *
+ * Removes a previously-established interrupt handler.  Returns true
+ * if there are no more handlers on the list that handler was on.  This
+ * information can be used to e.g. disable interrupts on a PIC.
+ */
+void	m68k_intr_init(const struct m68k_ih_allocfuncs *);
+void	*m68k_intr_establish(int (*)(void *), void *, struct evcnt *,
+	    int/*vec*/, int/*m68k ipl*/, int/*isrpri*/, int/*flags*/);
+bool	m68k_intr_disestablish(void *);
+
+#ifdef __HAVE_M68K_INTR_VECTORED
+void	*m68k_intrvec_intrhand(int vec);	/* XXX */
+#endif
+
+#endif /* !_LOCORE */
+
+#endif /* _KERNEL */
+
+#endif /* _M68k_INTR_H_ */

package/libc/include/m68k-netbsd-none/m68k/kcore.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: kcore.h,v 1.5 2008/04/28 20:23:26 martin Exp $	*/
+/*	$NetBSD: kcore.h,v 1.7 2023/01/29 09:24:33 mlelstv Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
@@ -57,24 +57,24 @@
 #define	M68K_NPHYS_RAM_SEGS	8	/* XXX */
 struct m68k_kcore_hdr {
 	int32_t		mmutype;	/* MMU type */
-	u_int32_t	sg_v;		/* STE bits */
-	u_int32_t	sg_frame;
-	u_int32_t	sg_ishift;
-	u_int32_t	sg_pmask;
-	u_int32_t	sg40_shift1;
-	u_int32_t	sg40_mask2;
-	u_int32_t	sg40_shift2;
-	u_int32_t	sg40_mask3;
-	u_int32_t	sg40_shift3;
-	u_int32_t	sg40_addr1;
-	u_int32_t	sg40_addr2;
-	u_int32_t	pg_v;		/* PTE bits */
-	u_int32_t	pg_frame;
-	u_int32_t	sysseg_pa;	/* PA of Sysseg[] */
-	u_int32_t	reloc;		/* value added to relocate a symbol
+	uint32_t	sg_v;		/* STE bits */
+	uint32_t	sg_frame;
+	uint32_t	sg_ishift;
+	uint32_t	sg_pmask;
+	uint32_t	sg40_shift1;
+	uint32_t	sg40_mask2;
+	uint32_t	sg40_shift2;
+	uint32_t	sg40_mask3;
+	uint32_t	sg40_shift3;
+	uint32_t	sg40_addr1;
+	uint32_t	sg40_addr2;
+	uint32_t	pg_v;		/* PTE bits */
+	uint32_t	pg_frame;
+	uint32_t	sysseg_pa;	/* PA of Sysseg[] */
+	uint32_t	reloc;		/* value added to relocate a symbol
 					   before address translation is
 					   enabled */
-	u_int32_t	relocend;	/* if kernbase < va < relocend, we
+	uint32_t	relocend;	/* if kernbase < va < relocend, we
 					   can do simple relocation to get
 					   the physical address */
 	phys_ram_seg_t	ram_segs[M68K_NPHYS_RAM_SEGS];
@@ -84,20 +84,20 @@ struct m68k_kcore_hdr {
  * kcore information for the sun2
  */
 struct sun2_kcore_hdr {
-	u_int32_t	segshift;
-	u_int32_t	pg_frame;	/* PTE bits */
-	u_int32_t	pg_valid;
-	u_int8_t	ksegmap[512];	/* kernel segment map */
+	uint32_t	segshift;
+	uint32_t	pg_frame;	/* PTE bits */
+	uint32_t	pg_valid;
+	uint8_t		ksegmap[512];	/* kernel segment map */
 };
 
 /*
  * kcore information for the sun3
  */
 struct sun3_kcore_hdr {
-	u_int32_t	segshift;
-	u_int32_t	pg_frame;	/* PTE bits */
-	u_int32_t	pg_valid;
-	u_int8_t	ksegmap[256];	/* kernel segment map */
+	uint32_t	segshift;
+	uint32_t	pg_frame;	/* PTE bits */
+	uint32_t	pg_valid;
+	uint8_t		ksegmap[256];	/* kernel segment map */
 };
 
 /*
@@ -106,10 +106,10 @@ struct sun3_kcore_hdr {
  */
 #define	SUN3X_NPHYS_RAM_SEGS	4
 struct sun3x_kcore_hdr {
-	u_int32_t	pg_frame;	/* PTE bits */
-	u_int32_t	pg_valid;
-	u_int32_t	contig_end;
-	u_int32_t	kernCbase;	/* VA of kernel level C page table */
+	uint32_t	pg_frame;	/* PTE bits */
+	uint32_t	pg_valid;
+	uint32_t	contig_end;
+	uint32_t	kernCbase;	/* VA of kernel level C page table */
 	phys_ram_seg_t	ram_segs[SUN3X_NPHYS_RAM_SEGS];
 };
 
@@ -118,8 +118,8 @@ struct sun3x_kcore_hdr {
  */
 struct cpu_kcore_hdr {
 	char		name[16];	/* machine name */
-	u_int32_t	page_size;	/* hardware page size */
-	u_int32_t	kernbase;	/* start of KVA space */
+	uint32_t	page_size;	/* hardware page size */
+	uint32_t	kernbase;	/* start of KVA space */
 	union {
 		struct m68k_kcore_hdr _m68k;
 		struct sun2_kcore_hdr _sun2;

package/libc/include/m68k-netbsd-none/m68k/lwp_private.h

@@ -0,0 +1,64 @@
+/*	$NetBSD: lwp_private.h,v 1.2 2024/12/01 08:44:43 skrll Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Klaus Klein.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _M68K_LWP_PRIVATE_H_
+#define _M68K_LWP_PRIVATE_H_
+
+#include <sys/cdefs.h>
+#include <sys/tls.h>
+
+#include <lwp.h>
+
+#define	TLS_TP_OFFSET	0x7000
+#define	TLS_DTV_OFFSET	0x8000
+
+__CTASSERT(TLS_TP_OFFSET + sizeof(struct tls_tcb) < 0x8000);
+__CTASSERT(TLS_TP_OFFSET % sizeof(struct tls_tcb) == 0);
+
+__BEGIN_DECLS
+
+static __inline struct tls_tcb *
+__lwp_gettcb_fast(void)
+{
+	unsigned int __tcb = (unsigned int)_lwp_getprivate();
+	return (struct tls_tcb *)(uintptr_t)
+	    (__tcb - TLS_TP_OFFSET - sizeof(struct tls_tcb));
+}
+
+static inline void
+__lwp_settcb(struct tls_tcb *__tcb)
+{
+	__tcb += TLS_TP_OFFSET / sizeof(*__tcb) + 1;
+	_lwp_setprivate(__tcb);
+}
+__END_DECLS
+
+#endif	/* !_M68K_LWP_PRIVATE_H_ */

package/libc/include/m68k-netbsd-none/m68k/m68k.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: m68k.h,v 1.24 2019/04/06 03:06:26 thorpej Exp $	*/
+/*	$NetBSD: m68k.h,v 1.27 2024/01/13 00:44:42 thorpej Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -58,7 +58,7 @@
  * All m68k ports must provide these globals.
  */
 extern	int cputype;		/* CPU on this host */
-extern	int ectype; 		/* external cache on this host */
+extern	int ectype;		/* external cache on this host */
 extern	int fputype;		/* FPU on this host */
 extern	int mmutype;		/* MMU on this host */
 #endif	/* _KERNEL */
@@ -103,14 +103,10 @@ void	copypage040(void *fromaddr, void *toaddr);
 void	copypage(void *fromaddr, void *toaddr);
 void	zeropage(void *addr);
 
-/* support.s */
-int 	getdfc(void);
-int 	getsfc(void);
-
 /* switch_subr.s */
 void	lwp_trampoline(void);
 void	m68881_save(struct fpframe *);
-void	m68881_restore(struct fpframe *); 
+void	m68881_restore(struct fpframe *);
 void	savectx(struct pcb *);
 
 /* w16copy.s */

package/libc/include/m68k-netbsd-none/m68k/mcontext.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: mcontext.h,v 1.12 2020/10/04 10:34:18 rin Exp $	*/
+/*	$NetBSD: mcontext.h,v 1.16 2024/11/30 01:04:11 christos Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -39,8 +39,8 @@
 /*
  * mcontext extensions to handle signal delivery.
  */
-#define _UC_SETSTACK	0x00010000
-#define _UC_CLRSTACK	0x00020000
+#define	_UC_SETSTACK	_UC_MD_BIT16
+#define	_UC_CLRSTACK	_UC_MD_BIT17
 
 /*
  * General register state
@@ -98,8 +98,8 @@ typedef struct {
 /* Note: no additional padding is to be performed in ucontext_t. */
 
 /* Machine-specific uc_flags value */
-#define _UC_M68K_UC_USER 0x40000000
-#define	_UC_TLSBASE	0x00080000
+#define	_UC_M68K_UC_USER _UC_MD_BIT30
+#define	_UC_TLSBASE	_UC_MD_BIT19
 
 #define _UC_MACHINE_SP(uc)	((uc)->uc_mcontext.__gregs[_REG_A7])
 #define _UC_MACHINE_FP(uc)	((uc)->uc_mcontext.__gregs[_REG_A6])
@@ -110,35 +110,4 @@ typedef struct {
 
 #define	__UCONTEXT_SIZE	1024
 
-#if defined(_LIBC_SOURCE) || defined(_RTLD_SOURCE) || defined(__LIBPTHREAD_SOURCE__)
-#define	TLS_TP_OFFSET	0x7000
-#define	TLS_DTV_OFFSET	0x8000
-
-#include <sys/tls.h>
-
-__CTASSERT(TLS_TP_OFFSET + sizeof(struct tls_tcb) < 0x8000);
-__CTASSERT(TLS_TP_OFFSET % sizeof(struct tls_tcb) == 0);
-
-__BEGIN_DECLS
-
-void *_lwp_getprivate(void);
-void _lwp_setprivate(void *);
-
-static __inline struct tls_tcb *
-__lwp_gettcb_fast(void)
-{
-	unsigned int __tcb = (unsigned int)_lwp_getprivate();
-	return (struct tls_tcb *)(uintptr_t)
-	    (__tcb - TLS_TP_OFFSET - sizeof(struct tls_tcb));
-}
-
-static inline void
-__lwp_settcb(struct tls_tcb *__tcb)
-{
-	__tcb += TLS_TP_OFFSET / sizeof(*__tcb) + 1;
-	_lwp_setprivate(__tcb);
-}
-__END_DECLS
-#endif
-
 #endif	/* !_M68K_MCONTEXT_H_ */

package/libc/include/m68k-netbsd-none/m68k/mmu_30.h

@@ -0,0 +1,105 @@
+/*	$NetBSD: mmu_30.h,v 1.3 2025/07/08 11:45:25 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 2023 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _M68K_MMU_30_H_
+#define	_M68K_MMU_30_H_
+
+#include <machine/fcode.h>
+
+/*
+ * The built-in MMU in the 68030 is a subset of the 68851.  Section 9.6
+ * of the 68030 User's Manual describes the differences:
+ *
+ * The following 68851 functions are not present on the 68030:
+ * - Access levels
+ * - Breakpoint registers
+ * - DMA Root Pointer
+ * - Task aliases
+ * - Lockable ATC entries
+ * - ATC entries defined as Shared Globally
+ *
+ * Furthermore, the 68030 has some functional differences:
+ * - Only 22 ATC entries
+ * - Reduced instruction set for MMU operations
+ * - Reduced addressing modes for MMU instructions.
+ *
+ * Instructions removed: PVALID, PFLUSHR, PFLUSHS, PBcc, PDBcc, PScc,
+ * PTRAPcc, PSAVE, PRESTORE.
+ *
+ * Registers removed: CAL, VAL, BAD, BACx, DRP, AC.
+ *
+ * The 68030 does, however, add a pair of Transparent Translation
+ * registers
+ */
+
+/*
+ * 9.7.3 -- Transparent Translation registers
+ *
+ * These registers define blocks of logical address space that are
+ * transparently translated VA==PA.  The minimum block size is 16MB,
+ * and the blocks may overlap.  The mode in which the transparent
+ * translation is applied is specified by the Function Code base and
+ * mask fields.
+ *
+ * The Logical Address Base specifies the address of the block and
+ * the Logical Address Mask field specifies the address bits to *ignore*.
+ *
+ */
+#define	TT30_LAB	__BITS(31,24)	/* Logical Address Base */
+#define	TT30_LAM	__BITS(16,23)	/* Logical Address Mask */
+#define	TT30_E		__BIT(15)	/* Enable transparent translation */
+#define	TT30_CI		__BIT(10)	/* Cache Inhibit */
+#define	TT30_RW		__BIT(9)	/* Read(1) or Write(0) translated */
+#define	TT30_RWM	__BIT(8)	/* RW field used(0) or ignored(1) */
+#define	TT30_FCBASE	__BITS(4,6)	/* Function Code base */
+#define	TT30_FCMASK	__BITS(0,2)	/* Function Code bits to ignore */
+
+/* Convenience definitions for address space selection. */
+#define	TT30_USERD	__SHIFTIN(FC_USERD,TT30_FCBASE)
+#define	TT30_USERP	__SHIFTIN(FC_USERP,TT30_FCBASE)
+#define	TT30_SUPERD	__SHIFTIN(FC_SUPERD,TT30_FCBASE)
+#define	TT30_SUPERP	__SHIFTIN(FC_SUPERP,TT30_FCBASE)
+
+#ifdef _KERNEL
+/*
+ * TT register value indices in the mmu_ttregs[] array.  Note that asm
+ * code makes assumptions about these indices, to change them at your
+ * peril.
+ */
+extern uint32_t mmu_tt30[];
+#define	MMU_TTREG_TT0	0
+#define	MMU_TTREG_TT1	1
+#define	MMU_NTTREGS30	2
+
+void	mmu_load_tt30(uint32_t *);
+#endif /* _KERNEL */
+
+#endif /* _M68K_MMU_30_H_ */