@woosh/meep-engine 3.16.0 → 3.17.0

package/src/shade/renderer/particles/vm/ParticleVMReference.js

@@ -3,9 +3,24 @@ import {
     PARTICLE_VM_MAX_INSTRUCTIONS,
 } from "../ParticleConstants.js";
 import {
+    VM_DEST,
+    VM_DST_MASK,
+    VM_DST_SHIFT,
+    VM_ISA,
+    VM_KIND,
+    VM_KIND_BITS,
+    VM_KIND_MASK,
+    VM_KIND_SHIFT,
+    VM_MAX_WIDTH,
     VM_OP,
-    vm_decode_op,
-    vm_decode_width,
+    VM_OP_MASK,
+    VM_OPERAND_BASE_MASK,
+    VM_OPERAND_SWIZZLE_SHIFT,
+    VM_SWIZZLE_IDENTITY,
+    VM_WIDTH,
+    VM_WIDTH_MASK,
+    VM_WIDTH_SHIFT,
+    vm_dest_width,
     vm_operation_width,
 } from "../isa/ParticleVMISA.js";
 
@@ -38,6 +53,73 @@ export function u32_to_unit_f32(u) {
     return (u >>> 8) * (1 / 16777216);
 }
 
+// --- the opcode rules as dense tables ------------------------------------------------------------
+//
+// The editor's preview runs this executor for every live particle every frame, so its speed is that
+// preview's frame rate, and a few thousand instructions a particle leave no room for a map lookup an
+// instruction. Everything the loop needs to know about an opcode is read out of the ISA once, here,
+// into arrays indexed by opcode number; the ISA stays the one place the rules are written.
+
+/** One past the largest opcode number. @type {number} */
+const OP_COUNT = VM_OP_MASK + 1;
+
+/** `1` where the opcode is defined. @type {Uint8Array} */
+const OP_DEFINED = new Uint8Array(OP_COUNT);
+
+/** The lane count the opcode always operates on, or `-1` where the instruction's width field says. @type {Int8Array} */
+const OP_WIDTH = new Int8Array(OP_COUNT);
+
+/** The lanes the opcode always writes, or `-1` for as many as it operates on. @type {Int8Array} */
+const OP_DEST = new Int8Array(OP_COUNT);
+
+/** Bit `n` set where source slot `n` is read one lane whatever the width. @type {Uint8Array} */
+const OP_SCALAR = new Uint8Array(OP_COUNT);
+
+for (const [op, meta] of VM_ISA) {
+    OP_DEFINED[op] = 1;
+    OP_WIDTH[op] = meta.width === VM_WIDTH.VARIABLE ? -1 : vm_operation_width(op, 0);
+    OP_DEST[op] = meta.dest === VM_DEST.WIDTH ? -1 : vm_dest_width(op, 0);
+
+    for (const slot of meta.scalar_operands) {
+        OP_SCALAR[op] |= 1 << slot;
+    }
+}
+
+// --- module-local copies of what the loop reads per instruction ----------------------------------
+//
+// An imported binding is a live lookup on every read under some module loaders (vitest's among
+// them), and the loop below reads a dozen of them per instruction. Copied once here, they are plain
+// constants to the JIT, and the opcode switch can be a jump table.
+
+const {
+    ABS, ACOS, ADD, ASIN, ATAN2, CLAMP, CMP_EQ, CMP_GE, CMP_GT, CMP_LE, CMP_LT, COS, CROSS, CURVE,
+    DISTANCE, DIV, DOT, EXP, FLOOR, FRACT, HALT, KILL, LENGTH, LOAD_ATTR, LOAD_BUILTIN, LOAD_CONST,
+    LOG, MAD, MAX, MIN, MIX, MOV, MUL, NEG, NOP, NORMALIZE, POW, RANDOM, RSQRT, SELECT, SIN,
+    SMOOTHSTEP, SQRT, STEP, STORE_ATTR, SUB, TAN,
+} = VM_OP;
+const KIND_REG = VM_KIND.REG;
+const KIND_IMM = VM_KIND.IMM;
+const OPCODE_MASK = VM_OP_MASK;
+const WIDTH_SHIFT = VM_WIDTH_SHIFT;
+const WIDTH_MASK = VM_WIDTH_MASK;
+const DST_SHIFT = VM_DST_SHIFT;
+const DST_MASK = VM_DST_MASK;
+const KIND_SHIFT = VM_KIND_SHIFT;
+const KIND_BITS = VM_KIND_BITS;
+const KIND_MASK = VM_KIND_MASK;
+const OPERAND_BASE_MASK = VM_OPERAND_BASE_MASK;
+const OPERAND_SWIZZLE_SHIFT = VM_OPERAND_SWIZZLE_SHIFT;
+const SWIZZLE_IDENTITY = VM_SWIZZLE_IDENTITY;
+const INSTRUCTION_WORDS = PARTICLE_VM_INSTRUCTION_WORDS;
+const MAX_INSTRUCTIONS = PARTICLE_VM_MAX_INSTRUCTIONS;
+const MAX_WIDTH = VM_MAX_WIDTH;
+
+/** Scratch for reading a literal's bits as the `f32` they are. */
+const LITERAL_F32 = new Float32Array(1);
+
+/** @type {Uint32Array} the same four bytes */
+const LITERAL_U32 = new Uint32Array(LITERAL_F32.buffer);
+
 /**
  * Execute one section of a particle program against a single particle record.
  *
@@ -45,7 +127,10 @@ export function u32_to_unit_f32(u) {
  * particle asked to be destroyed and the advanced RNG state so the caller can persist it.
  *
  * This is the CPU reference semantics — the WGSL interpreter is written to match it exactly, and the
- * parity spec cross-checks them.
+ * parity spec cross-checks them. The shape is the interpreter's: every source is resolved, lane by
+ * lane as far as the opcode reads it, before the opcode runs, and the destination is written after,
+ * so a source may overlap the destination in any way and still mean what it held before the
+ * instruction.
  *
  * @param {object} params
  * @param {Uint32Array} params.words instruction words for the section (SPAWN or UPDATE)
@@ -81,228 +166,264 @@ export function execute_particle_vm({
         return u32_to_unit_f32(r.value);
     };
 
-    const instruction_count = Math.min(words.length / PARTICLE_VM_INSTRUCTION_WORDS, PARTICLE_VM_MAX_INSTRUCTIONS);
+    // The three resolved sources and the result, one f32 per lane. Only the lanes an opcode reads
+    // are resolved and only the lanes it writes are stored, so nothing here is ever cleared.
+    const a = new Float32Array(MAX_WIDTH);
+    const b = new Float32Array(MAX_WIDTH);
+    const c = new Float32Array(MAX_WIDTH);
+    const d = new Float32Array(MAX_WIDTH);
+
+    /**
+     * Resolve a source by the kind its word carries: a register run read through its swizzle, or
+     * the one `f32` a literal is in every lane. The only place the kinds are read; every opcode
+     * below sees a value, so no opcode has a tagged mode of its own.
+     *
+     * @param {Float32Array} into
+     * @param {number} kind
+     * @param {number} word
+     * @param {number} lanes
+     */
+    const gather = (into, kind, word, lanes) => {
+        if (kind === KIND_REG) {
+            const base = word & OPERAND_BASE_MASK;
+            const pattern = ((word >>> OPERAND_SWIZZLE_SHIFT) & 0xff) ^ SWIZZLE_IDENTITY;
+
+            for (let i = 0; i < lanes; i++) {
+                into[i] = reg[base + ((pattern >>> (2 * i)) & 3)];
+            }
+        } else if (kind === KIND_IMM) {
+            LITERAL_U32[0] = word;
+            const value = LITERAL_F32[0];
+
+            for (let i = 0; i < lanes; i++) {
+                into[i] = value;
+            }
+        }
+    };
+
+    const instruction_count = Math.min(words.length / INSTRUCTION_WORDS, MAX_INSTRUCTIONS);
 
     for (let pc = 0; pc < instruction_count; pc++) {
-        const base = pc * PARTICLE_VM_INSTRUCTION_WORDS;
+        const base = pc * INSTRUCTION_WORDS;
         const word0 = words[base];
-        const op = vm_decode_op(word0);
-        const dst = words[base + 1];
-        const s0 = words[base + 2];
-        const s1 = words[base + 3];
-        const s2 = words[base + 4];
+        const op = word0 & OPCODE_MASK;
+
+        if (OP_DEFINED[op] === 0) {
+            throw new Error(`ParticleVMReference: unhandled opcode ${op} at pc ${pc}`);
+        }
 
         /** Lanes this instruction spans. Fixed-width opcodes ignore the encoded field. */
-        const w = vm_operation_width(op, vm_decode_width(word0));
+        const fixed_width = OP_WIDTH[op];
+        const w = fixed_width < 0 ? (word0 >>> WIDTH_SHIFT) & WIDTH_MASK : fixed_width;
+        const dst = (word0 >>> DST_SHIFT) & DST_MASK;
+        const kinds = word0 >>> KIND_SHIFT;
+        const scalar = OP_SCALAR[op];
+        const s0 = words[base + 1];
+        const s1 = words[base + 2];
+        const s2 = words[base + 3];
 
-        // Register operands are slot indices; lane `i` of an operand is slot `base + i`.
-        const d = dst;
-        const a = s0;
-        const b = s1;
-        const c = s2;
+        gather(a, kinds & KIND_MASK, s0, (scalar & 1) !== 0 ? 1 : w);
+        gather(b, (kinds >>> KIND_BITS) & KIND_MASK, s1, (scalar & 2) !== 0 ? 1 : w);
+        gather(c, (kinds >>> (2 * KIND_BITS)) & KIND_MASK, s2, (scalar & 4) !== 0 ? 1 : w);
 
         switch (op) {
-            case VM_OP.HALT:
+            case HALT:
                 return { killed, rng_state: state };
-            case VM_OP.NOP:
+            case NOP:
                 break;
 
-            case VM_OP.MOV:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i];
+            case MOV:
+                for (let i = 0; i < w; i++) d[i] = a[i];
                 break;
 
-            case VM_OP.LOAD_CONST: {
-                // The pool is addressed by word, so the operand is where the value starts, not
-                // which vec4 slot holds it.
-                for (let i = 0; i < w; i++) reg[d + i] = constants[s0 + i];
+            case LOAD_CONST:
+                // The pool is addressed by word, so the operand is where the value starts.
+                for (let i = 0; i < w; i++) d[i] = constants[s0 + i];
                 break;
-            }
 
-            case VM_OP.LOAD_ATTR: {
+            case LOAD_ATTR:
                 // Lanes past the attribute's component count read zero — a one-component attribute
                 // asked for at width 3 is (x, 0, 0), which is what widening it costs: nothing.
-                const off = s0; const comp = s1;
-                for (let i = 0; i < w; i++) reg[d + i] = i < comp ? record_f32[off + i] : 0;
+                for (let i = 0; i < w; i++) d[i] = i < s1 ? record_f32[s0 + i] : 0;
                 break;
-            }
 
-            case VM_OP.STORE_ATTR: {
-                const off = s0; const comp = s1; const src = dst;
-                for (let i = 0; i < comp; i++) record_f32[off + i] = reg[src + i];
+            case STORE_ATTR:
+                for (let i = 0; i < s2; i++) record_f32[s1 + i] = a[i];
                 break;
-            }
 
-            case VM_OP.LOAD_BUILTIN: {
+            case LOAD_BUILTIN: {
                 const v = builtins[s0] ?? [0, 0, 0, 0];
-                for (let i = 0; i < w; i++) reg[d + i] = v[i] ?? 0;
+                for (let i = 0; i < w; i++) d[i] = v[i] ?? 0;
                 break;
             }
 
-            case VM_OP.KILL:
-                if (reg[dst] > 0) killed = true;
+            case KILL:
+                if (a[0] > 0) killed = true;
                 break;
 
-            case VM_OP.ADD:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] + reg[b + i];
-                break;
-            case VM_OP.SUB:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] - reg[b + i];
+            case ADD:
+                for (let i = 0; i < w; i++) d[i] = a[i] + b[i];
                 break;
-            case VM_OP.MUL:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * reg[b + i];
+            case SUB:
+                for (let i = 0; i < w; i++) d[i] = a[i] - b[i];
                 break;
-            case VM_OP.DIV:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] / reg[b + i];
+            case MUL:
+                for (let i = 0; i < w; i++) d[i] = a[i] * b[i];
                 break;
-            case VM_OP.MAD:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * reg[b + i] + reg[c + i];
+            case DIV:
+                for (let i = 0; i < w; i++) d[i] = a[i] / b[i];
                 break;
-            case VM_OP.MIN:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.min(reg[a + i], reg[b + i]);
+            case MAD:
+                for (let i = 0; i < w; i++) d[i] = a[i] * b[i] + c[i];
                 break;
-            case VM_OP.MAX:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.max(reg[a + i], reg[b + i]);
+            case MIN:
+                for (let i = 0; i < w; i++) d[i] = Math.min(a[i], b[i]);
                 break;
-            case VM_OP.MIX:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] + (reg[b + i] - reg[a + i]) * reg[c + i];
+            case MAX:
+                for (let i = 0; i < w; i++) d[i] = Math.max(a[i], b[i]);
                 break;
-            case VM_OP.CLAMP:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.min(Math.max(reg[a + i], reg[b + i]), reg[c + i]);
+            case MIX:
+                for (let i = 0; i < w; i++) d[i] = a[i] + (b[i] - a[i]) * c[i];
                 break;
-            case VM_OP.SCALE: {
-                const scale = reg[b];
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * scale;
+            case CLAMP:
+                for (let i = 0; i < w; i++) d[i] = Math.min(Math.max(a[i], b[i]), c[i]);
                 break;
-            }
 
-            case VM_OP.NEG:
-                for (let i = 0; i < w; i++) reg[d + i] = -reg[a + i];
+            case NEG:
+                for (let i = 0; i < w; i++) d[i] = -a[i];
+                break;
+            case ABS:
+                for (let i = 0; i < w; i++) d[i] = Math.abs(a[i]);
                 break;
-            case VM_OP.ABS:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.abs(reg[a + i]);
+            case FLOOR:
+                for (let i = 0; i < w; i++) d[i] = Math.floor(a[i]);
                 break;
-            case VM_OP.FLOOR:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.floor(reg[a + i]);
+            case FRACT:
+                for (let i = 0; i < w; i++) d[i] = a[i] - Math.floor(a[i]);
                 break;
-            case VM_OP.FRACT:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] - Math.floor(reg[a + i]);
+            case SQRT:
+                for (let i = 0; i < w; i++) d[i] = Math.sqrt(a[i]);
                 break;
-            case VM_OP.SQRT:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.sqrt(reg[a + i]);
+            case SIN:
+                for (let i = 0; i < w; i++) d[i] = Math.sin(a[i]);
                 break;
-            case VM_OP.SIN:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.sin(reg[a + i]);
+            case COS:
+                for (let i = 0; i < w; i++) d[i] = Math.cos(a[i]);
                 break;
-            case VM_OP.COS:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.cos(reg[a + i]);
+            case EXP:
+                for (let i = 0; i < w; i++) d[i] = Math.exp(a[i]);
                 break;
-            case VM_OP.EXP:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.exp(reg[a + i]);
+            case LOG:
+                for (let i = 0; i < w; i++) d[i] = Math.log(a[i]);
                 break;
-            case VM_OP.LOG:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.log(reg[a + i]);
+            case POW:
+                for (let i = 0; i < w; i++) d[i] = Math.pow(a[i], b[i]);
                 break;
-            case VM_OP.POW:
-                for (let i = 0; i < w; i++) reg[d + i] = Math.pow(reg[a + i], reg[b + i]);
+            case STEP:
+                for (let i = 0; i < w; i++) d[i] = b[i] < a[i] ? 0 : 1;
                 break;
-            case VM_OP.STEP:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[b + i] < reg[a + i] ? 0 : 1;
+            case SMOOTHSTEP:
+                for (let i = 0; i < w; i++) d[i] = smoothstep(a[i], b[i], c[i]);
                 break;
-            case VM_OP.SMOOTHSTEP:
-                for (let i = 0; i < w; i++) reg[d + i] = smoothstep(reg[a + i], reg[b + i], reg[c + i]);
+            // WGSL's `inverseSqrt`. Spelled as the reciprocal of a root rather than approximated,
+            // because the reference is the definition the hardware's estimate is measured against.
+            case RSQRT:
+                for (let i = 0; i < w; i++) d[i] = 1 / Math.sqrt(a[i]);
+                break;
+            case TAN:
+                for (let i = 0; i < w; i++) d[i] = Math.tan(a[i]);
+                break;
+            case ASIN:
+                for (let i = 0; i < w; i++) d[i] = Math.asin(a[i]);
+                break;
+            case ACOS:
+                for (let i = 0; i < w; i++) d[i] = Math.acos(a[i]);
+                break;
+            // `y` first, as `Math.atan2` and WGSL's `atan2` both take it.
+            case ATAN2:
+                for (let i = 0; i < w; i++) d[i] = Math.atan2(a[i], b[i]);
                 break;
 
-            // The reductions write a single lane. Whatever wants the result wider gets an explicit
-            // broadcast from the compiler; the implicit fill-all-four is gone.
-            case VM_OP.DOT: {
+            // The reductions write a single lane; whatever wants the result wider reads it through
+            // an `.xxxx` swizzle.
+            case DOT: {
                 let dp = 0;
-                for (let i = 0; i < w; i++) dp += reg[a + i] * reg[b + i];
-                reg[d] = dp;
+                for (let i = 0; i < w; i++) dp += a[i] * b[i];
+                d[0] = dp;
                 break;
             }
-            case VM_OP.CROSS: {
-                // Read both sources out before writing: the destination is allowed to be one of them.
-                const ax = reg[a], ay = reg[a + 1], az = reg[a + 2];
-                const bx = reg[b], by = reg[b + 1], bz = reg[b + 2];
-                reg[d] = ay * bz - az * by;
-                reg[d + 1] = az * bx - ax * bz;
-                reg[d + 2] = ax * by - ay * bx;
+            case CROSS:
+                d[0] = a[1] * b[2] - a[2] * b[1];
+                d[1] = a[2] * b[0] - a[0] * b[2];
+                d[2] = a[0] * b[1] - a[1] * b[0];
                 // A fourth lane, if asked for, is the zero the opcode used to append.
-                for (let i = 3; i < w; i++) reg[d + i] = 0;
+                d[3] = 0;
                 break;
-            }
-            case VM_OP.LENGTH: {
+            case LENGTH: {
                 let sum = 0;
-                for (let i = 0; i < w; i++) sum += reg[a + i] * reg[a + i];
-                reg[d] = Math.sqrt(sum);
+                for (let i = 0; i < w; i++) sum += a[i] * a[i];
+                d[0] = Math.sqrt(sum);
                 break;
             }
-            case VM_OP.NORMALIZE: {
+            case NORMALIZE: {
                 let sum = 0;
-                for (let i = 0; i < w; i++) sum += reg[a + i] * reg[a + i];
+                for (let i = 0; i < w; i++) sum += a[i] * a[i];
                 const len = Math.sqrt(sum);
                 const inv = len > 0 ? 1 / len : 0;
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * inv;
+                for (let i = 0; i < w; i++) d[i] = a[i] * inv;
                 break;
             }
-            case VM_OP.DISTANCE: {
+            case DISTANCE: {
                 let sum = 0;
                 for (let i = 0; i < w; i++) {
-                    const e = reg[a + i] - reg[b + i];
+                    const e = a[i] - b[i];
                     sum += e * e;
                 }
-                reg[d] = Math.sqrt(sum);
-                break;
-            }
-            case VM_OP.SWIZZLE: {
-                // Selected lanes are read before any is written, so an in-place swizzle is safe.
-                const pattern = s1;
-                const l0 = reg[a + (pattern & 3)];
-                const l1 = reg[a + ((pattern >> 2) & 3)];
-                const l2 = reg[a + ((pattern >> 4) & 3)];
-                const l3 = reg[a + ((pattern >> 6) & 3)];
-                if (w > 0) reg[d] = l0;
-                if (w > 1) reg[d + 1] = l1;
-                if (w > 2) reg[d + 2] = l2;
-                if (w > 3) reg[d + 3] = l3;
+                d[0] = Math.sqrt(sum);
                 break;
             }
 
-            case VM_OP.CMP_LT:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] < reg[b + i] ? 1 : 0;
+            case CMP_LT:
+                for (let i = 0; i < w; i++) d[i] = a[i] < b[i] ? 1 : 0;
                 break;
-            case VM_OP.CMP_LE:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] <= reg[b + i] ? 1 : 0;
+            case CMP_LE:
+                for (let i = 0; i < w; i++) d[i] = a[i] <= b[i] ? 1 : 0;
                 break;
-            case VM_OP.CMP_GT:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] > reg[b + i] ? 1 : 0;
+            case CMP_GT:
+                for (let i = 0; i < w; i++) d[i] = a[i] > b[i] ? 1 : 0;
                 break;
-            case VM_OP.CMP_GE:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] >= reg[b + i] ? 1 : 0;
+            case CMP_GE:
+                for (let i = 0; i < w; i++) d[i] = a[i] >= b[i] ? 1 : 0;
                 break;
-            case VM_OP.CMP_EQ:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] === reg[b + i] ? 1 : 0;
+            case CMP_EQ:
+                for (let i = 0; i < w; i++) d[i] = a[i] === b[i] ? 1 : 0;
                 break;
-            case VM_OP.SELECT:
-                for (let i = 0; i < w; i++) reg[d + i] = reg[c + i] > 0.5 ? reg[b + i] : reg[a + i];
+            case SELECT:
+                for (let i = 0; i < w; i++) d[i] = c[i] > 0.5 ? b[i] : a[i];
                 break;
 
-            // One draw per lane. Draw counts are part of the program's meaning — the draws are a
-            // sequence, so one fewer moves every value after it — and with distributions gone the
-            // count is exactly the width.
-            case VM_OP.RANDOM:
-                for (let i = 0; i < w; i++) reg[d + i] = draw_unit();
+            // One draw per lane, in lane order. Draw counts are part of the program's meaning — the
+            // draws are a sequence, so one fewer moves every value after it.
+            case RANDOM:
+                for (let i = 0; i < w; i++) d[i] = draw_unit();
                 break;
 
-            case VM_OP.CURVE: {
-                const v = sampleCurve(s0, reg[b]);
-                for (let i = 0; i < w; i++) reg[d + i] = v;
+            case CURVE: {
+                const v = sampleCurve(s0, b[0]);
+                for (let i = 0; i < w; i++) d[i] = v;
                 break;
             }
 
             default:
                 throw new Error(`ParticleVMReference: unhandled opcode ${op} at pc ${pc}`);
         }
+
+        const fixed_dest = OP_DEST[op];
+        const dest = fixed_dest < 0 ? w : fixed_dest;
+
+        for (let i = 0; i < dest; i++) {
+            reg[dst + i] = d[i];
+        }
     }
 
     return { killed, rng_state: state };

package/src/shade/renderer/particles/vm/chunk_particle_vm.d.ts.map

@@ -1 +1 @@
-{"version":3,"file":"chunk_particle_vm.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/vm/chunk_particle_vm.js"],"names":[],"mappings":"AAmXA;;;GAGG;AACH,gCAFU,SAAS,CAEqD;0BAvX9C,oCAAoC"}
+{"version":3,"file":"chunk_particle_vm.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/vm/chunk_particle_vm.js"],"names":[],"mappings":"AA6UA;;;GAGG;AACH,gCAFU,SAAS,CAEmG;0BAhV5F,oCAAoC"}