@nataliapc/mcp-openmsx 1.1.15 → 1.2.2

package/resources/audio/psg_registers.md

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+# PSG Registers
+
+## Index
+
+- [PSG Registers overview](#psg-registers-overview)
+- [Frequency control registers](#)
+- [White noise frequency control register](#)
+- [PSG voice and I/O port control register](#)
+- [Amplitude and volume control registers](#)
+- [Envelope Form and Period Control Registers](#)
+- [PSG I/O Parallel Port Registers](#)
+
+
+## PSG Registers overview
+
+The PSG has 16 registers in which the content can be read and written except for register 14 which can only be read. To access the PSG registers, Bios in Main-ROM has two routines. The first is WRTPSG (00093h) which allows you to configure the PSG. The second, RDPSG (00096h), is used to read contents of a register.
+
+There is also a routine in Bios of the Main-ROM called GICINI (00090h), which is used to initialize the PSG and the data of the instruction PLAY. Once initialized, all registers from 0 to 13 will be set to zero except register 0 which will have the value 01010101b (55h), register 7 which will have 10111000b (B8h) and register 11 which will have 1011b (0BH) for the period of the envelope.
+
+PSG registers are also directly accessible through the I/O ports: 0A0h, 0A1h and 0A2h.
+To write in a register directly via the I/O ports, you must write the register number to port 0A0h then the value to be written to port 0A1h. Take care to cut interrupts while writing register number and value. To read a register via the I/O ports, write the register number to read to port 0A0h then read the value from port 0A2h.
+
+## Frequency control registers
+
+The first six registers are used to set the frequency to be generated to produce a sound.
+
+```
+             bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 0 |         8 least significant bits of voice frequency 1         |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 1 |   -   |   -   |   -   |   -   |  4 MSB of voice frequency 1   |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 2 |         8 least significant bits of voice frequency 2         |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 3 |   -   |   -   |   -   |   -   |  4 MSB of voice frequency 2   |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 4 |         8 least significant bits of voice frequency 3         |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 5 |   -   |   -   |   -   |   -   |  4 MSB of voice frequency 3   |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+```
+
+Value indicating the frequency of the white noise generator is 5 bits. The value to be written is obtained using the following formula:
+```
+Value = Fi / (16 x Fb)
+```
+
+- Fi = Internal frequency of PSG (1789772.5 Hz on MSX)
+- Fb = Tone frequency master to be produced (varies between between 27 and 111.860 Hz)
+
+For simplicity, here is a table of musical notes by octave obtained according to the value indicated in registers 0-1, 2-3 or 4-5.
+
+| Note | Octave 1 | Octave 2 | Octave 3 | Octave 4 | Octave 5 | Octave 6 | Octave 7 | Octave 8 |
+|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|
+|C|D5Dh|6AFh|357h|1ACh|0D6h|06Bh|035h|01Bh|
+|C#|C9Ch|64Eh|327h|194h|0CAh|065h|032h|019h|
+|D|BE7h|5F4h|2FAh|17Dh|0BEh|05Fh|030h|018h|
+|D#|B3Ch|59Eh|2CFh|168h|0B4h|05Ah|02Dh|016h|
+|E|A9Bh|54Eh|2A7h|153h|0AAh|055h|02Ah|015h|
+|F|A02h|501h|281h|140h|0A0h|050h|028h|014h|
+|F#|973h|4BAh|25Dh|12Eh|097h|04Ch|026h|013h|
+|G|8EBh|476h|23Bh|11Dh|08Fh|047h|024h|012h|
+|G#|86Bh|436h|21Bh|10Dh|087h|043h|022h|011h|
+|A|7F2h|3F9h|1FDh|0FEh<sup>*</sup>|07Fh|040h|020h|010h|
+|A#|780h|3C0h|1E0h|0F0h|078h|03Ch|01Eh|00Fh|
+|B|714h|38Ah|1C5h|0E3h|071h|039h|01Ch|00Eh|
+
+<sup>(*)</sup> 0FEh is the note produced by a tuning fork.
+For example, to produce the note Do in octave 4 by voice 1, we would write 1h in register 1 and ACh in register 0. In practice, this looks like below.
+In assembler:
+
+```
+WRTPSG	equ	00093h
+
+; --&gt; File header
+    db	0feh	; Binary code file
+    dw	START	; Program destination address
+    dw	END	; Program end address
+    dw	START	; Program execution address
+; ---
+    org	0c000h
+START:	
+    ld	b,13
+PSGini:	ld	a,b	; 
+    ld	e,0	; 8 least significant bits
+    cp	7
+    jr	nz,NoR7	; Jump if register different from 7
+    ld	e,10111111b	; Bit 7 to 1 and bit 6 to 0
+NoR7:	call	WRTPSG
+    djnz	PSGini	; Loop to initialize registers 
+
+    ld	a,0	; Register 0
+    ld	e,0ach	; 8 least significant bits
+    call	WRTPSG
+    ld	a,1	; Register 1
+    ld	e,1	; 4 most signifiant bits
+    call	WRTPSG
+    ld	a,8	; Register 8
+    ld	e,1100b	; Voice volume 1 to 12
+    call	WRTPSG
+    ld	a,7	; Register 7
+    ld	e,10111110b	; Enable voice 1 
+    call	WRTPSG
+    ret
+END:
+```
+
+Once assembled and saved as "V15O1C.BIN", run the routine with the following instruction.
+```
+BLOAD"V15O1C.BIN",R
+```
+In BASIC:
+```
+5 ' Initializes the sound registers of the PSG
+10 FOR R=0 TO 13
+20 IF R=7 THEN SOUND R,&amp;B10111111 ELSE SOUND R,0
+30 NEXT
+40 ' Play the note C on voice 1 with a volume of 12
+50 SOUND 0,&amp;hAC ' 8 least significant bits in register 0
+60 SOUND 1,1 ' 4 most significant bits in register 1
+70 SOUND 8,&amp;b1100 ' Adjusting the volume of voice 1 to 12
+80 SOUND 7,&amp;b10111110 ' Enables the sound generator on voice 1
+```
+
+## White noise frequency control register
+
+This register is used to enable or disable the sound generator as well as the noise generator.
+
+```
+             bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 6 |   -       -       -   |    White noise generator frequency    |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+```
+
+Value indicating the frequency of the white noise generator takes up 5 bits. The value to be written is obtained using the following formula. Only the 5 bits of the value are to be written in register 6.
+```
+Value = Fi / 16 x Fb
+```
+- Fi = PSG internal frequency (1789772.5 Hz)
+- Fb = Base frequency of the noise to be produced (varies between 3.608 and 111.860 Hz)
+
+## PSG voice and I/O port control register
+
+This register is used to enable or disable the sound generator as well as the noise generator. It is also used to adjust the direction of the PSG I/O ports.
+
+```
+             bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
+           | PSG I/O Ports |  Make the noise mute  |  Make the tone mute   |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 7 |  B=1  :  A=0  |voice3 :voice2 :voice1 |voice3 :voice2 :voice1 |
+           +-------+-------+-------+-------+-------+-------+-------+-------+
+```
+
+Notes:
+- To make mute the sound on a voice, you can set the volume of the voice to 0 (registers 8 to 10) or deactivate the tone and noise generator of this voice by setting the corresponding bits of register 7 to 1.
+- In order to guarantee the proper functioning of the PSG I/O ports, bit 7 of register 7 must always remain at 1 (port B in output mode) and bit 6 at 0 (port A in input mode).
+- It is therefore possible to enable the sound generator and the noise generator at the same time on each voice. That is to say, mix the two.
+
+## Amplitude and volume control registers
+
+```
+              bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 8  |   -       -       -   |  V/A  |  Voice Volume / Amplitude 1   |
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 9  |   -       -       -   |  V/A  |  Voice Volume / Amplitude 2   |
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 10 |   -       -       -   |  V/A  |  Voice Volume / Amplitude 3   |
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+```
+
+Reset bit 4 (V/A) to adjust the sound volume of the corresponding voice.
+When bit 4 (V/A) is set, the volume will vary in proportion to the shape of the envelope defined by register 13.
+
+## Envelope Form and Period Control Registers
+
+```
+              bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 11 |  8 LSB of the value that determines the envelope period (T)   |
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 12 |  8 MSB of the value that determines the envelope period (T)   |
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+Register 13 |   -       -       -       -   |        Envelope shape         |
+            +-------+-------+-------+-------+-------+-------+-------+-------+
+```
+
+Registers 11 and 12 control the envelope period. The value is on 16 bits (0~65535). It is calculated with the following expression: 
+```
+Value = Fi / (256 x T)
+```
+- Fi = Internal frequency of PSG (1789772.5 Hz on MSX)
+- T = Period of the envelope (in μs)
+
+The register 13 defines the envelope shape. Here are the possible shapes:
+```
+00xx = _|\______    01xx = _/|_____
+
+1000 = _|\|\|\|\    1001 = _|\_____
+                               ____
+1010 = _|\/\/\/\    1011 = _|\|
+                             ______
+1100 = _/|/|/|/|    1101 = _/
+
+1110 = _/\/\/\/\    1111 = _/|_____
+        T                   T
+```
+
+Bits detail:
+- Bit 0 (Hold) specifies whether the period should be repetitive or not.
+- Bit 1 (Alternate) specifies whether or not the shape of the envelope should be inverted on each repetition.
+- Bit 2 (Attack) specifies whether or not to invert the shape of the envelope.
+- Bit 3 (Continue) specifies that the shape of the envelope should remain at the same level at the end of the period.
+
+## PSG I/O Parallel Port Registers
+
+Registers 14 and 15 are used to access and control the parallel ports of the PSG. On MSX, Port A is connected as an entry and B at the output to read general ports 1 or 2 (joystick ports) as well as two other signals to know the type of Japanese keyboard used, as well as the signal read by the cassette interface. Register 15 is used to control the general ports, as well as the LED of the "Code" or "Kana" keys.
+
+```
+               bit 7    bit 6    bit 5    bit 4   bit 3   bit 2   bit 1   bit 0
+            +--------+--------+--------+--------+-------+-------+-------+-------+
+Register 14 | Port parallel A of E/S of PSG (Always set as input with R#7 bit6) |
+            +--------+--------+--------+--------+-------+-------+-------+-------+
+```
+
+This register allows to read the state of the pins for the selected general port, the Japanese keyboard type (JIS or JP50on), and the signal read from the cassette interface.
+
+- Bit 0 = Pin 1 state of the selected general port (Up if joystick)
+- Bit 1 = Pin 2 state of the selected general port (Down if joystick)
+- Bit 2 = Pin 3 state of the selected general port (Left if joystick)
+- Bit 3 = Pin 4 state of the selected general port (Right if joystick)
+- Bit 4 = Pin 6 state of the selected general port (Trigger A if joystick)
+- Bit 5 = Pin 7 state of the selected general port (Trigger B if joystick)
+- Bit 6 = 1 for JIS keyboard, 0 for JP50on (only valid for Japanese MSX)
+- Bit 7 = CASRD (signal read from the cassette interface)
+
+```
+               bit 7    bit 6    bit 5    bit 4    bit 3   bit 2   bit 1   bit 0
+            +--------+--------+--------+--------+--------+-------+-------+-------+
+Register 15 | Port parallel B of E/S of PSG (Always set as output with R#7 bit7) |
+            +--------+--------+--------+--------+--------+-------+-------+-------+
+```
+
+This register allows to control the direction of the signals  of the general port, which can be read via register 14. It allows also to set or read the state of the LED of the "code" or "kana" keys, depending on the keyboard.
+
+- Bit 0 = pin control 6 of the general port 1<sup>*</sup>
+- Bit 1 = pin control 7 of the general port 1<sup>*</sup>
+- Bit 2 = pin control 6 of the general port 2<sup>*</sup>
+- Bit 3 = pin control 7 of the general port 2<sup>*</sup>
+- Bit 4 = pin control 8 of the general port 1 (0 for standard joystick mode)
+- Bit 5 = pin control 8 of the general port 2 (0 for standard joystick mode)
+- Bit 6 = selection of the general port readable via register 14 (1 for port 2)
+- Bit 7 = LED control of the "Code" or "Kana" key. (1 to turn off)
+
+<sup>(*)</sup> Put to 1 if the general port is used as a starter (reading).
+
+The general port pins are connected as follows.
+
+```
+     General port 1                   General port 2
+  ┌───────────────────┐            ┌───────────────────┐
+  │ 1   2   3   4   5 ──── +5V     │ 1   2   3   4   5 ──── +5V
+   \                 /              \                 /
+    \ 6   7   8   9 ────── GND       \ 6   7   8   9 ────── GND
+    └───────────────┘                └───────────────┘
+   1│6│2│7│3│8│4│                   1│6│2│7│3│8│4│
+    │ │ │ │ │ │ │                    │ │ │ │ │ │ │
+    └─└─└─└─└─|─│1-4,6-7      1-4,6-7│─┘─┘─┘─┘─│─┘
+             8| ▼                    ▼        8│
+To bit 4 of <─┘ ┌────────────────────┐        └─> To bit 5 of
+PSG port B      │Commutation circuit │            PSG port B
+                │                    ┼──────┐
+                └──┼──┼──┼──┼──┼──┼──┘      ▼
+                  1│ 2│ 3│ 4│ 6│ 7│        To bit 6 of PSG port B
+                   ▼  ▼  ▼  ▼  ▼  ▼        (General port select signal)
+               To bits 0-5 of PSG port A
+```
+
+© 1996-2025  Microcomputer & Related Culture Foundation. MSX is a trademark of MSX Licensing Corporation. 

package/resources/audio/sound_cartridge_scc.md

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+# Konami SCC Sound Chip
+
+
+The SCC is a wavetable sound chip, just like the Gravis Ultra Sound, Sound Blaster (AWE)32 and Moonsound.  They all have memory (tables), in which samples (waves) are stored.  The samples are played back looped. The speed with which the samples are played, determines the frequency of the tone.  A modern wavetable sound module usually has over a megabyte of memory, while the SCC has 128 bytes of memory.
+
+List of what the SCC ICs says:
+- My Salamander SCC IC: `KONAMI 051649 2212P003 JAPAN 8750AAA`.
+- F1 Spirit: `KONAMI 051649 2212P003 JAPAN 8723AAA`.
+- King's Valley 2 (MSX1): `KONAMI 051649 2212P003 JAPAN 8836EAI`.
+- My Haunted Castle (Arcade PCB): `KONAMI 051649 2212P003 JAPAN 8802EAI`.
+
+
+Clay Cowgill explains: the last digits aren't really a serial number, but rather a date code and fabrication location/lot numbers. The format is Year, Week, Info, so 8740AAA is:
+
+1987, 40th week (probably early November), AAA code (that would be manufacturer specific, but it probably tells what factory made it, what wafer batch it was from, what process line it was on, etc.)
+
+You'll notice that the first two digits stay between 87-88 (they seem to have made all the chips between 1987 and 1988) and the next two digits are between 01-52 (only 52 weeks in a year).
+
+Otherwise, all the chips you listed should be identical.  (You could swap them and they'd still work the same in theory-- they were just made at different times.)
+
+This SCC was also used in several arcade games made by Konami. As far as I know they are: Haunted Castle, City Bomber, Hexion, Nyan Nyan Panic. All of these are emulated by mame. Apart from the SCC (known as K051649 in MAME) they also use an YM3812 (OPL3) for music and another chip for samples.
+
+I've got the Haunted Castle PCB, [Levien van Zon](http://maleb.scum.org/) has made an [excellent scan](http://bifi.msxnet.org/msxnet/tech/Konami_GX768.jpg) of it. To the left of the SCC (which is at the top-left) you can see the resistors packed into one device (which is for D/A conversion). You can also see the YM3812 (OPL3) and the Z80A.
+
+The SCC has five channels. There are four functions for each channel:
+- 32 bytes waveform.
+- 12 bits frequency.
+- 4 bits volume.
+- 1 bit on/off switch.
+
+Just like the bank select registers, the SCC is accessed through memory mapped I/O, and not through I/O ports. If you write xx111111b (3Fh, bits 7 and 6 are ignored) to bank select register 3 (memory area 9000h to 97FFh, see megaROM mappers for more information), the SCC can be accessed through memory area from 9800h to 9FFFh.
+
+The register structure is similar to the PSG.
+
+| Address | Function |
+| 9800h-981Fh | waveform channel 1 |
+| 9820h-983Fh | waveform channel 2 |
+| 9840h-985Fh | waveform channel 3 |
+| 9860h-987Fh | waveform channel 4 and 5 |
+| 9880h-9881h | frequency channel 1 |
+| 9882h-9883h | frequency channel 2 |
+| 9884h-9885h | frequency channel 3 |
+| 9886h-9887h | frequency channel 4 |
+| 9888h-9889h | frequency channel 5 |
+| 988Ah | volume channel 1 |
+| 988Bh | volume channel 2 |
+| 988Ch | volume channel 3 |
+| 988Dh | volume channel 4 |
+| 988Eh | volume channel 5 |
+| 988Fh | on/off switch channel 1 to 5 |
+| 9890h-989Fh | same as 9880h to 988Fh |
+| 98A0h-98DFh | no function |
+| 98E0h-98FFh | test register |
+
+As you may have noticed, channel 4 shares its waveform with channel 5. The SCC+ has five waveforms so each channel has it's own waveform. See SCC+ Sound Cartridge for more information.
+
+The waveform is made up of 32, signed (two's complement) bytes. The waveform represents the actual form of the tone the sound chip produces. It's played back from byte 0 to 31, and then again from 0 to 31, etc. A value of 0 means no amplitude. From 1 to 127 results in an increasingly higher amplitude. From -1 to -128 (FFh to 80h) results in an increasingly higher negative amplitude.
+
+The frequency is stored the same way as in the PSG. The first byte contains bits 0 to 7 from the frequency. Bits 0 to 3 of the second byte contain bits 8 to 11 of the frequency. Bits 4 to 7 of the second byte are ignored. Remember that the value you enter is a period: a higher value gives a lower frequency.
+
+The formula for calculating the frequency of the tone is the same as from the PSG:
+```
+               fclock
+   ftone = -------------
+            32 * (TP + 1)
+```
+- fclock: is the clock frequency of the computer. 3,579,545 Hz
+- ftone: is the frequency of the channel
+- TP: is the value in the frequency registers
+
+The volume is stored in the same way as in the PSG, though it does not support envelopes. Bits 0 to 3 contain a volume of 0 to 15, and bits 7 to 4 are ignored. A volume of 0 is silent, and a volume of 15 is maximum volume.
+
+The on/off switch register switches the different channels on or off. Set the associated bit high for a channel to activate it. It has the following structure:
+
+| **Bit** | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|
+| **Channel** | none | none | none | 5 | 4 | 3 | 2 | 1 |
+
+
+### Test Register - 98E0h
+
+This register is not used by Konami. All the addresses in the memory area (98E0h - 98FFh) refer to the same register. It is set a different memory area in the SCC+ (Sound Cartridge).
+
+I haven't ever seen a description of this register, but by sampling the SCC on my PC, I've tried figuring out it's function.
+
+| **Bit** | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|
+| **Function** | noise | noise | ? | ? | ? | ? | pitch | pitch |
+
+The default value seems to be 0.
+
+The pitch bits change the frequency of all the channels. If they are set to 11B or 10B, all the frequencies are multiplied by 16. If they are set to 01B, all the frequencies are multiplied by 256. (Most frequencies are shifted out of hearing range, except if you set the frequency to minimum (TP = FFFh), then you'll hear something.)
+
+If the noise bits are set to 01B, channel 4 and 5 produce noise (=random frequencies near TP), and if the bits are set to 11B, channel 4 and 5 produce noise with envelopes.
+
+This is as much as I've figured out so far. It probably isn't (completely) correct, but I'll continue to try and figure it out. If you think you can help me in any way, please do so.
+
+## Memory Behaviour
+
+The memory area from 9800h to 987Fh behaves as RAM. The memory area from 9880h to 98FFh is write only; if you read it, it'll always return FFh.
+
+The memory area from 9900h to 99FFh has exactly the same function as from 9800h to 98FFh. The same accounts for the area from 9A00h to 9AFFh, and so on to the area from 9F00h to 9FFFh. This behaviour can be easily be explained: the SCC/Mapper does not process address line A8 - A10, thus it cannot distinguish 9900h from 9800h, or 9F00h from 9800h. See [pinouts.txt](http://bifi.msxnet.org/msxnet/tech/pinouts.txt) for more info.
+
+The memory area from 8000h to 97FFh is a part of the ROM as you would expect it to be.
+
+## Locating the SCC
+
+How do you in which slot the SCC is? One way is to search the slots for cartridge with the 'AB' code that can be removed by writing a value other than 0 to the bank select register. However, in some cartridges the ROM is disabled; you won't find the 'AB' code. A better why is to search for a slot that contains ROM, and contains RAM at 9800h - 987Fh after writing 3Fh to 9000h. This will also work on the SCC+.
+
+However, not all MSX emulators emulate the RAM behaviour; it's not used by any Konami game. To use the SCC on a emulator, assume that it is in slot 1 - 0, and write 3Fh to 9000h, and write your data to 9800h - 988Fh.
+
+## Weird Behaviour
+
+I have a disassembler/monitor called monMSX, and if I view the SCC wave memory with it, it starts behaving very erratic. Every time its memory is read, it returns different values. Writing values does not seem to have any effect either.
+
+If I then exit monMSX and start a game that uses the SCC, it sounds very weird. The waveforms seem to be wrong up. (volume and frequencies seem to be correct.)
+
+---
+
+(c)BiFi <<bifi@msxnet.org>>
+
+
+

package/resources/audio/sound_cartridge_scci.md

@@ -0,0 +1,250 @@
+# Konami's Sound Cartridge SCC+ (SCCI)) for the MSX
+
+## Index
+
+- [Features](#features)
+- [Hardware Properties](#hardware-properties)
+- [Expanding RAM memory](#expanding-ram-memory)
+  - [Connecting the Memory Banks](#connecting-the-memory-banks)
+- [Using SCC+](#using-scc)
+  - [Loading ROM files into Sound Cartridge](#loading-rom-files-into-sound-cartridge)
+- [Programming](#programming)
+  - [Memory](#memory)
+  - [Mode Register](#mode-register)
+	- [Writing to the Mode Register](#writing-to-the-mode-register)
+  - [Using the Sound Chip - SCC mode](#using-the-sound-chip---scc-mode)
+  - [Using the Sound Chip - SCC+ mode](#using-the-sound-chip---scc-mode-1)
+
+
+## Features
+
+The Konami games Snatcher and SD Snatcher are both games on disks that operate with a cartridge, a Sound Cartridge. The cartridge is supplied with the original games.
+
+This Sound Cartridge contains 64Kb RAM and a SCC (a sound chip designed by Konami). The RAM is not standard, so it can't be used with MemMan or any other standard program. The SCC is slightly better than the one in Konami megabit ROM cartridges. That is probably how the cartridge got the nickname "SCC+", to my knowledge Konami never used this name.
+
+There were some rumours that the RAM in the cartridges was SRAM and the SCC was a 16 channel sound chip. As most rumours, this is not true. The RAM is just the usual DRAM (volatile) and the SCC is a 5 channel SCC. There also isn't a SCC+ in any megaROM. Several people on the MSX mailinglist have checked Solid Snake, Space Manbow, Quarth amongst others.
+
+The two Sound Cartridges are different and incompatible. They are identical in capabilities, only the memory layout is different. So the sound chip itself is identical.
+
+I assume Konami changed the layout so the cartridges are incompatible; if one owned Snatcher (lucky sod, nowadays) you would have to buy SD Snatcher, not just copy the disks of SD Snatcher (of course, anyone who knew Z80 assembly could `fix` that problem).
+
+The sound chip is normal SCC (= the SCC in Konami megabit ROM cartridges) compatible. This means it can be used with cracked Konami megabit ROM cartridges for the music. Also, there is no game in the Sound Cartridge, so it doesn't need to be modified to be used (or inserted after startup).
+
+The improvement of SCC is compared to the normal SCC that the Sound Cartridge has a extra waveform. Now channel 4 doesn't have to share its waveform with channel 5 (thus all five channels have a private waveform).
+
+## Hardware Properties
+
+The number written on the large IC is "KONAMI 052539 SCC-I2312P001 JAPAN", which is the same number written on the Snatcher SCC+ of Klaas de Wind (I haven't opened my own Snatcher SCC+ ^^;). This shows that the sound chip of SD Snatcher and Snatcher are identical.
+
+The sound IC is very large compared to the normal megaROM SCC IC. There are some very obvious reasons for this. First of all, to recoqnise the address BFFEh indepentently of all other addresses, all 16 address lines must be connected to it. Not all address lines are connected to a megaROM SCC IC (difference : 3 lines). The RAM is DRAM, so the address lines are multiplexed. So a seperate connect is necessary for the DRAM and the refresh signal is necessary (difference : about 11).
+
+On the picture there are four postions for DRAM ICs. As you can see only two are used. Now there'll all filled! In the Snatcher SCC+, the other two postions are filled, that's the difference.
+
+## Expanding RAM Memory
+
+It's possible to add another 64Kb RAM to both cartridges. There are two open places on the print for it (see the picture above.). They're four bits wide, and have a 64K range. That's RAM IC type 4464. Note that on the RAM ICs already on-board do not have standard types printed on them.
+
+If you've added the RAM, you can load Konami MegaROMs of 128Kb in it. It's very nice because the cartridge behaves exactly as a real SCC cartridge when it's loaded. Until you turn the power off. :) See below for the program to load unmodified .rom files.
+
+Now all SD/The Snatchers and game collections work with your cartridge.
+
+If you're going to do this and don't have much experience soldering: I had some trouble getting the ICs onto the PCB, because Konami was nice enough to put solder in the holes where the pins have to go in. Someone told me to use a soldering pump (also called solder sucker, tinzuigertje in Dutch) to get the solder out. Using that device it was a piece of cake.
+
+### Connecting the Memory Banks
+
+It is possible to connect the two 64Kb memory banks so they both seems to exist (mirrored). Now values 0-7 selects the same memory area as values 8-15. This works for both cartridges.
+
+Now all Konami games work with your cartridge, but it is not possible to load megaROMs into it.
+
+To do this, connect the CAS (pin 16) of one of the RAM ICs with the CAS of the places where you can put a RAM IC. Easy as can be. Konami used the CAS (Collumn Address Strobe) as a sort of Output Enable.
+
+## Using SCC+
+
+The Snatcher Sound Cartridge can be used with the Konami Games Collections, since most games in these collections have been improved to use the Snatcher Sound Cartridge sound chip.
+
+There are cracks around of SD Snatcher, The Snatcher and the Games Collections which operate with a standard megaROM SCC. Mostly the music sounds the same, but because the megaROM SCC has one wave form less, it sometimes will sound differently.
+
+The Konami Games Collections and The Snatcher cannot be used with the standard SD Snatcher cartridge, but they can with the Snatcher cartridge. This is because they use values 0-7 for the bank select registers, which select the non-existing memory in the SD Snatcher cartridge so it does not seem to exist.
+
+There are several solutions to this problem:
+- Modify the games. Add 8 to every value that this written to a bank select register.
+- You can also add another 64Kb RAM to your cartridge (see above).
+- Or you can connect the two 64Kb memory areas so they seem one (see above).
+
+SD Snatcher works only with the SD cartridge. Values 8-15 select the memory.
+
+### Loading ROM Files into Sound Cartridge
+
+Since the Sound Cartridge contains RAM, it is possible to load ROM files into it. The standard Sound Cartridge (SD or The Snatcher) can only hold ROM files up to 64Kb (that's the amount of RAM) or 128Kb if it is expanded.
+
+If you've expanded the RAM of your Sound Cartridge, you can also load one megabit (128Kb) ROM files into your Sound Cartridge. Note that the Sound Cartridge will be behave exactly as an Konami SCC 1 megabit ROM. (until 2 ms after you turned the power off. ^_^) These ROM files can be loaded without problem, but the Konami 1 megabit ROM without SCC can also using SCROM.
+
+SCROM can convert them to use the correct mapper addresses, that's not 4000h/6000h/8000h/A000h, but 5000h/7000h/9000h/B000h). Documentation is in the zip file.
+
+[scrom.zip](http://bifi.msxnet.org/msxnet/tech/scrom.zip) (Sound Cartridge ROM loader)
+
+The fact that this is possible makes me think that this cartridge was used for testing Konami ROMs while they were in development. Of course, this is only speculation.
+
+## Programming
+
+In this section I'll atempt to explain how the SCC+ can be used from assembly. It is much like a normal SCC, but now with RAM and an extra wave form.
+
+### Memory
+
+As with Konami megaROMs, the memory is divided into four memory banks:
+```
+	Bank 1: 4000h-5FFFh
+	Bank 2: 6000h-7FFFh
+	Bank 3: 8000h-9FFFh
+	Bank 4: A000h-BFFFh
+```
+
+And, to access the bank select registers, write to any address of the following memory areas:
+```
+	Bank 1: 5000h-57FFh
+	Bank 2: 7000h-77FFh
+	Bank 3: 9000h-97FFh
+	Bank 4: B000h-B7FFh
+```
+
+As you can see this much like the megaROM SCC. See megaROM mappers for more information on memory banks and bank select registers.
+
+Both cartridges have a (physical) memory bank of 128Kb RAM while there is only 64Kb installed on it. Thus there are 16 memory areas of each 8Kb. Bits 7 to 4 are ignored, thus 16 (10000b) selects the first memory area (0).
+
+Here's the difference between The Snatcher cartridge and SD Snatcher cartridge:
+- On the Snatcher cartridge, the RAM is installed in the lower part of the 128Kb
+(values 0-7 select installed RAM, 8-F select nothing (if you read it you'll get FFh)).
+- And on the SD Snatcher cartridge the RAM is installed in the higher part of the 128Kb: values 0-7  select nothing, 8-F select installed RAM).
+
+It is possible to add the other 64Kb RAM to both cartridges. This has several interesting advantages, see somewhere above for more information.
+
+By default, the bank select registers have the following values:
+```
+	Bank 1: 0
+	Bank 2: 1
+	Bank 3: 2
+	Bank 4: 3
+```
+
+(As, of course, a megaROM cartridge.) This select the first 32Kb RAM in the The Snatcher cartridge, and nothing in the SD Snatcher cartridge (unless expanded). This is important for memory residant programs, because the 'AB' code must be there. In the standard SD Snatcher cartridge memory resident programs disappear (get deselected) after a hard reset.
+
+In its initial state, you can only read from the memory. But, it wouldn't be very useful if you couldn't write to it. That's why you can change to RAM mode. In this mode, you can't change memory areas, but you can read and write to the memory (where existing). I've called the mode in which you can change memory areas "bank select mode".
+
+To change modes, use the:
+
+### Mode Register
+
+Using the mode register, you can switch between normal SCC and SCC+ mode and between RAM and bank select mode.
+
+| Bit |  Function |
+|:-:|---|
+| 7 | none |
+| 6 | none |
+| 5 | Sound Mode (1 = SCC+, 0 = SCC) |
+| 4 | Memory Mode (1 = RAM, 0 = bank select) |
+| 3 | none |
+| 2 | Bank 3 Mode (1 = RAM, 0 = bank select) |
+| 1 | Bank 2 Mode (1 = RAM, 0 = bank select) |
+| 0 | Bank 1 Mode (1 = RAM, 0 = bank select) |
+
+The Memory Mode bit sets all memory banks to either RAM or bank select, but the Bank x Mode bits are for setting the memory banks individually back to RAM mode when the cartridge is in bank select mode. They sort of "override" the bank select mode. The Bank x Mode bits have no effect in RAM mode.
+
+When the cartridge is in bank select mode (bit 4 low), banks 1, 2 and 3 can be set back into RAM individually using bits 0, 1 and 2.
+
+If Bank 1 Mode is high, and the cartridge is in bank select mode (bit 4 is low), Bank 1 is put into RAM mode. The same applies to Bank 2 mode.
+
+For the Bank 3 Mode, there is another requirement: the cartridge must be in SCC+ mode, and not SCC mode. Thus, if bit 4 is low, bit 5 high and bit 2 high, bank 3 is in RAM mode. (Mode Register value 24h for example)
+
+So for some examples:
+```
+Value:	Bank 1   2   3   4
+ 10h	    RAM RAM RAM RAM
+ 01h	    RAM ROM ROM ROM
+ 27h	    RAM RAM RAM ROM
+ 07h	    RAM RAM ROM ROM
+```
+
+The Mode Register has the initial value 0: by default, it is in SCC compatibility mode and bank select mode (thus operating exactly like a megaROM cartridge).
+
+Here are some useful values for the Mode Register (Konami uses some of these; they're holy & very logical). Note that the lower Fh could just as well be any other value, they're just there to make it obvious you want RAM mode.
+
+| Value | Memory Mode | Sound Mode |
+|:-:|:-:|:-:|
+| 00h | bankselect | SCC |
+| 1Fh | RAM | SCC |
+| 20h | bankselect | SCC+ |
+| 3Fh | RAM | SCC+ |
+
+#### Writing to the Mode Register
+
+The mode register can be written to via memory mapped I/O address BFFEh and BFFFh. It can't be read; if you try to read one of these addresses, you'll get a byte from the memory bank as you would have expected. It does not matter whether you use address BFFEh or BFFFh.
+
+This, of course, has an annoying consequence: RAM at address BFFEh and BFFFh cannot be changed. Note that if you use the same RAM in a different bank, these restrictions do not apply.
+
+### Using the Sound Chip - SCC mode
+
+When bank 3 is in bank select mode and in SCC mode, you can use the SCC in more or less the same way as the SCC in a megaROM. You must write xx11111b (3Fh, bits 6/7 do not matter) to bank select register 3. Now you can access the SCC in memory area 9800h-9FDFh. If bank 3 is in RAM mode, you can read from the SCC but you can't write to it.
+
+| Address | Function |
+|:-:|---|
+| 9800h-981Fh | waveform channel 1 |
+| 9820h-983Fh | waveform channel 2 |
+| 9840h-985Fh | waveform channel 3 |
+| 9860h-987Fh | read: waveform channel 4<br>write: waveform channel 4 and 5 |
+| 9880h-9881h | frequency channel 1 |
+| 9882h-9883h | frequency channel 2 |
+| 9884h-9885h | frequency channel 3 |
+| 9886h-9887h | frequency channel 4 |
+| 9888h-9889h | frequency channel 5 |
+| 988Ah | volume channel 1 |
+| 988Bh | volume channel 2 |
+| 988Ch | volume channel 3 |
+| 988Dh | volume channel 4 |
+| 988Eh | volume channel 5 |
+| 988Fh | on/off switch channel 1 to 5 |
+| 9890h-989Fh | same as 9880h-988Fh |
+| 98A0h-98BFh | read: waveform channel 5 (no write) |
+| 98C0h-98DFh | test register |
+| 98E0h-98FFh | no function |
+
+The test register is a different memory area, and the waveform of channel 5 can be read separately. Whatever you write to waveform channel 4 (9860h-987Fh), also gets written to waveform channel 5. In this way it is fully megaROM SCC compatible (except for the test register which is at 98E0h-98FFh in the megaROM SCC.
+
+In this mode, waveform from channel 4 and 5 can only differ if they have just been changed in SCC+ mode.
+
+See SCC Sound Chip for more information.
+
+### Using the Sound Chip - SCC+ mode
+
+When bank 4 is in bank select mode and in SCC+ mode, you can active the SCC by writing 1xxxxxxxb (80h, bits 0 to 6 are not important) to bank select register 4. The SCC+ appears at memory area B800h to BFDFh (last two bytes are for mode register). It has the following structure, which is much like the SCC. If bank 4 is in RAM mode you can read from the SCC but you can't write to it.
+
+| Address | Function |
+|:-:|---|
+| B800h-B81Fh | waveform channel 1 |
+| B820h-B83Fh | waveform channel 2 |
+| B840h-B85Fh | waveform channel 3 |
+| B860h-B87Fh | waveform channel 4 |
+| B880h-B89Fh | waveform channel 5 |
+| B8A0h-B8A1h | frequency channel 1 |
+| B8A2h-B8A3h | frequency channel 2 |
+| B8A4h-B8A5h | frequency channel 3 |
+| B8A6h-B8A7h | frequency channel 4 |
+| B8A8h-B8A9h | frequency channel 5 |
+| B8AAh | volume channel 1 |
+| B8ABh | volume channel 2 |
+| B8ACh | volume channel 3 |
+| B8ADh | volume channel 4 |
+| B8AEh | volume channel 5 |
+| B8AFh | on/off switch channel 1 to 5 |
+| B8B0h-B8BFh | same as B8A0h-B8AFh |
+| B8C0h-B8DFh | test register |
+| B8E0h-B8FFh | no function |
+
+The difference is that now channel 5 has a private waveform. For more information about the operation of the SCC, see SCC Sound Chip.
+
+The fact that SCC may be addressed in two modes, this does not mean that the SCC+ has twice the channels of normal SCC. If you change Sound Mode, the different addresses refer to the same registers.
+
+If the SCC control areas (these things above) are active, and you put the SCC+ into RAM mode and then start writing to the control areas, some really weird things happen in the RAM. The SCC is unaffected but whole areas of the RAM are messed up.
+
+---
+
+(c)BiFi <<bifi@msxnet.org>>