@h2loop/autosar 1.0.1 → 1.2.0

package/python/ecuc_engine/codegen/modules/mcal.py

@@ -0,0 +1,170 @@
+"""Port and Dio from the STANDARD R25-11 param defs, plus a per-silicon vendor-extension hook.
+
+Standard part (no vendor data): Port_Cfg.h switches and PortConf_PortPin_* symbols, Port tables
+(pin direction / initial mode / level / allowed modes bitmask / changeable flags) in the file of
+their config class; Dio_Cfg.h with DioConf_DioPort_* / DioConf_DioChannel_* / DioConf_DioChannelGroup_*
+symbols and the Dio_ChannelGroupType objects the group symbols point to (SWS_Dio_00184: mask,
+offset, port; ECUC_Dio_00149: the symbol is the address expression).
+
+Vendor hook: `.hydron/autosar.json` {"codegen": {"mcal": {"silicon": "tc4d", "pinMap": "mcal/pins.json"}}}
+loads codegen/mcal/<silicon>.json (or a project file) that maps the standard pin attributes to
+register fields, and a project pin map {"<PortPin SHORT-NAME>": {"port": "P00", "pin": 5,
+"modes": {"PORT_PIN_MODE_CAN": 2}, "fields": {"PD": 0}}}. With both, Port_PBcfg.c / Port_Cfg.c gets
+a register image (address, value) per pin. Missing data is reported, never guessed.
+"""
+from __future__ import annotations
+
+import json
+import os
+import re
+
+from .. import cwriter as W
+from ..model import CLASS_RANK
+from ..registry import Generator, register
+
+HERE = os.path.dirname(os.path.dirname(__file__))
+
+
+def _pins(spec: str) -> set:
+    out = set()
+    for part in str(spec).split(","):
+        a, _, b = part.strip().partition("-")
+        if a:
+            out.update(range(int(a), int(b or a) + 1))
+    return out
+
+
+def load_silicon(root: str, name: str) -> dict:
+    for f in (os.path.join(root, name), os.path.join(root, ".hydron", "codegen", "mcal", f"{name}.json"),
+              os.path.join(HERE, "mcal", f"{name}.json")):
+        if os.path.isfile(f):
+            with open(f) as fh:
+                return json.load(fh)
+    raise FileNotFoundError(f"no MCAL silicon mapping {name!r} (bundled: "
+                            f"{', '.join(sorted(x[:-5] for x in os.listdir(os.path.join(HERE, 'mcal'))))})")
+
+
+def register_image(sil: dict, pins: list, pin_map: dict) -> tuple:
+    """[(address, value, comment)], [missing-data notes] for Port pins (container, attrs)."""
+    regs = sil["registers"]
+    fields = sil["fields"]
+    rows, missing = [], []
+    for c, attrs in pins:
+        pm = pin_map.get(c.name)
+        if pm is None:
+            missing.append(f"{c.name}: not in the pin map (port/pin unknown)")
+            continue
+        port = sil["ports"].get(pm.get("port"))
+        if port is None:
+            missing.append(f"{c.name}: port {pm.get('port')!r} not in the {sil['silicon']} mapping")
+            continue
+        pin = int(pm.get("pin", -1))
+        if pin not in _pins(port.get("pins", "0-15")):
+            missing.append(f"{c.name}: {pm['port']}.{pin} is not an available port slice ({sil.get('portsCite', '')})")
+            continue
+        vals: dict = {}
+        d = sil.get("direction", {}).get(attrs.get("PortPinDirection"))
+        if d is None:
+            missing.append(f"{c.name}: no field mapping for direction {attrs.get('PortPinDirection')}")
+            continue
+        vals.update({k: v for k, v in d.items() if k != "cite"})
+        mode = attrs.get("PortPinInitialMode")
+        mv = (pm.get("modes") or {}).get(mode)
+        if mv is not None:
+            vals["MODE"] = int(mv)
+        elif mode in sil.get("modes", {}):
+            vals.update({k: v for k, v in sil["modes"][mode].items() if k != "cite"})
+        else:
+            missing.append(f"{c.name}: alternate-function number for {mode} on {pm['port']}.{pin} "
+                           "(per-pin, from the vendor VSMD / data sheet pin table)")
+            continue
+        for k, v in (pm.get("fields") or {}).items():
+            vals[k] = int(v)
+        level = sil.get("level", {}).get(attrs.get("PortPinLevelValue"), {})
+        if attrs.get("PortPinDirection") == "PORT_PIN_OUT":
+            vals.update(level)
+        by_reg: dict = {}
+        for k, v in vals.items():
+            f = fields.get(k)
+            if f is None:
+                missing.append(f"{c.name}: field {k} unknown in the {sil['silicon']} mapping")
+                continue
+            if v >> f["width"]:
+                missing.append(f"{c.name}: {k}={v} does not fit {f['width']} bit(s)")
+                continue
+            by_reg[f["reg"]] = by_reg.get(f["reg"], 0) | (int(v) << f["lsb"])
+        base = int(port["base"], 16)
+        # level request (GPIO) before the driver configuration (DRVCFG): no glitch when the output turns on
+        for reg in sorted(by_reg, key=lambda r: (r != "GPIO", r)):
+            r = regs[reg]
+            addr = base + int(r["offset"], 16) + pin * int(r["stride"], 16)
+            fl = ", ".join(f"{k}={v}" for k, v in sorted(vals.items()) if fields.get(k, {}).get("reg") == reg)
+            rows.append((addr, by_reg[reg], f"{c.name}: {pm['port']}.{pin} {reg} {fl}"))
+    return rows, missing
+
+
+@register("Port")
+class Port(Generator):
+    def specific(self, mo):
+        opts = (getattr(self.ctx, "options", {}) or {}).get("mcal") or {}
+        if not opts.get("silicon"):
+            return
+        root = self.cg.p.root
+        sil = load_silicon(root, opts["silicon"])
+        pin_map = {}
+        if opts.get("pinMap"):
+            pf = opts["pinMap"] if os.path.isabs(opts["pinMap"]) else os.path.join(root, opts["pinMap"])
+            with open(pf) as fh:
+                pin_map = json.load(fh)
+        pins = []
+        rank = 1
+        for c in self.cg.sorted_instances(self.mc, "PortPin"):
+            attrs = {n: c.text(n) for n in ("PortPinDirection", "PortPinInitialMode", "PortPinLevelValue")}
+            pins.append((c, attrs))
+            for n in attrs:
+                rank = max(rank, self.cg.eff_class(self.mc, self.cg.param_def(c, n)))
+        rows, missing = register_image(sil, pins, pin_map)
+        mo.notes += [f"{sil['silicon']} ({sil.get('status', '')}): {m}" for m in missing]
+        if not rows:
+            mo.notes.append(f"{sil['silicon']}: no register image generated; needs vendor data: "
+                            + "; ".join(sil.get("needsVendorData", [])))
+            return
+        t = f"Port_Cfg{sil['silicon'].capitalize()}RegType"
+        mo.types.append("typedef struct {\n  uint32 Address;\n  uint32 Value;\n} " + t + ";")
+        cnt = f"PORT_CFG_NUM_{sil['silicon'].upper()}_REG_INIT"
+        mo.group(f"{sil['title']} ({sil.get('status')})", [(cnt, W.c_uint(len(rows)))])
+        decl = f"CONST({t}, PORT_CONST) Port_Cfg{sil['silicon'].capitalize()}RegInit[{cnt}]"
+        mo.hdecls.append(f"extern {decl};")
+        lines = [W.initializer([W.c_uint(a, True), W.c_uint(v, True)], cm) for a, v, cm in rows]
+        cites = "; ".join(f"{k}: {r['cite']}" for k, r in sil["registers"].items())
+        mo.table(rank, f"/* Register image from the {sil['silicon']} mapping ({cites}).\n"
+                       f" * {sil.get('statusNote', '')[:300]} */\n{decl} = {{\n" + ",\n".join(lines) + "\n};")
+
+
+@register("Dio")
+class Dio(Generator):
+    def specific(self, mo):
+        if "Dio.h" not in self.ctx.headers:
+            mo.notes.append("no Dio.h (static Dio code) in the project: Dio_ChannelGroupType objects not generated")
+            return
+        objs, decls = [], []
+        for g in self.cg.instances(self.mc, "DioChannelGroup"):
+            ident = (g.text("DioChannelGroupIdentification") or "").strip()
+            m = re.fullmatch(r"&\s*([A-Za-z_]\w*)", ident)
+            if not m:
+                mo.notes.append(f"{g.path}: DioChannelGroupIdentification {ident!r} is not '&<object>'; "
+                                "the Dio_ChannelGroupType object is not generated")
+                continue
+            port = g.parent.text("DioPortId") if g.parent is not None else None
+            vals = [W.c_uint(int(g.text("DioPortMask") or 0, 0), True), W.c_uint(int(g.text("DioPortOffset") or 0, 0)),
+                    W.c_uint(int(port or 0, 0))]
+            decls.append(f"extern CONST(Dio_ChannelGroupType, DIO_CONST) {m.group(1)};")
+            objs.append(f"CONST(Dio_ChannelGroupType, DIO_CONST) {m.group(1)} = {{ {', '.join(vals)} }}; "
+                        f"/* {g.name}: mask, offset, port (SWS_Dio_00184) */")
+        if objs:
+            mo.hdecls += ["/* Channel groups (ECUC_Dio_00149); Dio.h defines Dio_ChannelGroupType before including Dio_Cfg.h */",
+                          *decls]
+            rank = max(self.cg.eff_class(self.mc, self.cg.param_def(g, "DioPortMask"))
+                       for g in self.cg.instances(self.mc, "DioChannelGroup"))
+            mo.table(max(rank, CLASS_RANK["PRE-COMPILE"]), "\n".join(objs))
+            mo.include("Dio.h")

package/python/ecuc_engine/codegen/modules/memstack.py

@@ -0,0 +1,24 @@
+"""Memory stack: NvM, MemIf, Fee, Ea. Everything they need is expressible by the defs (block
+descriptors, symbolic block IDs/numbers, pre-compile switches), so they are plain registrations;
+the NvM block-descriptor layout of a given static NvM comes from its binding."""
+from ..registry import Generator, register
+
+
+@register("NvM")
+class NvM(Generator):
+    pass
+
+
+@register("MemIf")
+class MemIf(Generator):
+    pass
+
+
+@register("Fee")
+class Fee(Generator):
+    pass
+
+
+@register("Ea")
+class Ea(Generator):
+    pass

package/python/ecuc_engine/codegen/registry.py

@@ -0,0 +1,208 @@
+"""Generator registry. A module generator self-registers with @register("<ModuleDefName>").
+
+Any configured module can be emitted by the generic Generator (macros, symbols, tables straight
+from the param defs). A registered subclass adds only what the defs cannot express (and is what
+`autosar_codegen` runs by default). To add a module: drop a file in codegen/modules/ with a
+@register'ed subclass; modules/__init__.py imports every file in the folder.
+"""
+from __future__ import annotations
+
+import re
+from typing import Optional
+
+from . import binding as B
+from . import cwriter as W
+from . import emit as E
+
+GENERATORS: dict = {}
+
+
+def register(name: str):
+    def deco(cls):
+        cls.module = name
+        GENERATORS[name] = cls
+        return cls
+    return deco
+
+
+def generator_for(name: str):
+    from . import modules  # noqa: F401  (self-registration)
+    return GENERATORS.get(name, Generator)
+
+
+def registered() -> list:
+    from . import modules  # noqa: F401
+    return sorted(GENERATORS)
+
+
+class Generator:
+    module: Optional[str] = None
+    std_header = "Std_Types.h"
+
+    def __init__(self, ctx: E.Ctx, mc):
+        self.ctx = ctx
+        self.cg = ctx.cg
+        self.mc = mc
+
+    def run(self) -> E.ModuleOutput:
+        mo = E.ModuleOutput(self.ctx, self.mc)
+        mo.h_includes = [self.default_std_header()]
+        mb = B.select(self.ctx.bindings, self.mc.name, self.ctx.headers, self.ctx.binding_name)
+        mo.binding = mb
+        if mb and mb.get("headerIncludes"):
+            mo.h_includes = list(mb["headerIncludes"])
+        E.scalar_macros(self.cg, mo)
+        E.symbolic_names(self.cg, mo)
+        self.specific(mo)
+        if mb is None or mb.get("genericTables", False):
+            E.generic_tables(self.cg, mo, set(self.skip_tables(mo)))
+        if mb is not None:
+            try:
+                apply_binding(self.cg, mo, mb, self.path_steps(mo))
+            except B.BindingError as ex:
+                mo.errors.append(str(ex))
+        return mo
+
+    def path_steps(self, mo) -> dict:
+        """call:<name> resolvers for the binding path language: {name: fn(container, Eval) -> token | None}."""
+        return {}
+
+    def default_std_header(self) -> str:
+        """ComStack_Types.h for modules that reference EcuC PDUs (communication stack), else Std_Types.h."""
+        md = self.mc.defn
+        if md is not None:
+            for d in self.cg.defs.by_path.values():
+                if d.module == md.path and d.kind and "REFERENCE" in d.kind and any(
+                        r.endswith("/EcucPduCollection/Pdu") for r in d.dest_refs):
+                    return "ComStack_Types.h"
+        return self.std_header
+
+    def skip_tables(self, mo) -> list:
+        return []
+
+    def specific(self, mo: E.ModuleOutput):
+        """Module-specific emission (only what the param defs cannot express)."""
+
+
+def apply_binding(cg, mo: E.ModuleOutput, mb: dict, ext: Optional[dict] = None):
+    ev = B.Eval(cg, mo.mc, mo.ctx)
+    ev.ext = ext or {}
+    sets = mb.get("sets", {})
+    for req in mb.get("require", []):
+        bad = [r for r in ev.rows(req["rows"], sets) if not ev.matches(r, [req])]
+        if bad:
+            vals = sorted({str(ev.raw(r, req["path"])) for r in bad})
+            mo.errors.append(f"{len(bad)} {req['rows']} container(s) have {req['path']} = {', '.join(vals)} "
+                             f"({', '.join(r.name for r in bad[:5])}{', ...' if len(bad) > 5 else ''}); the "
+                             f"{mb['_binding']} static code supports only "
+                             f"{', '.join('(not configured)' if x is None else str(x) for x in req['in'])}: {req.get('why', '')}")
+    for un in mb.get("unsupported", []):
+        rows = cg.instances(mo.mc, un["rows"])
+        if rows:
+            mo.errors.append(f"{len(rows)} {un['rows']} container(s) configured ({', '.join(r.name for r in rows[:5])}"
+                             f"{', ...' if len(rows) > 5 else ''}), which the {mb['_binding']} static code cannot "
+                             f"represent: {un.get('why', '')}")
+    for inc in mb.get("sourceIncludes", []):
+        mo.include(inc)
+    macros = []
+    values: dict = {}
+    for m in mb.get("macros", []):
+        val = m["value"]
+        v = ev.macro(val, sets) if re.match(r"^(count|max):", val) else val
+        macros.append((m["name"], v))
+        values[m["name"]] = v
+    mo.group(f"Static-code interface ({mb['_binding']} binding)", macros)
+    pending: list = []
+    for vs in mb.get("vars", []):
+        ev.rank = 1
+        lines = []
+        for r in ev.rows(vs["rows"], sets):
+            size, _ = ev.field(r, {"name": vs["name"], "path": vs["size"]})
+            name = vs["name"].replace("{}", r.name)
+            lines.append(f"{'static ' if vs.get('static') else ''}VAR({vs['type']}, {vs['qualifier']}) {name}[{size}];")
+        pending.append(("var", ev.rank, vs.get("section", "VAR_NOINIT_UNSPECIFIED"), "\n".join(lines)))
+    for t in mb.get("tables", []):
+        ev.rank = 1
+        rows = ev.rows(t["rows"], sets)
+        if t.get("order"):
+            from ..values import parse_int
+            rows.sort(key=lambda r: (parse_int(r.text(t["order"]) or "") is None, parse_int(r.text(t["order"]) or "") or 0))
+        lines, externs = [], []
+        des = t.get("designated")
+        if des:
+            _check_index(cg, mo, t, rows, des, values)
+        for r in rows:
+            vals = []
+            for f in t["fields"]:
+                v, _ = ev.field(r, f)
+                vals.append(v)
+                if f.get("extern") and v not in ("NULL_PTR", "0", "0u") and not v.startswith('"'):
+                    m = re.search(r"[A-Za-z_]\w*", v)
+                    if m:
+                        ext_ = "extern " + f["extern"].replace("{}", m.group(0)) + ";"
+                        if ext_ not in externs:
+                            externs.append(ext_)
+            lead = ""
+            if des:
+                lead = f"[{des.replace('{sym}', cg.symbol(r)) if isinstance(des, str) else cg.symbol(r)}] = "
+            comment = t.get("comment", "name")
+            cm = {"name": r.name, "sym": cg.symbol(r) or r.name}.get(comment, r.name)
+            if t.get("scalar"):
+                lines.append(f"  {lead}{vals[0]} /* {cm} */")
+            else:
+                lines.append(f"  {lead}{{ {', '.join(vals)} }} /* {cm} */")
+        st = "static " if t.get("static") else ""
+        size = t.get("size", "")
+        body = (f"/* {t.get('doc', t['rows'])} */\n{st}CONST({t['type']}, {t['qualifier']}) {t['name']}[{size}] = {{\n" +
+                ",\n".join(lines) + "\n};")
+        pending.append(("table", ev.rank, body, externs))
+    objects = mb.get("objects", [])
+    if objects:
+        # a root config object points at the (static) tables and buffers, so they all live in its file:
+        # the most dynamic config class among them (e.g. <Mip>_PBcfg.c for a post-build PduR_Config)
+        top = max([p[1] for p in pending] + [1])
+        pending = [(p[0], top) + p[2:] for p in pending]
+        for o in objects:
+            body = (f"CONST({o['type']}, {o['qualifier']}) {o['name']} = {{\n  " + ", ".join(o["init"]) + "\n};")
+            pending.append(("table", top, body, []))
+    for p in pending:
+        if p[0] == "var":
+            mo.var(p[1], p[2], p[3])
+        else:
+            mo.table(p[1], p[2], p[3])
+    mo.used_mips |= ev.used_mips
+
+
+def _check_index(cg, mo, t: dict, rows: list, des, values: dict):
+    """A designated table is indexed by handle (minus an offset): every row must land in [0, size) exactly once,
+    or the static code's table lookup would be wrong. Reported as an error, never renumbered here."""
+    from ..values import parse_int
+    off_name = None
+    if isinstance(des, str):
+        m = re.fullmatch(r"\{sym\}\s*-\s*(\w+)", des.strip())
+        if not m:
+            return
+        off_name = m.group(1)
+    num = lambda v: parse_int(re.sub(r"[uUlL]+$", "", str(v)))  # noqa: E731
+    off = num(values.get(off_name, "0")) if off_name else 0
+    size = num(values[t["size"]]) if t.get("size") in values else len(rows)
+    seen: dict = {}
+    bad = 0
+    for r in rows:
+        h = parse_int(cg.symbol_value(r) or "")
+        if h is None:
+            continue
+        i = h - (off or 0)
+        if not 0 <= i < (size or 0) or i in seen:
+            bad += 1
+            if bad > 5:
+                continue
+            pm = cg.symbolic_param(r)
+            mo.errors.append(f"{r.path}: {pm.name if pm else 'handle'}={h} does not fit the static code's "
+                             f"{t['name']}[{t.get('size')}] indexed by {des if isinstance(des, str) else '{sym}'} "
+                             f"({'collides with ' + seen[i] if i in seen else f'index {i} outside 0..{(size or 0) - 1}'}); "
+                             f"the {t['rows']} handles must be contiguous in the order the static code expects")
+            continue
+        seen[i] = r.name
+    if bad > 5:
+        mo.errors.append(f"... {bad - 5} more {t['rows']} handle(s) outside {t['name']}")

package/python/ecuc_engine/codegen/schm_memmap.py

@@ -0,0 +1,159 @@
+"""SchM_<Mip>.h and <Mip>_MemMap.h (+ an aggregating MemMap.h when the project has none).
+
+SchM_<Mip>.h (SWS_Rte BSW scheduler part): exclusive-area enter/exit macros and the module's main
+function prototypes.
+  * Exclusive areas: the ones the module's static code actually uses (`SchM_Enter_<Mip>_<EA>` found
+    in the project's non-generated C), plus any configured for the module in the Rte ECUC.
+    Mechanism per RteExclusiveAreaImplMechanism when configured (RteBswExclusiveAreaImpl), else
+    ALL_INTERRUPT_BLOCKING (OS SuspendAllInterrupts/ResumeAllInterrupts).
+  * Main functions: <Mip>_MainFunction for a `...MainFunctionPeriod` parameter, and one per instance
+    of a `<Mip>MainFunction<X>` container (Com-style named main functions).
+<Mip>_MemMap.h: SWS_MemMap_00032 file name, keyword evaluation and START/STOP sequence checks in the
+shape of the SWS_MemMap example (chapter A.3); pragmas are left to the project's MemMapAllocation
+(`.hydron/autosar.json` codegen.memmap.pragmas), so the default build is compiler-neutral.
+"""
+from __future__ import annotations
+
+import re
+
+from . import cwriter as W
+
+DEFAULT_SECTIONS = ["CODE", "CONST_UNSPECIFIED", "CONFIG_DATA_UNSPECIFIED", "VAR_INIT_UNSPECIFIED",
+                    "VAR_NOINIT_UNSPECIFIED", "VAR_CLEARED_UNSPECIFIED"]
+
+MECHANISMS = {
+    "ALL_INTERRUPT_BLOCKING": ("SuspendAllInterrupts()", "ResumeAllInterrupts()"),
+    "OS_INTERRUPT_BLOCKING": ("SuspendOSInterrupts()", "ResumeOSInterrupts()"),
+}
+
+
+def _scan(ctx, rx) -> dict:
+    hits: dict = {}
+    for f in ctx.sources:
+        try:
+            with open(f, errors="replace") as fh:
+                text = fh.read()
+        except OSError:
+            continue
+        for m in rx.finditer(text):
+            hits.setdefault(m.group(1), set()).add(ctx.cg.p.rel(f))
+    return hits
+
+
+def _ea_mechanisms(cg) -> dict:
+    """EA short name -> (mechanism, os resource) from the Rte ECUC, when configured."""
+    out = {}
+    rte = cg.module("Rte")
+    if rte is None:
+        return out
+    for c in rte.containers:
+        if c.def_name != "RteBswExclusiveAreaImpl":
+            continue
+        ref = c.text("RteBswExclusiveAreaRef") or ""
+        mech = c.text("RteExclusiveAreaImplMechanism") or "ALL_INTERRUPT_BLOCKING"
+        res = (c.text("RteBswExclusiveAreaOsResourceRef") or "").rsplit("/", 1)[-1]
+        if ref:
+            out[ref.rsplit("/", 1)[-1]] = (mech, res)
+    return out
+
+
+def main_functions(cg, mo) -> list:
+    mc = mo.mc
+    out = list(getattr(mo, "main_functions", []))
+    for c in mc.containers:
+        if c.defn is None:
+            continue
+        m = re.match(rf"^{re.escape(mc.name)}MainFunction(\w*)$", c.def_name)
+        if m:
+            suffix = m.group(1)
+            fn = f"{mo.mip}_MainFunction{suffix}" + ("" if c.name == c.def_name else f"_{c.name}")
+            if fn not in out:
+                out.append(fn)
+            continue
+        if cg.is_multi(c):
+            continue
+        for p in c.defn.params:
+            if p.endswith("MainFunctionPeriod") and c.text(p.rsplit("/", 1)[-1]) is not None:
+                fn = f"{mo.mip}_MainFunction"
+                if fn not in out:
+                    out.append(fn)
+    return out
+
+
+def schm_header(ctx, mo) -> tuple:
+    mip, MIP = mo.mip, mo.MIP
+    eas = _scan(ctx, re.compile(rf"\bSchM_(?:Enter|Exit)_{re.escape(mip)}_(\w+)\s*\("))
+    mech = _ea_mechanisms(ctx.cg)
+    for ea in mech:
+        if ea.upper().startswith(MIP + "_") and ea not in eas:
+            eas[ea] = {"Rte ECUC"}
+    mfs = main_functions(ctx.cg, mo)
+    name = f"SchM_{mip}.h"
+    g = W.guard(name)
+    lines = [mo._banner(name), "", f"#ifndef {g}", f"#define {g}", "", '#include "Std_Types.h"']
+    if eas:
+        lines.append('#include "Os.h"')
+    if eas:
+        lines += ["", "/* Exclusive areas (SWS_Rte SchM_Enter/SchM_Exit); used in: "
+                  + ", ".join(sorted({f for s in eas.values() for f in s})) + " */"]
+        for ea in sorted(eas):
+            m, res = mech.get(ea, ("ALL_INTERRUPT_BLOCKING", ""))
+            if m == "OS_RESOURCE" and res:
+                enter, exit_ = f"(void)GetResource({res})", f"(void)ReleaseResource({res})"
+            else:
+                enter, exit_ = MECHANISMS.get(m, ("do { } while (0)", "do { } while (0)"))
+            lines += [W.define(f"SchM_Enter_{mip}_{ea}()", enter, m), W.define(f"SchM_Exit_{mip}_{ea}()", exit_)]
+    if mfs:
+        lines += ["", "/* Main functions called by the BSW scheduler */"]
+        lines += [f"extern FUNC(void, {MIP}_CODE) {fn}(void);" for fn in mfs]
+    lines += ["", f"#endif /* {g} */", ""]
+    return name, "\n".join(lines)
+
+
+def module_memmap(ctx, mo, pragmas: dict) -> tuple:
+    mip, MIP = mo.mip, mo.MIP
+    used = _scan(ctx, re.compile(rf"\b{re.escape(MIP)}_START_SEC_(\w+)"))
+    sections = list(DEFAULT_SECTIONS) + sorted(s for s in used if s not in DEFAULT_SECTIONS)
+    name = f"{mip}_MemMap.h"
+    lines = [mo._banner(name),
+             "/* Memory mapping of the module's sections (SWS_MemMap_00032). No include guard: it is included",
+             " * once per section switch. Pragmas come from codegen.memmap.pragmas (MemMapAllocation); none by default. */",
+             "", "#define MEMMAP_ERROR", ""]
+    for i, sec in enumerate(sections):
+        kw = f"{MIP}_SEC_{sec}"
+        start = pragmas.get(sec, {}).get("start", "") if isinstance(pragmas.get(sec), dict) else ""
+        stop = pragmas.get(sec, {}).get("stop", "") if isinstance(pragmas.get(sec), dict) else ""
+        lines += [
+            f"{'#if' if i == 0 else '#elif'} defined({MIP}_START_SEC_{sec})",
+            f"  #undef {MIP}_START_SEC_{sec}",
+            "  #undef MEMMAP_ERROR",
+            f"  #ifdef {MIP}_MEMMAP_SEQUENCE_OPEN",
+            f'    #error "{name}: {kw}: STOP the open section before starting a new one"',
+            "  #endif",
+            f"  #define {MIP}_MEMMAP_SEQUENCE_OPEN",
+            *( [f"  {start}"] if start else []),
+            f"#elif defined({MIP}_STOP_SEC_{sec})",
+            f"  #undef {MIP}_STOP_SEC_{sec}",
+            "  #undef MEMMAP_ERROR",
+            f"  #ifndef {MIP}_MEMMAP_SEQUENCE_OPEN",
+            f'    #error "{name}: {kw}: STOP without START"',
+            "  #endif",
+            f"  #undef {MIP}_MEMMAP_SEQUENCE_OPEN",
+            *( [f"  {stop}"] if stop else []),
+        ]
+    lines += ["#endif", "", "#if defined(MEMMAP_ERROR)", f'  #error "{name}: unknown memory section"', "#endif", ""]
+    return name, "\n".join(lines), sections
+
+
+def aggregate_memmap(ctx, entries: list) -> str:
+    """Legacy MemMap.h dispatching to the per-module files (only emitted when the project has none)."""
+    lines = [W.banner("MemMap.h", "MemMap", "-", ctx.release, [], "-"),
+             "/* Dispatches each <MIP>_START_SEC_/<MIP>_STOP_SEC_ keyword to <Mip>_MemMap.h. No include guard. */", ""]
+    first = True
+    for mip, sections in entries:
+        MIP = mip.upper()
+        cond = " || \\\n    ".join(f"defined({MIP}_{k}_SEC_{s})" for s in sections for k in ("START", "STOP"))
+        lines += [f"{'#if' if first else '#elif'} {cond}", f'  #include "{mip}_MemMap.h"']
+        first = False
+    lines += ["#else", '  #error "MemMap.h: unknown memory section"', "#endif", ""]
+    return "\n".join(lines)