@h2loop/autosar 0.1.2 → 1.1.0

package/python/ecuc_engine/codegen/model.py

@@ -0,0 +1,259 @@
+"""Generator view of the ECUC model: merged containers, effective config classes, refs, symbols.
+
+Everything here is derived from the engine's loader (`model.Project`) and the param defs
+(`defs.DefIndex`); nothing is module-specific. Container order is document order (files sorted by
+path, elements in file order), so every table built from it is deterministic.
+"""
+from __future__ import annotations
+
+import re
+from dataclasses import dataclass, field
+from typing import Iterable, Optional
+
+from .. import defs as D
+from ..model import Elem, ParamVal, Project
+from ..values import parse_float, parse_int
+
+CLASS_RANK = {"PUBLISHED-INFORMATION": 0, "PRE-COMPILE": 1, "LINK": 2, "POST-BUILD": 3}
+CLASS_FILE = {0: "Cfg.c", 1: "Cfg.c", 2: "Lcfg.c", 3: "PBcfg.c"}
+DEFAULT_VARIANT = "VARIANT-PRE-COMPILE"
+
+# AUTOSAR_CP_TR_ReleaseOverview R25-11, Table 1.2 "Mapping schema version to platform releases"
+# (and Table 1.1 for the R4.x schemas): schema AUTOSAR_000NN -> internal release number.
+SCHEMA_RELEASE = {
+    "00042": (4, 3, 0), "00043": (4, 3, 0), "00044": (4, 3, 1), "00045": (4, 3, 1), "00046": (4, 4, 0),
+    "00047": (4, 4, 0), "00048": (4, 5, 0), "00049": (4, 6, 0), "00050": (4, 7, 0), "00051": (4, 8, 0),
+    "00052": (4, 9, 0), "00053": (4, 10, 0), "00054": (4, 11, 0),
+}
+
+
+def snake(name: str) -> str:
+    """CamelCase -> UPPER_SNAKE (NvMDevErrorDetect -> NVM_DEV_ERROR_DETECT)."""
+    s = re.sub(r"(?<=[a-z0-9])(?=[A-Z])|(?<=[A-Z])(?=[A-Z][a-z])", "_", name)
+    return re.sub(r"_+", "_", s).upper()
+
+
+@dataclass
+class Container:
+    """One container value, merged across file splits (all fragments with the same AUTOSAR path)."""
+    path: str
+    name: str
+    defn: Optional[D.DefNode]
+    frags: list
+    module: "ModuleCfg"
+    parent: Optional["Container"] = None
+    children: list = field(default_factory=list)
+
+    @property
+    def def_name(self) -> str:
+        return self.defn.name if self.defn else (self.frags[0].def_ref or "?").rsplit("/", 1)[-1]
+
+    def values(self, name: str) -> list:
+        return [pv for f in self.frags for pv in f.params if pv.name == name]
+
+    def value(self, name: str) -> Optional[ParamVal]:
+        v = self.values(name)
+        return v[0] if v else None
+
+    def text(self, name: str) -> Optional[str]:
+        v = self.value(name)
+        return v.value if v is not None else None
+
+    def sub(self, def_name: str) -> list:
+        return [c for c in self.children if c.def_name == def_name]
+
+
+@dataclass
+class ModuleCfg:
+    name: str  # def short name (the Mip unless overridden)
+    elem: Elem
+    defn: Optional[D.DefNode]
+    variant: str
+    containers: list  # all Containers, document order (pre-order)
+    top: list  # top-level Containers
+    mip: str = ""
+
+    @property
+    def MIP(self) -> str:
+        return self.mip.upper()
+
+
+class CgModel:
+    def __init__(self, project: Project, mip_overrides: Optional[dict] = None):
+        self.p = project
+        self.defs = project.defs
+        self.mip_overrides = mip_overrides or {}
+        self.modules: dict[str, ModuleCfg] = {}
+        self.by_path: dict[str, Container] = {}
+        self.order: dict[str, int] = {}
+        self._rev: Optional[dict] = None
+        self._sorted: dict = {}
+        for m in sorted(project.modules, key=lambda e: (e.file, e.line)):
+            self._add_module(m)
+
+    # ---------- construction ----------
+    def _def(self, def_ref: Optional[str]) -> Optional[D.DefNode]:
+        if not def_ref:
+            return None
+        d = self.defs.get(def_ref)
+        if d is not None:
+            return d
+        # vendor-relocated or other-release DEFINITION-REF: match by module-relative path
+        rel = self.defs.rel(def_ref)
+        for mp, md in self.defs.modules.items():
+            if rel.split("/", 1)[0] == md.name:
+                return self.defs.get(mp + rel[len(md.name):])
+        return None
+
+    def _add_module(self, m: Elem):
+        md = self._def(m.def_ref)
+        name = md.name if md else (m.def_ref or m.name).rsplit("/", 1)[-1]
+        if name in self.modules:  # split module configuration: merge into the first one
+            mc = self.modules[name]
+        else:
+            variant = m.node.child_text("IMPLEMENTATION-CONFIG-VARIANT") or DEFAULT_VARIANT
+            mc = ModuleCfg(name, m, md, variant, [], [], self.mip_overrides.get(name, name))
+            self.modules[name] = mc
+        for c in m.children:
+            self._add_container(mc, c, None)
+
+    def _add_container(self, mc: ModuleCfg, e: Elem, parent: Optional[Container]):
+        c = self.by_path.get(e.path)
+        if c is None:
+            c = Container(e.path, e.name, self._def(e.def_ref), [], mc, parent)
+            self.by_path[e.path] = c
+            self.order[e.path] = len(self.order)
+            mc.containers.append(c)
+            (parent.children if parent else mc.top).append(c)
+        c.frags.append(e)
+        for ch in e.children:
+            self._add_container(mc, ch, c)
+
+    # ---------- queries ----------
+    def by_path_index(self, c: Container) -> int:
+        return self.order.get(c.path, 0)
+
+    def module(self, name: str) -> Optional[ModuleCfg]:
+        return self.modules.get(name)
+
+    def instances(self, mc: ModuleCfg, def_name: str) -> list:
+        return [c for c in mc.containers if c.def_name == def_name]
+
+    def target(self, pv: Optional[ParamVal]) -> Optional[Container]:
+        if pv is None or not pv.value:
+            return None
+        return self.by_path.get(pv.value.strip())
+
+    def reverse(self) -> dict:
+        """target path -> [(Container, ref name)] for every ECUC reference value, document order."""
+        if self._rev is None:
+            self._rev = {}
+            for mc in self.modules.values():
+                for c in mc.containers:
+                    for f in c.frags:
+                        for pv in f.params:
+                            if pv.is_ref and pv.value:
+                                self._rev.setdefault(pv.value.strip(), []).append((c, pv.name))
+        return self._rev
+
+    def referrers(self, target: Container, module: Optional[str] = None, ref: Optional[str] = None) -> list:
+        out = []
+        for c, rname in self.reverse().get(target.path, []):
+            if module is not None and c.module.name != module:
+                continue
+            if ref is not None and rname != ref:
+                continue
+            out.append(c)
+        return out
+
+    def param_def(self, c: Container, name: str) -> Optional[D.DefNode]:
+        if c.defn is None:
+            return None
+        for p in c.defn.params + c.defn.refs:
+            if p.rsplit("/", 1)[-1] == name:
+                return self.defs.get(p)
+        return None
+
+    def eff_class(self, mc: ModuleCfg, d: Optional[D.DefNode]) -> int:
+        """Effective config class rank of a param/ref (or container multiplicity) for the module's variant."""
+        if d is None:
+            return CLASS_RANK["PRE-COMPILE"]
+        cc = d.config_classes or d.mult_classes
+        if not cc:
+            return CLASS_RANK["PRE-COMPILE"]
+        cls = cc.get(mc.variant)
+        if cls is None:  # variant not listed for this param: take the least dynamic class it supports
+            cls = min(cc.values(), key=lambda k: CLASS_RANK.get(k, 1))
+        return CLASS_RANK.get(cls, 1)
+
+    def symbolic_param(self, c: Container) -> Optional[D.DefNode]:
+        if c.defn is None:
+            return None
+        for p in c.defn.params:
+            d = self.defs.get(p)
+            if d is not None and d.symbolic_name:
+                return d
+        return None
+
+    def symbol(self, c: Container) -> Optional[str]:
+        """TPS_ECUC_02108: <Mip>Conf_<ContainerDefShortName>_<ContainerValueShortName>."""
+        if self.symbolic_param(c) is None:
+            return None
+        return f"{c.module.mip}Conf_{c.def_name}_{c.name}"
+
+    def symbol_value(self, c: Container) -> Optional[str]:
+        d = self.symbolic_param(c)
+        return c.text(d.name) if d is not None else None
+
+    def sorted_instances(self, mc: ModuleCfg, def_name: str) -> list:
+        """Instances of a container def, ordered by their symbolic handle when they have one, else document order."""
+        key = (mc.name, def_name)
+        if key not in self._sorted:
+            insts = self.instances(mc, def_name)
+            if insts and self.symbolic_param(insts[0]) is not None:
+                def k(c):
+                    v = parse_int(self.symbol_value(c) or "")
+                    return (v is None, v if v is not None else 0)
+                insts = sorted(insts, key=k)  # stable: ties stay in document order
+            self._sorted[key] = insts
+        return self._sorted[key]
+
+    def index_of(self, c: Container) -> int:
+        return self.sorted_instances(c.module, c.def_name).index(c)
+
+    def is_multi(self, c: Container) -> bool:
+        """True if this container, or any ancestor, is an instance of a def with upper multiplicity > 1."""
+        x: Optional[Container] = c
+        while x is not None:
+            if x.defn is None or x.defn.upper != 1:
+                return True
+            x = x.parent
+        return False
+
+    def release(self) -> tuple:
+        """AUTOSAR release of the configuration, from the schema version of its files."""
+        for f in sorted(self.p.files):
+            head = self.p.files[f].data[:2048]
+            m = re.search(rb"AUTOSAR_(\d{5})\.xsd", head)
+            if m and m.group(1).decode() in SCHEMA_RELEASE:
+                return SCHEMA_RELEASE[m.group(1).decode()]
+        return (4, 11, 0)
+
+    def rel_files(self, mc: ModuleCfg) -> list:
+        files = sorted({f.file for c in mc.containers for f in c.frags} | {mc.elem.file})
+        return [self.p.rel(f).replace("\\", "/") for f in files]
+
+
+def num(v: Optional[str]) -> Optional[int]:
+    return parse_int(v) if v is not None else None
+
+
+def flt(v: Optional[str]) -> Optional[float]:
+    return parse_float(v) if v is not None else None
+
+
+def iter_param_defs(defs: D.DefIndex, d: D.DefNode) -> Iterable[D.DefNode]:
+    for p in d.params + d.refs:
+        x = defs.get(p)
+        if x is not None:
+            yield x

package/python/ecuc_engine/codegen/modules/__init__.py

@@ -0,0 +1,7 @@
+"""Module generators. Every .py file here registers itself with @register("<ModuleDefName>")."""
+import importlib
+import os
+
+for _f in sorted(os.listdir(os.path.dirname(__file__))):
+    if _f.endswith(".py") and _f != "__init__.py":
+        importlib.import_module(f"{__name__}.{_f[:-3]}")

package/python/ecuc_engine/codegen/modules/comstack.py

@@ -0,0 +1,14 @@
+"""PduR and CanIf. Handle IDs, routing and PDU tables are def-driven; the neighbour handles
+(PduR -> CanIf/Com, CanIf -> PduR) are found through the shared EcucPduCollection/Pdu
+(TPS_ECUC 3.4.1.3) by the binding path language (`peer:`). ComStack_Types.h is the base header."""
+from ..registry import Generator, register
+
+
+@register("PduR")
+class PduR(Generator):
+    std_header = "ComStack_Types.h"
+
+
+@register("CanIf")
+class CanIf(Generator):
+    std_header = "ComStack_Types.h"

package/python/ecuc_engine/codegen/modules/dem.py

@@ -0,0 +1,22 @@
+"""Dem: event IDs and the other symbolic IDs are generic (TPS_ECUC_02108). Module-specific:
+  * the DTC value of every DemDTC as DEM_DTC_<NAME> (DemDtcValue is not a symbolicNameValue param,
+    so TPS_ECUC_02108 does not name it; this generator's convention, <MIP>_<SN> per SWS_BSW_00124);
+  * Dem_MainFunction, scheduled with DemGeneral/DemTaskTime (ECUC_Dem_00715)."""
+from .. import cwriter as W
+from ..model import snake
+from ..registry import Generator, register
+from ...values import parse_int
+
+
+@register("Dem")
+class Dem(Generator):
+    def specific(self, mo):
+        lines = []
+        for c in self.cg.instances(self.mc, "DemDTC"):
+            v = parse_int(c.text("DemDtcValue") or "")
+            if v is not None:
+                lines.append((f"DEM_DTC_{snake(c.name)}", W.c_uint(v, hexa=True), "DemDtcValue"))
+        mo.group("DTC values (DemDTC/DemDtcValue)", lines)
+        gen = [c for c in self.mc.containers if c.def_name == "DemGeneral"]
+        if gen and gen[0].text("DemTaskTime") is not None:
+            mo.main_functions = ["Dem_MainFunction"]

package/python/ecuc_engine/codegen/modules/mcal.py

@@ -0,0 +1,170 @@
+"""Port and Dio from the STANDARD R25-11 param defs, plus a per-silicon vendor-extension hook.
+
+Standard part (no vendor data): Port_Cfg.h switches and PortConf_PortPin_* symbols, Port tables
+(pin direction / initial mode / level / allowed modes bitmask / changeable flags) in the file of
+their config class; Dio_Cfg.h with DioConf_DioPort_* / DioConf_DioChannel_* / DioConf_DioChannelGroup_*
+symbols and the Dio_ChannelGroupType objects the group symbols point to (SWS_Dio_00184: mask,
+offset, port; ECUC_Dio_00149: the symbol is the address expression).
+
+Vendor hook: `.hydron/autosar.json` {"codegen": {"mcal": {"silicon": "tc4d", "pinMap": "mcal/pins.json"}}}
+loads codegen/mcal/<silicon>.json (or a project file) that maps the standard pin attributes to
+register fields, and a project pin map {"<PortPin SHORT-NAME>": {"port": "P00", "pin": 5,
+"modes": {"PORT_PIN_MODE_CAN": 2}, "fields": {"PD": 0}}}. With both, Port_PBcfg.c / Port_Cfg.c gets
+a register image (address, value) per pin. Missing data is reported, never guessed.
+"""
+from __future__ import annotations
+
+import json
+import os
+import re
+
+from .. import cwriter as W
+from ..model import CLASS_RANK
+from ..registry import Generator, register
+
+HERE = os.path.dirname(os.path.dirname(__file__))
+
+
+def _pins(spec: str) -> set:
+    out = set()
+    for part in str(spec).split(","):
+        a, _, b = part.strip().partition("-")
+        if a:
+            out.update(range(int(a), int(b or a) + 1))
+    return out
+
+
+def load_silicon(root: str, name: str) -> dict:
+    for f in (os.path.join(root, name), os.path.join(root, ".hydron", "codegen", "mcal", f"{name}.json"),
+              os.path.join(HERE, "mcal", f"{name}.json")):
+        if os.path.isfile(f):
+            with open(f) as fh:
+                return json.load(fh)
+    raise FileNotFoundError(f"no MCAL silicon mapping {name!r} (bundled: "
+                            f"{', '.join(sorted(x[:-5] for x in os.listdir(os.path.join(HERE, 'mcal'))))})")
+
+
+def register_image(sil: dict, pins: list, pin_map: dict) -> tuple:
+    """[(address, value, comment)], [missing-data notes] for Port pins (container, attrs)."""
+    regs = sil["registers"]
+    fields = sil["fields"]
+    rows, missing = [], []
+    for c, attrs in pins:
+        pm = pin_map.get(c.name)
+        if pm is None:
+            missing.append(f"{c.name}: not in the pin map (port/pin unknown)")
+            continue
+        port = sil["ports"].get(pm.get("port"))
+        if port is None:
+            missing.append(f"{c.name}: port {pm.get('port')!r} not in the {sil['silicon']} mapping")
+            continue
+        pin = int(pm.get("pin", -1))
+        if pin not in _pins(port.get("pins", "0-15")):
+            missing.append(f"{c.name}: {pm['port']}.{pin} is not an available port slice ({sil.get('portsCite', '')})")
+            continue
+        vals: dict = {}
+        d = sil.get("direction", {}).get(attrs.get("PortPinDirection"))
+        if d is None:
+            missing.append(f"{c.name}: no field mapping for direction {attrs.get('PortPinDirection')}")
+            continue
+        vals.update({k: v for k, v in d.items() if k != "cite"})
+        mode = attrs.get("PortPinInitialMode")
+        mv = (pm.get("modes") or {}).get(mode)
+        if mv is not None:
+            vals["MODE"] = int(mv)
+        elif mode in sil.get("modes", {}):
+            vals.update({k: v for k, v in sil["modes"][mode].items() if k != "cite"})
+        else:
+            missing.append(f"{c.name}: alternate-function number for {mode} on {pm['port']}.{pin} "
+                           "(per-pin, from the vendor VSMD / data sheet pin table)")
+            continue
+        for k, v in (pm.get("fields") or {}).items():
+            vals[k] = int(v)
+        level = sil.get("level", {}).get(attrs.get("PortPinLevelValue"), {})
+        if attrs.get("PortPinDirection") == "PORT_PIN_OUT":
+            vals.update(level)
+        by_reg: dict = {}
+        for k, v in vals.items():
+            f = fields.get(k)
+            if f is None:
+                missing.append(f"{c.name}: field {k} unknown in the {sil['silicon']} mapping")
+                continue
+            if v >> f["width"]:
+                missing.append(f"{c.name}: {k}={v} does not fit {f['width']} bit(s)")
+                continue
+            by_reg[f["reg"]] = by_reg.get(f["reg"], 0) | (int(v) << f["lsb"])
+        base = int(port["base"], 16)
+        # level request (GPIO) before the driver configuration (DRVCFG): no glitch when the output turns on
+        for reg in sorted(by_reg, key=lambda r: (r != "GPIO", r)):
+            r = regs[reg]
+            addr = base + int(r["offset"], 16) + pin * int(r["stride"], 16)
+            fl = ", ".join(f"{k}={v}" for k, v in sorted(vals.items()) if fields.get(k, {}).get("reg") == reg)
+            rows.append((addr, by_reg[reg], f"{c.name}: {pm['port']}.{pin} {reg} {fl}"))
+    return rows, missing
+
+
+@register("Port")
+class Port(Generator):
+    def specific(self, mo):
+        opts = (getattr(self.ctx, "options", {}) or {}).get("mcal") or {}
+        if not opts.get("silicon"):
+            return
+        root = self.cg.p.root
+        sil = load_silicon(root, opts["silicon"])
+        pin_map = {}
+        if opts.get("pinMap"):
+            pf = opts["pinMap"] if os.path.isabs(opts["pinMap"]) else os.path.join(root, opts["pinMap"])
+            with open(pf) as fh:
+                pin_map = json.load(fh)
+        pins = []
+        rank = 1
+        for c in self.cg.sorted_instances(self.mc, "PortPin"):
+            attrs = {n: c.text(n) for n in ("PortPinDirection", "PortPinInitialMode", "PortPinLevelValue")}
+            pins.append((c, attrs))
+            for n in attrs:
+                rank = max(rank, self.cg.eff_class(self.mc, self.cg.param_def(c, n)))
+        rows, missing = register_image(sil, pins, pin_map)
+        mo.notes += [f"{sil['silicon']} ({sil.get('status', '')}): {m}" for m in missing]
+        if not rows:
+            mo.notes.append(f"{sil['silicon']}: no register image generated; needs vendor data: "
+                            + "; ".join(sil.get("needsVendorData", [])))
+            return
+        t = f"Port_Cfg{sil['silicon'].capitalize()}RegType"
+        mo.types.append("typedef struct {\n  uint32 Address;\n  uint32 Value;\n} " + t + ";")
+        cnt = f"PORT_CFG_NUM_{sil['silicon'].upper()}_REG_INIT"
+        mo.group(f"{sil['title']} ({sil.get('status')})", [(cnt, W.c_uint(len(rows)))])
+        decl = f"CONST({t}, PORT_CONST) Port_Cfg{sil['silicon'].capitalize()}RegInit[{cnt}]"
+        mo.hdecls.append(f"extern {decl};")
+        lines = [W.initializer([W.c_uint(a, True), W.c_uint(v, True)], cm) for a, v, cm in rows]
+        cites = "; ".join(f"{k}: {r['cite']}" for k, r in sil["registers"].items())
+        mo.table(rank, f"/* Register image from the {sil['silicon']} mapping ({cites}).\n"
+                       f" * {sil.get('statusNote', '')[:300]} */\n{decl} = {{\n" + ",\n".join(lines) + "\n};")
+
+
+@register("Dio")
+class Dio(Generator):
+    def specific(self, mo):
+        if "Dio.h" not in self.ctx.headers:
+            mo.notes.append("no Dio.h (static Dio code) in the project: Dio_ChannelGroupType objects not generated")
+            return
+        objs, decls = [], []
+        for g in self.cg.instances(self.mc, "DioChannelGroup"):
+            ident = (g.text("DioChannelGroupIdentification") or "").strip()
+            m = re.fullmatch(r"&\s*([A-Za-z_]\w*)", ident)
+            if not m:
+                mo.notes.append(f"{g.path}: DioChannelGroupIdentification {ident!r} is not '&<object>'; "
+                                "the Dio_ChannelGroupType object is not generated")
+                continue
+            port = g.parent.text("DioPortId") if g.parent is not None else None
+            vals = [W.c_uint(int(g.text("DioPortMask") or 0, 0), True), W.c_uint(int(g.text("DioPortOffset") or 0, 0)),
+                    W.c_uint(int(port or 0, 0))]
+            decls.append(f"extern CONST(Dio_ChannelGroupType, DIO_CONST) {m.group(1)};")
+            objs.append(f"CONST(Dio_ChannelGroupType, DIO_CONST) {m.group(1)} = {{ {', '.join(vals)} }}; "
+                        f"/* {g.name}: mask, offset, port (SWS_Dio_00184) */")
+        if objs:
+            mo.hdecls += ["/* Channel groups (ECUC_Dio_00149); Dio.h defines Dio_ChannelGroupType before including Dio_Cfg.h */",
+                          *decls]
+            rank = max(self.cg.eff_class(self.mc, self.cg.param_def(g, "DioPortMask"))
+                       for g in self.cg.instances(self.mc, "DioChannelGroup"))
+            mo.table(max(rank, CLASS_RANK["PRE-COMPILE"]), "\n".join(objs))
+            mo.include("Dio.h")

package/python/ecuc_engine/codegen/modules/memstack.py

@@ -0,0 +1,24 @@
+"""Memory stack: NvM, MemIf, Fee, Ea. Everything they need is expressible by the defs (block
+descriptors, symbolic block IDs/numbers, pre-compile switches), so they are plain registrations;
+the NvM block-descriptor layout of a given static NvM comes from its binding."""
+from ..registry import Generator, register
+
+
+@register("NvM")
+class NvM(Generator):
+    pass
+
+
+@register("MemIf")
+class MemIf(Generator):
+    pass
+
+
+@register("Fee")
+class Fee(Generator):
+    pass
+
+
+@register("Ea")
+class Ea(Generator):
+    pass

package/python/ecuc_engine/codegen/registry.py

@@ -0,0 +1,133 @@
+"""Generator registry. A module generator self-registers with @register("<ModuleDefName>").
+
+Any configured module can be emitted by the generic Generator (macros, symbols, tables straight
+from the param defs). A registered subclass adds only what the defs cannot express (and is what
+`autosar_codegen` runs by default). To add a module: drop a file in codegen/modules/ with a
+@register'ed subclass; modules/__init__.py imports every file in the folder.
+"""
+from __future__ import annotations
+
+import re
+from typing import Optional
+
+from . import binding as B
+from . import cwriter as W
+from . import emit as E
+
+GENERATORS: dict = {}
+
+
+def register(name: str):
+    def deco(cls):
+        cls.module = name
+        GENERATORS[name] = cls
+        return cls
+    return deco
+
+
+def generator_for(name: str):
+    from . import modules  # noqa: F401  (self-registration)
+    return GENERATORS.get(name, Generator)
+
+
+def registered() -> list:
+    from . import modules  # noqa: F401
+    return sorted(GENERATORS)
+
+
+class Generator:
+    module: Optional[str] = None
+    std_header = "Std_Types.h"
+
+    def __init__(self, ctx: E.Ctx, mc):
+        self.ctx = ctx
+        self.cg = ctx.cg
+        self.mc = mc
+
+    def run(self) -> E.ModuleOutput:
+        mo = E.ModuleOutput(self.ctx, self.mc)
+        mo.h_includes = [self.default_std_header()]
+        mb = B.select(self.ctx.bindings, self.mc.name, self.ctx.headers, self.ctx.binding_name)
+        mo.binding = mb
+        if mb and mb.get("headerIncludes"):
+            mo.h_includes = list(mb["headerIncludes"])
+        E.scalar_macros(self.cg, mo)
+        E.symbolic_names(self.cg, mo)
+        self.specific(mo)
+        if mb is None or mb.get("genericTables", False):
+            E.generic_tables(self.cg, mo, set(self.skip_tables(mo)))
+        if mb is not None:
+            apply_binding(self.cg, mo, mb)
+        return mo
+
+    def default_std_header(self) -> str:
+        """ComStack_Types.h for modules that reference EcuC PDUs (communication stack), else Std_Types.h."""
+        md = self.mc.defn
+        if md is not None:
+            for d in self.cg.defs.by_path.values():
+                if d.module == md.path and d.kind and "REFERENCE" in d.kind and any(
+                        r.endswith("/EcucPduCollection/Pdu") for r in d.dest_refs):
+                    return "ComStack_Types.h"
+        return self.std_header
+
+    def skip_tables(self, mo) -> list:
+        return []
+
+    def specific(self, mo: E.ModuleOutput):
+        """Module-specific emission (only what the param defs cannot express)."""
+
+
+def apply_binding(cg, mo: E.ModuleOutput, mb: dict):
+    ev = B.Eval(cg, mo.mc, mo.ctx)
+    for inc in mb.get("sourceIncludes", []):
+        mo.include(inc)
+    macros = []
+    for m in mb.get("macros", []):
+        val = m["value"]
+        macros.append((m["name"], ev.macro(val) if re.match(r"^(count|max):", val) else val))
+    mo.group(f"Static-code interface ({mb['_binding']} binding)", macros)
+    ranks: dict = {}
+    pending: list = []
+    for t in mb.get("tables", []):
+        ev.rank = 1
+        rows = list(cg.sorted_instances(mo.mc, t["rows"]))
+        if t.get("order"):
+            from ..values import parse_int
+            rows.sort(key=lambda r: (parse_int(r.text(t["order"]) or "") is None, parse_int(r.text(t["order"]) or "") or 0))
+        lines, externs = [], []
+        for r in rows:
+            vals = []
+            for f in t["fields"]:
+                v, _ = ev.field(r, f)
+                vals.append(v)
+                if f.get("extern") and v not in ("NULL_PTR", "0", "0u") and not v.startswith('"'):
+                    m = re.search(r"[A-Za-z_]\w*", v)
+                    if m:
+                        ext = "extern " + f["extern"].replace("{}", m.group(0)) + ";"
+                        if ext not in externs:
+                            externs.append(ext)
+            lead = f"[{cg.symbol(r)}] = " if t.get("designated") else ""
+            comment = t.get("comment", "name")
+            cm = {"name": r.name, "sym": cg.symbol(r) or r.name}.get(comment, r.name)
+            if t.get("scalar"):
+                lines.append(f"  {lead}{vals[0]} /* {cm} */")
+            else:
+                lines.append(f"  {lead}{{ {', '.join(vals)} }} /* {cm} */")
+        st = "static " if t.get("static") else ""
+        size = t.get("size", "")
+        body = (f"/* {t.get('doc', t['rows'])} */\n{st}CONST({t['type']}, {t['qualifier']}) {t['name']}[{size}] = {{\n" +
+                ",\n".join(lines) + "\n};")
+        ranks[t["name"]] = ev.rank
+        pending.append((ev.rank, body, externs))
+    objects = mb.get("objects", [])
+    if objects:
+        # a root config object points at the (static) tables, so they all live in its file:
+        # the most dynamic config class among them (e.g. <Mip>_PBcfg.c for a post-build PduR_Config)
+        top = max([r for r, _, _ in pending] + [1])
+        pending = [(top, b, e) for _, b, e in pending]
+        for o in objects:
+            body = (f"CONST({o['type']}, {o['qualifier']}) {o['name']} = {{\n  " + ", ".join(o["init"]) + "\n};")
+            pending.append((top, body, []))
+    for rank, body, externs in pending:
+        mo.table(rank, body, externs)
+    mo.used_mips |= ev.used_mips