@h2loop/autosar 0.1.2 → 1.1.0

package/python/ecuc_engine/add_signal.py

@@ -0,0 +1,351 @@
+"""autosar_add_signal: add one Com signal end to end, consistently, or refuse.
+
+Chain (all derived by following references from a sibling signal already in the target I-PDU, so it works
+for any project that follows its own conventions):
+  ECUC   ComSignal (parameter elements templated from the sibling: DEFINITION-REF/DEST/value-element types),
+         ComIPduSignalRef on the I-PDU, ComHandleId = lowest unused (existing handles never move)
+  System SYSTEM-SIGNAL, I-SIGNAL, I-SIGNAL-TO-I-PDU-MAPPING and every element in the sibling's chain that
+         carries the sibling's name (I-SIGNAL-TRIGGERING, I-SIGNAL-PORT, ...), plus the reference entries that
+         shared elements (PDU-TRIGGERING, ECU extract FIBEX-ELEMENTS, ...) hold for the sibling
+  DBC    an SG_ line in the frame with the I-PDU's CAN ID, if a .dbc in the project has it
+Layout is checked first (inside the I-PDU, no overlap); ecuc_validate runs after the write and any new
+finding rolls everything back.
+"""
+from __future__ import annotations
+
+import os
+import re
+from typing import Optional
+
+from . import paths
+from .arxml_edit import ArxmlEditError, ArxmlEditor
+from .model import Project
+from .rules import RuleContext
+from .rules.com import _layout, bits
+from .values import parse_int
+from .xmltree import escape, line_indent
+
+TYPES = {"BOOLEAN": 1, "UINT8": 8, "SINT8": 8, "UINT16": 16, "SINT16": 16, "UINT32": 32, "SINT32": 32,
+         "UINT64": 64, "SINT64": 64, "FLOAT32": 32, "FLOAT64": 64}
+ORDER = {"LITTLE_ENDIAN": "MOST-SIGNIFICANT-BYTE-LAST", "BIG_ENDIAN": "MOST-SIGNIFICANT-BYTE-FIRST", "OPAQUE": "OPAQUE"}
+
+
+class AddSignalError(Exception):
+    pass
+
+
+def _resolve_ipdu(project: Project, ipdu: str):
+    from .ecucjson import resolve
+    r = resolve(project, ipdu)
+    cands = [r] if isinstance(r, str) else r.get("didYouMean", [])
+    cands = [c for c in cands if project.find(c) and (project.find(c)[0].def_ref or "").endswith("/ComIPdu")]
+    if len(cands) != 1:
+        raise AddSignalError(f"I-PDU {ipdu!r} does not name exactly one ComIPdu ({cands or 'none found'})")
+    return project.find(cands[0])[0]
+
+
+def plan_layout(ctx: RuleContext, ip, pos: Optional[int], size: int, endian: str):
+    pdu = ctx.target(ctx.value(ip, "ComPduIdRef"))
+    length = parse_int(ctx.text(pdu, "PduLength") or "") if pdu is not None else None
+    if length is None:
+        raise AddSignalError(f"{ip.name}: PduLength unknown (ComPduIdRef -> EcuC Pdu)")
+    used = set()
+    members = [ctx.target(pv) for pv in ctx.values(ip, "ComIPduSignalRef")]
+    for s in (m for m in members if m is not None):
+        for _label, bs, *_rest in _layout(ctx, s):
+            used |= set(bs)
+    limit = length * 8
+    if pos is None:  # first free byte-aligned position
+        for start in range(0, limit, 8):
+            b = bits(start, size, endian)
+            if min(b) >= 0 and max(b) < limit and not used & set(b):
+                pos = start
+                break
+        if pos is None:
+            raise AddSignalError(f"{ip.name}: no free byte-aligned position for {size} bits (PduLength {length})")
+    b = bits(pos, size, endian)
+    if min(b) < 0 or max(b) >= limit:
+        raise AddSignalError(f"bits {min(b)}..{max(b)} lie outside {ip.name} (PduLength {length} bytes)")
+    if used & set(b):
+        raise AddSignalError(f"bits {sorted(used & set(b))[:8]} of the new signal overlap existing signals in {ip.name}")
+    return pos, members, pdu
+
+
+def _container_text(data: bytes, node) -> bytes:
+    return data[node.start:node.end]
+
+
+def add_signal(project: Project, name: str, ipdu: str, bit_size: Optional[int] = None, signal_type: str = "UINT8",
+               bit_position: Optional[int] = None, endianness: str = "LITTLE_ENDIAN", init=0,
+               transfer_property: Optional[str] = None, dry_run: bool = False) -> dict:
+    from .edit import Editor
+    from .validate import validate
+    signal_type = signal_type.upper()
+    endianness = endianness.upper()
+    size = bit_size or TYPES.get(signal_type)
+    if not size:
+        raise AddSignalError(f"bit_size needed for type {signal_type}")
+    if not re.fullmatch(r"[A-Za-z_]\w*", name):
+        raise AddSignalError(f"{name!r} is not a valid SHORT-NAME / C identifier")
+    ctx = RuleContext(project)
+    ip = _resolve_ipdu(project, ipdu)
+    if project.find(f"{ip.parent.path}/{name}"):
+        raise AddSignalError(f"{ip.parent.path}/{name} already exists")
+    pos, members, pdu = plan_layout(ctx, ip, bit_position, size, endianness)
+    sib = next((m for m in members if m is not None and (m.def_ref or "").endswith("/ComSignal")), None)
+    if sib is None:
+        raise AddSignalError(f"{ip.name} has no ComSignal to use as template")
+    before = {(d["rule"], d["path"], d["message"]) for d in validate(project, check_generated=False)["diagnostics"]
+              if d["severity"] in ("error", "warning")}
+    notes: list = []
+
+    # ---------- system extract ----------
+    sysi = project.system
+    ref_pv = next((pv for g in project.find(sib.path) for pv in g.params if pv.is_ref and sysi.get(pv.value or "")), None)
+    sys_writes, new_mapping = {}, None
+    if ref_pv is not None and sysi.by_path:
+        ed = ArxmlEditor(project)
+        try:
+            new_mapping = _clone_system_chain(project, ed, sysi.get(ref_pv.value), sib.name, name)
+            m_path = new_mapping
+            ed.op_set({"path": m_path, "element": "START-POSITION", "value": pos})
+            ed.op_set({"path": m_path, "element": "PACKING-BYTE-ORDER", "value": ORDER.get(endianness, endianness)})
+            if transfer_property:
+                ed.op_set({"path": m_path, "element": "TRANSFER-PROPERTY", "value": transfer_property.upper().replace("_", "-")})
+            isig = _renamed(sysi.get(ref_pv.value).one("I-SIGNAL-REF"), sib.name, name)
+            if isig:
+                ed.op_set({"path": isig, "element": "LENGTH", "value": size})
+                ft, node = ed.tree_for(isig)
+                if ed.own_child(node, "VALUE") is not None:
+                    ed.op_set({"path": isig, "element": "VALUE", "value": init})
+                else:
+                    ed.op_add({"parent_path": isig, "element": "INIT-VALUE",
+                               "values": {"NUMERICAL-VALUE-SPECIFICATION": {"VALUE": init}}})
+        except ArxmlEditError as e:
+            raise AddSignalError(f"system extract: {e}") from None
+        probs = ed.check()
+        if probs:
+            raise AddSignalError("system extract edit would leave: " + "; ".join(probs[:5]))
+        sys_writes = {f: ft.data for f, ft in ed.files.items() if ft.data != ed.original[f]}
+    else:
+        notes.append("no system-extract link on the template signal; extract not changed")
+
+    # ---------- ECUC ----------
+    ced = Editor(project)
+    data = project.files[sib.file].data
+    unit = ced.unit(sib.file, sib.node)
+    ind = line_indent(data, sib.node.start) or b""
+    tmpl = {pv.name: pv for g in project.find(sib.path) for pv in g.params}
+    used_ids = {parse_int(pv.value or "") for c in ctx.containers(ctx.rel(sib.def_ref)) for pv in ctx.values(c, "ComHandleId")}
+    hid = next(i for i in range(0, 1 << 16) if i not in used_ids)
+    want = {"ComBitPosition": pos, "ComBitSize": size, "ComSignalType": signal_type, "ComSignalEndianness": endianness,
+            "ComSignalInitValue": init, "ComHandleId": hid}
+    if transfer_property:
+        want["ComTransferProperty"] = transfer_property.upper()
+    elif "ComTransferProperty" in tmpl:
+        want["ComTransferProperty"] = tmpl["ComTransferProperty"].value
+    missing = [k for k in ("ComBitPosition", "ComBitSize", "ComHandleId") if k not in tmpl]
+    if missing:
+        raise AddSignalError(f"template signal {sib.name} lacks {missing}; add the signal with ecuc_edit instead")
+    skipped = [k for k in want if k not in tmpl]
+    if skipped:
+        notes.append(f"not set (template {sib.name} has no such parameter element): {', '.join(skipped)} — "
+                     "set them with ecuc_edit if the module requires them")
+    nl = project.files[sib.file].newline
+    params, refs = [], []
+    for k, pv in tmpl.items():
+        if pv.is_ref:
+            if new_mapping and sysi.get(pv.value or ""):
+                refs.append(_retarget(data, pv, new_mapping))
+            continue
+        if k in want:
+            params.append(_revalue(data, pv, want[k]))
+    head = re.sub(r'\s+UUID="[^"]*"', "", data[sib.node.start:sib.node.stag_end].decode())
+    dr = sib.node.child("DEFINITION-REF")
+    u = unit.decode()
+    lines = [(0, head), (1, f"<SHORT-NAME>{escape(name)}</SHORT-NAME>"), (1, data[dr.start:dr.end].decode()),
+             (1, "<PARAMETER-VALUES>")]
+    for p in params:
+        lines += [(2, p[0])] + [(2, ln) for ln in p[1:]]
+    lines.append((1, "</PARAMETER-VALUES>"))
+    if refs:
+        lines.append((1, "<REFERENCE-VALUES>"))
+        for r in refs:
+            lines += [(2, r[0])] + [(2, ln) for ln in r[1:]]
+        lines.append((1, "</REFERENCE-VALUES>"))
+    lines.append((0, f"</{sib.node.tag}>"))
+    block = nl.join((ind if i else b"") + (u * d + t).encode() for i, (d, t) in enumerate(lines))
+    last = max((c for c in sib.parent.children if (c.def_ref or "").endswith("/ComSignal") and c.file == sib.file),
+               key=lambda c: c.node.end)
+    ced.patch(sib.file, last.node.end, last.node.end, nl + ind + block)
+    ip = project.find(ip.path)[0]
+    sref = [pv for pv in ip.params if pv.name == "ComIPduSignalRef"]
+    tpl = sref[-1].node
+    d2 = project.files[ip.file].data
+    rtext = d2[tpl.start:tpl.end].decode().replace(f">{sref[-1].value}<", f">{ip.parent.path}/{name}<")
+    rind = line_indent(d2, tpl.start) or b""
+    ced.patch(ip.file, tpl.end, tpl.end, project.files[ip.file].newline + rind + rtext.encode())
+    ecuc_writes = {f: project.files[f].data for f in ced.original if project.files[f].data != ced.original[f]}
+
+    # ---------- DBC ----------
+    dbc_writes = _dbc_line(project, pdu, name, pos, size, endianness, signal_type, notes)
+
+    writes = {**sys_writes, **ecuc_writes, **dbc_writes}
+    originals = {f: open(f, "rb").read() for f in writes}
+    res = {"signal": f"{ip.parent.path}/{name}", "ipdu": ip.path, "ComBitPosition": pos, "ComBitSize": size,
+           "ComHandleId": hid, "systemMapping": new_mapping, "files": sorted(project.rel(f) for f in writes),
+           "notes": notes}
+    if dry_run:
+        return {**res, "ok": True, "written": False}
+    for f, b in writes.items():
+        with open(f, "wb") as fh:
+            fh.write(b)
+    after = validate(Project(project.root), check_generated=False)
+    new = [d for d in after["diagnostics"] if d["severity"] in ("error", "warning")
+           and (d["rule"], d["path"], d["message"]) not in before]
+    if new:
+        for f, b in originals.items():
+            with open(f, "wb") as fh:
+                fh.write(b)
+        return {**res, "ok": False, "written": False, "error": "validation found new problems; all changes rolled back",
+                "diagnostics": new[:20]}
+    return {**res, "ok": True, "written": True, "validation": after["summary"],
+            "next": "regenerate (autosar_generate), use the generated symbol "
+                    f"ComConf_ComSignal_{name} in the C code, build (autosar_build)"}
+
+
+def _dedent(text: str) -> list:
+    lines = text.split("\n")
+    rest = [ln for ln in lines[1:] if ln.strip()]
+    cut = min((len(ln) - len(ln.lstrip()) for ln in rest), default=0)
+    first_ind = 0
+    if rest:
+        # the first line has no leading whitespace (it starts at the element); later lines are deeper by one unit
+        first_ind = cut - min((len(ln) - len(ln.lstrip()) for ln in rest[-1:]), default=cut)
+    return [lines[0].strip()] + [ln[cut + first_ind:] if len(ln) >= cut else ln.strip() for ln in lines[1:]]
+
+
+def _revalue(data: bytes, pv, value) -> list:
+    vn = pv.value_node
+    if vn is None or vn.cstart is None:
+        raise AddSignalError(f"template parameter {pv.name} has no VALUE")
+    v = "true" if value is True else "false" if value is False else str(value)
+    text = (data[pv.node.start:vn.cstart] + escape(v).encode() + data[vn.cend:pv.node.end]).decode()
+    return _dedent(text)
+
+
+def _retarget(data: bytes, pv, target: str) -> list:
+    vn = pv.value_node
+    text = (data[pv.node.start:vn.cstart] + escape(target).encode() + data[vn.cend:pv.node.end]).decode()
+    return _dedent(text)
+
+
+def _renamed(path, old: str, new: str) -> Optional[str]:
+    if not path or not isinstance(path, str):
+        return None
+    head, _, last = path.rpartition("/")
+    return f"{head}/{last.replace(old, new)}" if old in last else None
+
+
+def _clone_system_chain(project: Project, ed: ArxmlEditor, mapping, old: str, new: str) -> str:
+    """Clone the sibling's extract chain under the new name; return the new mapping path."""
+    sysi = project.system
+    if mapping is None or mapping.tag != "I-SIGNAL-TO-I-PDU-MAPPING":
+        raise ArxmlEditError("template signal's system reference is not an I-SIGNAL-TO-I-PDU-MAPPING")
+    seed = {mapping.path}
+    isig = sysi.get(mapping.one("I-SIGNAL-REF"))
+    if isig is not None:
+        seed.add(isig.path)
+        ss = sysi.get(isig.one("SYSTEM-SIGNAL-REF"))
+        if ss is not None:
+            seed.add(ss.path)
+    chain = set(seed)
+    changed = True
+    while changed:  # referencing idents named after the sibling, and named idents they reference
+        changed = False
+        for p in list(chain):
+            for r in sysi.refs_to(p):
+                if r.path not in chain and old in r.path.rsplit("/", 1)[-1]:
+                    chain.add(r.path)
+                    changed = True
+            i = sysi.get(p)
+            for t, vals in (i.values.items() if i else []):
+                for v in vals if (t.endswith("-REF") or t.endswith("-TREF")) else []:
+                    vi = sysi.get(v)
+                    if vi is not None and v not in chain and old in v.rsplit("/", 1)[-1]:
+                        chain.add(v)
+                        changed = True
+    mapping_new = None
+    subst = {p: _renamed(p, old, new) for p in chain}
+    if any(v is None for v in subst.values()):
+        subst = {k: v for k, v in subst.items() if v}
+    for p in sorted(chain, key=lambda x: (x != mapping.path, x)):
+        ft, node = ed.tree_for(p)
+        text = ft.data[node.start:node.end].decode()
+        for a, b in subst.items():
+            text = text.replace(f">{a}<", f">{b}<")
+        text = text.replace(f"<SHORT-NAME>{p.rsplit('/', 1)[-1]}</SHORT-NAME>",
+                            f"<SHORT-NAME>{subst[p].rsplit('/', 1)[-1]}</SHORT-NAME>", 1)
+        if subst[p] in ft.by_path or project.identifiables.get(subst[p]):
+            raise ArxmlEditError(f"{subst[p]} already exists")
+        ind = line_indent(ft.data, node.start) or b""
+        ed.added_tags[subst[p]] = node.tag
+        ed.patch(ft, node.end, node.end, ft.nl + ind + text.encode())
+        if p == mapping.path:
+            mapping_new = subst[p]
+    # reference entries held by shared elements (not renamed): clone the wrapper next to the original
+    for p in chain:
+        for r in sysi.refs_to(p):
+            if r.path in chain:
+                continue
+            ft, node = ed.tree_for(r.path)
+            for leaf in node.iter():
+                if leaf.text.strip() != p or not (leaf.tag.endswith("-REF") or leaf.tag.endswith("-TREF")):
+                    continue
+                wrap = leaf
+                while wrap.parent is not None and wrap.parent is not node and len(wrap.parent.children) == 1 \
+                        and not wrap.parent.tag.endswith("S"):
+                    wrap = wrap.parent
+                text = ft.data[wrap.start:wrap.end].decode().replace(f">{p}<", f">{subst[p]}<")
+                ind = line_indent(ft.data, wrap.start) or b""
+                ed.patch(ft, wrap.end, wrap.end, ft.nl + ind + text.encode())
+                ft, node = ed.tree_for(r.path)
+                break
+    return mapping_new
+
+
+def _dbc_line(project: Project, pdu, name, pos, size, endian, typ, notes) -> dict:
+    from .audit import can_info
+    infos = can_info(project, pdu.path if pdu is not None else None)
+    dbcs = paths.walk(project.root, lambda n: n.lower().endswith(".dbc")).files
+    if not dbcs or not infos:
+        return {}
+    out = {}
+    for info in infos:
+        cid = info.get("canId")
+        if cid is None:
+            continue
+        for f in dbcs:
+            text = open(f, encoding="utf-8", errors="replace").read()
+            m = re.search(rf"^BO_ ({cid}|{cid | 0x80000000}) (\w+)\s*:.*$", text, re.M)
+            if not m:
+                continue
+            block_end = m.end()
+            sg = list(re.finditer(r"^\s*SG_ .*$", text[m.end():].split("\n\n", 1)[0], re.M))
+            recv = "Vector__XXX"
+            if sg:
+                block_end = m.end() + sg[-1].end()
+                rm = re.search(r'"[^"]*"\s*(.*)$', sg[-1].group(0))
+                recv = (rm.group(1).strip() if rm else "") or recv
+            start = pos
+            if endian == "BIG_ENDIAN":
+                from .rules.system import _motorola_msb
+                start = _motorola_msb(pos, size)
+            sign = "-" if typ.startswith("S") else "+"
+            mx = (1 << size) - 1 if sign == "+" else (1 << (size - 1)) - 1
+            line = f'\n SG_ {name} : {start}|{size}@{0 if endian == "BIG_ENDIAN" else 1}{sign} (1,0) [0|{mx}] "" {recv}'
+            if re.search(rf"^\s*SG_ {re.escape(name)}\b", text, re.M):
+                continue
+            out[f] = (text[:block_end] + line + text[block_end:]).encode()
+            notes.append(f"added SG_ {name} to BO_ {m.group(1)} {m.group(2)} in {project.rel(f)}")
+    return out