zemu 0.1.0

data/src/external/Z/API/Z/hardware/CPU/architecture/6502.h

@@ -0,0 +1,90 @@
+/* Z Kit - hardware/CPU/architecture/6502.h
+ _____  _______________
+/_   /_/  -_/_   _/  _ |
+ /____/\___/ /__//___/_| Kit
+Copyright (C) 2006-2018 Manuel Sainz de Baranda y Goñi.
+Released under the terms of the GNU Lesser General Public License v3.
+
+Registers:
+.-----------------------------------.
+| F E D C B A 9 8 | 7 6 5 4 3 2 1 0 |
+|-----------------------------------|
+|		 PC		    | Program Counter
+'-----------------------------------|
+		  |	   S	    | Stack Pointer
+		  |-----------------|
+		  |	   P	    | Program Status (flags)
+		  |-----------------|
+		  |	   A	    | Accumulator
+		  |-----------------|
+		  |	   X	    | X Index
+		  |-----------------|
+		  |	   Y	    | Y Index
+		  '-----------------'
+
+Status (P register):
+.-----------------.
+| 7 6 5 4 3 2 1 0 |
+| N V - B D I Z C |
+'-|-|-|-|-|-|-|-|-'
+  | | | | | | | '-> carry
+  | | | | | | '---> zero
+  | | | | | '-----> interrupt (IRQ disable)
+  | | | | '-------> decimal (use BCD for arithmetics)
+  | | | '---------> break
+  | | '-----------> (ignored)
+  | '-------------> overflow
+  '---------------> negative */
+
+#ifndef _Z_hardware_CPU_architecture_6502_H_
+#define _Z_hardware_CPU_architecture_6502_H_
+
+#include <Z/types/base.h>
+
+/* MARK: - Addresses */
+
+#define Z_6502_ADDRESS_NMI_POINTER   0xFFFA
+#define Z_6502_ADDRESS_RESET_POINTER 0XFFFC
+#define Z_6502_ADDRESS_IRQ_POINTER   0xFFFE
+#define Z_6502_ADDRESS_BRK_POINTER   0xFFFE
+#define Z_6502_ADDRESS_STACK	     0x0100
+
+/* MARK: - Values after power on */
+
+#define Z_6502_VALUE_AFTER_POWER_ON_PC 0x0000
+#define Z_6502_VALUE_AFTER_POWER_ON_S  0xFD
+#define Z_6502_VALUE_AFTER_POWER_ON_P  0x36
+#define Z_6502_VALUE_AFTER_POWER_ON_A  0x00
+#define Z_6502_VALUE_AFTER_POWER_ON_X  0x00
+#define Z_6502_VALUE_AFTER_POWER_ON_Y  0x00
+
+/* MARK: - State storage type */
+
+Z_DEFINE_STRICT_STRUCTURE_BEGIN
+	zuint16 pc;
+	zuint8	s, p, a, x, y;
+
+	struct {zuint8 irq :1;
+		zuint8 nmi :1;
+	} internal;
+Z_DEFINE_STRICT_STRUCTURE_END Z6502State;
+
+#define Z_6502_STATE_PC( object) (object)->pc
+#define Z_6502_STATE_S(	 object) (object)->s
+#define Z_6502_STATE_P(	 object) (object)->p
+#define Z_6502_STATE_A(	 object) (object)->a
+#define Z_6502_STATE_X(	 object) (object)->x
+#define Z_6502_STATE_Y(	 object) (object)->y
+#define Z_6502_STATE_NMI(object) (object)->internal.nmi
+#define Z_6502_STATE_IRQ(object) (object)->internal.irq
+
+#define Z_6502_STATE_MEMBER_PC	pc
+#define Z_6502_STATE_MEMBER_S	s
+#define Z_6502_STATE_MEMBER_P	p
+#define Z_6502_STATE_MEMBER_A	a
+#define Z_6502_STATE_MEMBER_X	x
+#define Z_6502_STATE_MEMBER_Y	y
+#define Z_6502_STATE_MEMBER_NMI internal.nmi
+#define Z_6502_STATE_MEMBER_IRQ internal.irq
+
+#endif /* _Z_hardware_CPU_architecture_6502_H_ */

data/src/external/Z/API/Z/hardware/CPU/architecture/Z80.h

@@ -0,0 +1,245 @@
+/* Z Kit - hardware/CPU/architecture/Z80.h
+ _____  _______________
+/_   /_/  -_/_   _/  _ |
+ /____/\___/ /__//___/_| Kit
+Copyright (C) 2006-2018 Manuel Sainz de Baranda y Goñi.
+Released under the terms of the GNU Lesser General Public License v3.
+
+Registers:
+.-----------------------------------.
+| F E D C B A 9 8 | 7 6 5 4 3 2 1 0 |
+|-----------------------------------|
+|		 PC		    |
+|-----------------------------------|
+|		 SP		    |
+|-----------------------------------|
+|	 A	 AF	   F	    |
+|-----------------------------------|
+|	 B	 BC	   C	    |
+|-----------------------------------|
+|	 D	 DE	   E	    |
+|-----------------------------------|
+|	 H	 HL	   L	    |
+|-----------------------------------|
+|	IXH	 IX	  IXL	    |
+|-----------------------------------|
+|	IYH	 IY	  IYL	    |
+|-----------------------------------|
+|		 AF'		    |
+|-----------------------------------|
+|		 BC'		    |
+|-----------------------------------|
+|		 DE'		    |
+|-----------------------------------|
+|		 HL'		    |
+'-----------------------------------|
+		  |	   I	    |
+		  |-----------------|
+		  |	   R	    |
+		  '-----------------'
+
+Flags (F register):
+.-----------------.
+| 7 6 5 4 3 2 1 0 |
+| S Z Y H X P N C |
+'-|-|-|-|-|-|-|-|-'
+  | | | | | | | '-> carry
+  | | | | | | '---> addition / subtraction
+  | | | | | '-----> parity / 2-compliment signed overflow
+  | | | | '-------> result bit 3 copy (undocumented)
+  | | | '---------> half carry
+  | | '-----------> result bit 5 copy (undocumented)
+  | '-------------> zero
+  '---------------> sign */
+
+#ifndef _Z_hardware_CPU_architecture_Z80_H_
+#define _Z_hardware_CPU_architecture_Z80_H_
+
+#include <Z/types/base.h>
+
+/* MARK: - Limits and features */
+
+#define Z_Z80_MINIMUM_CYCLES_PER_INSTRUCTION 4
+#define Z_Z80_MAXIMUM_CYCLES_PER_INSTRUCTION 23
+#define Z_Z80_MINIMUM_BITS_INSTRUCTION	     8
+#define Z_Z80_MAXIMUM_BITS_INSTRUCTION	     32
+#define Z_Z80_BITS_ADDRESS_BUS		     16
+#define Z_Z80_BITS_DATA_BUS		     8
+#define Z_Z80_BITS_ADDRESSING		     16
+
+/* MARK: - Addresses */
+
+#define Z_Z80_ADDRESS_NMI_POINTER 0x0066
+
+/* MARK: - Values after power on */
+/*
+#define Z_Z80_VALUE_AFTER_POWER_ON_PC	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_SP	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_AF	  0x0040
+#define Z_Z80_VALUE_AFTER_POWER_ON_BC	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_DE	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_HL	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_IX	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_IY	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_AF_	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_BC_	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_DE_	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_HL_	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_I	  0x00
+#define Z_Z80_VALUE_AFTER_POWER_ON_R	  0x00
+#define Z_Z80_VALUE_AFTER_POWER_ON_MEMPTR 0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_IFF1	  0
+#define Z_Z80_VALUE_AFTER_POWER_ON_IFF2	  0
+#define Z_Z80_VALUE_AFTER_POWER_ON_IM	  1*/
+
+#define Z_Z80_VALUE_AFTER_POWER_ON_PC	  0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_SP	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_AF	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_BC	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_DE	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_HL	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_IX	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_IY	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_AF_	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_BC_	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_DE_	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_HL_	  0xFFFF
+#define Z_Z80_VALUE_AFTER_POWER_ON_I	  0x00
+#define Z_Z80_VALUE_AFTER_POWER_ON_R	  0x00
+#define Z_Z80_VALUE_AFTER_POWER_ON_MEMPTR 0x0000
+#define Z_Z80_VALUE_AFTER_POWER_ON_IFF1	  0
+#define Z_Z80_VALUE_AFTER_POWER_ON_IFF2	  0
+#define Z_Z80_VALUE_AFTER_POWER_ON_IM	  0
+
+/* MARK: - Values after reset */
+
+#define Z_Z80_VALUE_AFTER_RESET_PC     Z_Z80_VALUE_AFTER_POWER_ON_PC
+#define Z_Z80_VALUE_AFTER_RESET_SP     Z_Z80_VALUE_AFTER_POWER_ON_SP
+#define Z_Z80_VALUE_AFTER_RESET_AF     Z_Z80_VALUE_AFTER_POWER_ON_AF
+#define Z_Z80_VALUE_AFTER_RESET_BC     Z_Z80_VALUE_AFTER_POWER_ON_BC
+#define Z_Z80_VALUE_AFTER_RESET_DE     Z_Z80_VALUE_AFTER_POWER_ON_DE
+#define Z_Z80_VALUE_AFTER_RESET_HL     Z_Z80_VALUE_AFTER_POWER_ON_HL
+#define Z_Z80_VALUE_AFTER_RESET_IX     Z_Z80_VALUE_AFTER_POWER_ON_IX
+#define Z_Z80_VALUE_AFTER_RESET_IY     Z_Z80_VALUE_AFTER_POWER_ON_IY
+#define Z_Z80_VALUE_AFTER_RESET_AF_    Z_Z80_VALUE_AFTER_POWER_ON_AF_
+#define Z_Z80_VALUE_AFTER_RESET_BC_    Z_Z80_VALUE_AFTER_POWER_ON_BC_
+#define Z_Z80_VALUE_AFTER_RESET_DE_    Z_Z80_VALUE_AFTER_POWER_ON_DE_
+#define Z_Z80_VALUE_AFTER_RESET_HL_    Z_Z80_VALUE_AFTER_POWER_ON_HL_
+#define Z_Z80_VALUE_AFTER_RESET_I      Z_Z80_VALUE_AFTER_POWER_ON_I
+#define Z_Z80_VALUE_AFTER_RESET_R      Z_Z80_VALUE_AFTER_POWER_ON_R
+#define Z_Z80_VALUE_AFTER_RESET_MEMPTR Z_Z80_VALUE_AFTER_POWER_ON_MEMPTR
+#define Z_Z80_VALUE_AFTER_RESET_IFF1   Z_Z80_VALUE_AFTER_POWER_ON_IFF1
+#define Z_Z80_VALUE_AFTER_RESET_IFF2   Z_Z80_VALUE_AFTER_POWER_ON_IFF2
+#define Z_Z80_VALUE_AFTER_RESET_IM     Z_Z80_VALUE_AFTER_POWER_ON_IM
+
+/* MARK: - Information for emulation */
+
+#define Z_Z80_RESET_IS_EQUAL_TO_POWER_ON TRUE
+
+/* MARK: - State storage type */
+
+Z_DEFINE_STRICT_STRUCTURE_BEGIN
+	zuint16	pc,  sp;
+	Z16Bit	af,  bc,  de,  hl,  ix, iy;
+	Z16Bit	af_, bc_, de_, hl_;
+	zuint8	r,   i;
+
+	zuint16 memptr;
+
+	struct {zuint8 halt :1;
+		zuint8 irq  :1;
+		zuint8 nmi  :1;
+		zuint8 iff1 :1;
+		zuint8 iff2 :1;
+		zuint8 ei   :1;
+		zuint8 im   :2;
+	} internal;
+Z_DEFINE_STRICT_STRUCTURE_END ZZ80State;
+
+#define Z_Z80_STATE_AF(	   object) (object)->af.value_uint16
+#define Z_Z80_STATE_BC(	   object) (object)->bc.value_uint16
+#define Z_Z80_STATE_DE(	   object) (object)->de.value_uint16
+#define Z_Z80_STATE_HL(	   object) (object)->hl.value_uint16
+#define Z_Z80_STATE_IX(	   object) (object)->ix.value_uint16
+#define Z_Z80_STATE_IY(	   object) (object)->iy.value_uint16
+#define Z_Z80_STATE_PC(	   object) (object)->pc
+#define Z_Z80_STATE_SP(	   object) (object)->sp
+#define Z_Z80_STATE_AF_(   object) (object)->af_.value_uint16
+#define Z_Z80_STATE_BC_(   object) (object)->bc_.value_uint16
+#define Z_Z80_STATE_DE_(   object) (object)->de_.value_uint16
+#define Z_Z80_STATE_HL_(   object) (object)->hl_.value_uint16
+#define Z_Z80_STATE_A(	   object) (object)->af.values_uint8.index1
+#define Z_Z80_STATE_F(	   object) (object)->af.values_uint8.index0
+#define Z_Z80_STATE_B(	   object) (object)->bc.values_uint8.index1
+#define Z_Z80_STATE_C(	   object) (object)->bc.values_uint8.index0
+#define Z_Z80_STATE_D(	   object) (object)->de.values_uint8.index1
+#define Z_Z80_STATE_E(	   object) (object)->de.values_uint8.index0
+#define Z_Z80_STATE_H(	   object) (object)->hl.values_uint8.index1
+#define Z_Z80_STATE_L(	   object) (object)->hl.values_uint8.index0
+#define Z_Z80_STATE_IXH(   object) (object)->ix.values_uint8.index1
+#define Z_Z80_STATE_IXL(   object) (object)->ix.values_uint8.index0
+#define Z_Z80_STATE_IYH(   object) (object)->iy.values_uint8.index1
+#define Z_Z80_STATE_IYL(   object) (object)->iy.values_uint8.index0
+#define Z_Z80_STATE_A_(	   object) (object)->af_.values_uint8.index1
+#define Z_Z80_STATE_F_(	   object) (object)->af_.values_uint8.index0
+#define Z_Z80_STATE_B_(	   object) (object)->bc_.values_uint8.index1
+#define Z_Z80_STATE_C_(	   object) (object)->bc_.values_uint8.index0
+#define Z_Z80_STATE_D_(	   object) (object)->de_.values_uint8.index1
+#define Z_Z80_STATE_E_(	   object) (object)->de_.values_uint8.index0
+#define Z_Z80_STATE_H_(	   object) (object)->hl_.values_uint8.index1
+#define Z_Z80_STATE_L_(	   object) (object)->hl_.values_uint8.index0
+#define Z_Z80_STATE_I(	   object) (object)->i
+#define Z_Z80_STATE_R(	   object) (object)->r
+#define Z_Z80_STATE_MEMPTR(object) (object)->memptr
+#define Z_Z80_STATE_HALT(  object) (object)->internal.halt
+#define Z_Z80_STATE_IFF1(  object) (object)->internal.iff1
+#define Z_Z80_STATE_IFF2(  object) (object)->internal.iff2
+#define Z_Z80_STATE_EI(	   object) (object)->internal.ei
+#define Z_Z80_STATE_IM(	   object) (object)->internal.im
+#define Z_Z80_STATE_NMI(   object) (object)->internal.nmi
+#define Z_Z80_STATE_IRQ(   object) (object)->internal.irq
+
+#define Z_Z80_STATE_MEMBER_AF	  af.value_uint16
+#define Z_Z80_STATE_MEMBER_BC	  bc.value_uint16
+#define Z_Z80_STATE_MEMBER_DE	  de.value_uint16
+#define Z_Z80_STATE_MEMBER_HL	  hl.value_uint16
+#define Z_Z80_STATE_MEMBER_IX	  ix.value_uint16
+#define Z_Z80_STATE_MEMBER_IY	  iy.value_uint16
+#define Z_Z80_STATE_MEMBER_PC	  pc
+#define Z_Z80_STATE_MEMBER_SP	  sp
+#define Z_Z80_STATE_MEMBER_AF_	  af_.value_uint16
+#define Z_Z80_STATE_MEMBER_BC_	  bc_.value_uint16
+#define Z_Z80_STATE_MEMBER_DE_	  de_.value_uint16
+#define Z_Z80_STATE_MEMBER_HL_	  hl_.value_uint16
+#define Z_Z80_STATE_MEMBER_A	  af.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_F	  af.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_B	  bc.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_C	  bc.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_D	  de.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_E	  de.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_H	  hl.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_L	  hl.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_IXH	  ix.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_IXL	  ix.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_IYH	  iy.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_IYL	  iy.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_A_	  af_.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_F_	  af_.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_B_	  bc_.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_C_	  bc_.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_D_	  de_.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_E_	  de_.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_H_	  hl_.values_uint8.index1
+#define Z_Z80_STATE_MEMBER_L_	  hl_.values_uint8.index0
+#define Z_Z80_STATE_MEMBER_I	  i
+#define Z_Z80_STATE_MEMBER_R	  r
+#define Z_Z80_STATE_MEMPTR_MEMPTR memptr
+#define Z_Z80_STATE_MEMBER_HALT	  internal.halt
+#define Z_Z80_STATE_MEMBER_IFF1	  internal.iff1
+#define Z_Z80_STATE_MEMBER_IFF2	  internal.iff2
+#define Z_Z80_STATE_MEMBER_EI	  internal.ei
+#define Z_Z80_STATE_MEMBER_IM	  internal.im
+#define Z_Z80_STATE_MEMBER_NMI	  internal.nmi
+#define Z_Z80_STATE_MEMBER_IRQ	  internal.irq
+
+#endif /* _Z_hardware_CPU_architecture_Z80_H_ */

data/src/external/Z/API/Z/hardware/CPU/architecture/i4004.h

@@ -0,0 +1,37 @@
+/* Z Kit - hardware/CPU/architecture/i4004.h
+ _____  _______________
+/_   /_/  -_/_   _/  _ |
+ /____/\___/ /__//___/_| Kit
+Copyright (C) 2006-2018 Manuel Sainz de Baranda y Goñi.
+Released under the terms of the GNU Lesser General Public License v3. */
+
+#ifndef _Z_hardware_CPU_architecture_i4004_H_
+#define _Z_hardware_CPU_architecture_i4004_H_
+
+#include <Z/types/base.h>
+
+/* MARK: - Addresses */
+
+
+/* MARK: - Values after power on */
+
+
+/* MARK: - Values after reset */
+
+
+/* MARK: - Information for emulation */
+
+
+/* MARK: - State storage type */
+
+typedef struct {
+	zuint16	stack[4];
+	zuint8  pc;
+	zuint8	p[8];
+	zuint8	a;
+	zuint8	c;
+} Zi4004State;
+
+/* MARK: - State structure macros */
+
+#endif /* _Z_hardware_CPU_architecture_i4004_H_ */

data/src/external/Z/API/Z/hardware/PSG/General Instrument/AY-3-891x.h

@@ -0,0 +1,180 @@
+/* Z Kit - hardware/PSG/General Instrument/AY-3-891x.h
+ _____  _______________
+/_   /_/  -_/_   _/  _ |
+ /____/\___/ /__//___/_| Kit
+Copyright (C) 2006-2018 Manuel Sainz de Baranda y Goñi.
+Released under the terms of the GNU Lesser General Public License v3.
+
+		     .----._.----.
+       Vss (GND) -01-|	  \_/	 |-40- Vcc (+5V)
+	    N.C. -02-|		 |-39- TEST 1
+ANALOG CHANNEL B -03-|     _	 |-38- ANALOG CHANNEL C
+ANALOG CHANNEL A -04-|	  (_)	 |-37- DA0
+	    N.C. -05-|		 |-36- DA1
+	    IOB7 -06-|		 |-35- DA2
+	    IOB6 -07-|		 |-34- DA3
+	    IOB5 -08-|		 |-33- DA4
+	    IOB4 -09-|		 |-32- DA5
+	    IOB3 -10-|	 SOUND	 |-31- DA6
+	    IOB2 -11-| AY-3-8910 |-30- DA7
+	    IOB1 -12-|		 |-29- BC1
+	    IOB0 -13-| GI	 |-28- BC2
+	    IOA7 -14-|		 |-27- BDIR
+	    IOA6 -15-|		 |-26- TEST 2
+	    IOA5 -16-|	   _	 |-25- A8
+	    IOA4 -17-|	  (_)	 |-24- A9
+	    IOA3 -18-|		 |-23- RESET
+	    IOA2 -19-|		 |-22- CLOCK
+	    IOA1 -20-|		 |-21- IOA0
+		     '-----------'
+
+		     .----._.----.
+ANALOG CHANNEL C -01-|	  \_/	 |-28- DA0
+	  TEST 1 -02-|		 |-27- DA1
+       Vcc (+5V) -03-|		 |-26- DA2
+ANALOG CHANNEL B -04-|		 |-25- DA3
+ANALOG CHANNEL A -05-|		 |-24- DA4
+       Vss (GND) -06-|	 SOUND	 |-23- DA5
+	    IOA7 -07-| AY-3-8912 |-22- DA6
+	    IOA6 -08-|		 |-21- DA7
+	    IOA5 -09-| GI	 |-20- BC1
+	    IOA4 -10-|		 |-19- BC2
+	    IOA3 -11-|		 |-18- BDIR
+	    IOA2 -12-|		 |-17- A8
+	    IOA1 -13-|		 |-16- RESET
+	    IOA0 -14-|		 |-15- CLOCK
+		     '-----------'
+
+		     .----._.----.
+       Vss (GND) -01-|	  \_/	 |-24- CHIP SELECT
+	    BDIR -02-|		 |-23- A8
+ 	     BC1 -03-|		 |-22- A9
+ 	     DA7 -04-|		 |-21- RESET
+ 	     DA6 -05-|		 |-20- CLOCK
+ 	     DA5 -06-|	 SOUND	 |-19- Vss (GND)
+ 	     DA4 -07-| AY-3-8913 |-18- ANALOG C
+ 	     DA3 -08-|		 |-17- ANALOG A
+ 	     DA2 -09-| GI	 |-16- NO CONNECT
+ 	     DA1 -10-|		 |-15- ANALOG B
+ 	     DA0 -11-|		 |-14- TEST IN
+	TEST OUT -12-|		 |-13- Vcc
+		     '-----------'
+
+						   Content
+			      .-----------------------------------------------.
+	      Register	      |	 7  |  6  |  5	|  4  |	 3  |  2  |  1	|  0  |
+.-----------------------------+-----------------------------------------------|
+| R0  |			      |		      8-Bit Fine Tune A		      |
+|-----| Channel A Tone Period |-----------------------------------------------|
+| R1  |			      | ///////////////////// |  4-Bit Coarse Tune A  |
+|-----+-----------------------+-----------------------------------------------|
+| R2  |			      |		      8-Bit Fine Tune B		      |
+|-----| Channel B Tone Period |-----------------------------------------------|
+| R3  |			      | ///////////////////// |  4-Bit Coarse Tune B  |
+|-----+-----------------------+-----------------------------------------------|
+| R4  |			      |		      8-Bit Fine Tune C		      |
+|-----| Channel C Tone Period |-----------------------------------------------|
+| R5  |			      | ///////////////////// |  4-Bit Coarse Tune C  |
+|-----+-----------------------+-----------------------------------------------|
+| R6  | Noise Period	      | /////////////// |    5-Bit Period Control     |
+|-----+-----------------------+-----------------------------------------------|
+| R7  | Enable		      |	 IN OUT	  |	 Noise	    |	   Noise      |
+|     |			      |-----------+-----------------+-----------------|
+|     |			      | IOB | IOA |  C	|  B  |  A  |  C  |  B  |  A  |
+|-----+-----------------------+-----------------+-----+-----+-----+-----+-----|
+| R10 | Channel A Amplitude   | /////////////// |  M  |  L3 |  L2 |  L1 |  L0 |
+|-----+-----------------------+-----------------+-----+-----+-----+-----+-----|
+| R11 | Channel B Amplitude   | /////////////// |  M  |  L3 |  L2 |  L1 |  L0 |
+|-----+-----------------------+-----------------+-----+-----+-----+-----+-----|
+| R12 | Channel C Amplitude   | /////////////// |  M  |  L3 |  L2 |  L1 |  L0 |
+|-----+-----------------------+-----------------------------------------------|
+| R13 |			      |		      8-Bit Fine Tune E		      |
+|-----| Envelope Period	      |-----------------------------------------------|
+| R14 |			      |		     8-Bit Coarse Tune E	      |
+|-----+-----------------------+-----------------------------------------------|
+| R15 | Envelope Shape Cycle  | ///////////////////// | CONT| ATT | ALT | HOLD|
+|-----+-----------------------+-----------------------------------------------|
+| R16 | I/O Port A Data Store |		 8-Bit Parallel I/O on Port A	      |
+|-----+-----------------------+-----------------------------------------------|
+| R17 | I/O Port B Data Store |		 8-Bit Parallel I/O on Port A	      |
+'----------------------------------------------------------------------------*/
+
+#ifndef _Z_hardware_PSG_General_Instrument_AY_3_891x_H_
+#define _Z_hardware_PSG_General_Instrument_AY_3_891x_H_
+
+#include <Z/types/base.h>
+
+Z_DEFINE_STRICT_STRUCTURE (Z_BIT_FIELD(8, 8) (
+	zuint8 unused0 :1,
+	zuint8 unused1 :1,
+	zuint8 unused2 :1,
+	zuint8 m       :1,
+	zuint8 l3      :1,
+	zuint8 l2      :1,
+	zuint8 l1      :1,
+	zuint8 l0      :1
+)) ZAY3891xAmplitude;
+
+Z_DEFINE_STRICT_UNION (
+	zuint8 registers[16];
+
+	struct {zuint8 channel_a_tone_period_fine_tune;
+		zuint8 channel_a_tone_period_coarse_tune;
+		zuint8 channel_b_tone_period_fine_tune;
+		zuint8 channel_b_tone_perid_coarse_tune;
+		zuint8 channel_c_tone_period_fine_tune;
+		zuint8 channel_c_tone_period_coarse_tune;
+		zuint8 noise_period;
+
+		struct {Z_BIT_FIELD(8, 8) (
+			zuint8 iob     :1,
+			zuint8 ioa     :1,
+			zuint8 noise_c :1,
+			zuint8 noise_b :1,
+			zuint8 noise_a :1,
+			zuint8 tone_c  :1,
+			zuint8 tone_b  :1,
+			zuint8 tone_a  :1
+		)} enable;
+
+		ZAY3891xAmplitude channel_a_amplitude;
+		ZAY3891xAmplitude channel_b_amplitude;
+		ZAY3891xAmplitude channel_c_amplitude;
+
+		zuint8 envelope_period_fine_tune;
+		zuint8 envelope_period_coarse_tune;
+
+		struct {Z_BIT_FIELD(8, 8) (
+			zuint8 unused0 :1,
+			zuint8 unused1 :1,
+			zuint8 unused2 :1,
+			zuint8 unused3 :1,
+			zuint8 cont    :1,
+			zuint8 att     :1,
+			zuint8 alt     :1,
+			zuint8 hold    :1
+		)} envelope_shape_cycle;
+
+		zuint8 io_port_a_data_store;
+		zuint8 io_port_b_data_store;
+	} values;
+) ZAY3891xState;
+
+#define Z_AY_3_891X_CHANNEL_A_TONE_PERIOD_FINE_TUNE    0
+#define Z_AY_3_891X_CHANNEL_A_TONE_PERIOD_COARSE_TUNE  1
+#define Z_AY_3_891X_CHANNEL_B_TONE_PERIOD_FINE_TUNE    2
+#define Z_AY_3_891X_CHANNEL_B_TONE_PERID_COARSE_TUNE   3
+#define Z_AY_3_891X_CHANNEL_C_TONE_PERIOD_FINE_TUNE    4
+#define Z_AY_3_891X_CHANNEL_C_TONE_PERIOD_COARSE_TUNE  5
+#define Z_AY_3_891X_NOISE_PERIOD		       6
+#define Z_AY_3_891X_ENABLEE			       7
+#define Z_AY_3_891X_CHANNEL_A_AMPLITUDE		       8
+#define Z_AY_3_891X_CHANNEL_B_AMPLITUDE		       9
+#define Z_AY_3_891X_CHANNEL_C_AMPLITUDE		      10
+#define Z_AY_3_891X_ENVELOPE_PERIOD_FINE_TUNE	      11
+#define Z_AY_3_891X_ENVELOPE_PERIOD_COARSE_TUNE	      12
+#define Z_AY_3_891X_ENVELOPE_SHAPE_CYCLE	      13
+#define Z_AY_3_891X_IO_PORT_A_DATA_STORE	      14
+#define Z_AY_3_891X_IO_PORT_B_DATA_STORE	      15
+
+#endif /* _Z_hardware_PSG_General_Instrument_AY_3_891x_H_ */