wasmtime 17.0.1 → 18.0.3

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Files changed (2563) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +114 -142
  3. data/ext/Cargo.toml +8 -9
  4. data/ext/cargo-vendor/cranelift-bforest-0.105.3/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.105.3/Cargo.toml +40 -0
  6. data/ext/cargo-vendor/cranelift-codegen-0.105.3/.cargo-checksum.json +1 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.105.3/Cargo.toml +175 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.105.3/build.rs +395 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/egraph/domtree.rs +74 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/egraph.rs +705 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/isa/x64/inst/emit.rs +4395 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/isa/x64/inst/emit_tests.rs +5525 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/isa/x64/inst.isle +5215 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/isa/x64/lower.isle +4742 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/isa/x64/mod.rs +233 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/lib.rs +106 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/machinst/reg.rs +562 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/opts/README.md +81 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/opts/extends.isle +91 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/opts/icmp.isle +197 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/prelude_opt.isle +122 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.105.3/src/verifier/mod.rs +2033 -0
  23. data/ext/cargo-vendor/cranelift-codegen-meta-0.105.3/.cargo-checksum.json +1 -0
  24. data/ext/cargo-vendor/cranelift-codegen-meta-0.105.3/Cargo.toml +35 -0
  25. data/ext/cargo-vendor/cranelift-codegen-shared-0.105.3/.cargo-checksum.json +1 -0
  26. data/ext/cargo-vendor/cranelift-codegen-shared-0.105.3/Cargo.toml +22 -0
  27. data/ext/cargo-vendor/cranelift-control-0.105.3/.cargo-checksum.json +1 -0
  28. data/ext/cargo-vendor/cranelift-control-0.105.3/Cargo.toml +30 -0
  29. data/ext/cargo-vendor/cranelift-entity-0.105.3/.cargo-checksum.json +1 -0
  30. data/ext/cargo-vendor/cranelift-entity-0.105.3/Cargo.toml +50 -0
  31. data/ext/cargo-vendor/cranelift-frontend-0.105.3/.cargo-checksum.json +1 -0
  32. data/ext/cargo-vendor/cranelift-frontend-0.105.3/Cargo.toml +68 -0
  33. data/ext/cargo-vendor/cranelift-isle-0.105.3/.cargo-checksum.json +1 -0
  34. data/ext/cargo-vendor/cranelift-isle-0.105.3/Cargo.toml +46 -0
  35. data/ext/cargo-vendor/cranelift-native-0.105.3/.cargo-checksum.json +1 -0
  36. data/ext/cargo-vendor/cranelift-native-0.105.3/Cargo.toml +43 -0
  37. data/ext/cargo-vendor/cranelift-native-0.105.3/src/lib.rs +188 -0
  38. data/ext/cargo-vendor/cranelift-wasm-0.105.3/.cargo-checksum.json +1 -0
  39. data/ext/cargo-vendor/cranelift-wasm-0.105.3/Cargo.toml +106 -0
  40. data/ext/cargo-vendor/cranelift-wasm-0.105.3/src/code_translator.rs +3681 -0
  41. data/ext/cargo-vendor/cranelift-wasm-0.105.3/src/environ/dummy.rs +953 -0
  42. data/ext/cargo-vendor/cranelift-wasm-0.105.3/src/environ/spec.rs +953 -0
  43. data/ext/cargo-vendor/cranelift-wasm-0.105.3/src/sections_translator.rs +409 -0
  44. data/ext/cargo-vendor/cranelift-wasm-0.105.3/src/translation_utils.rs +91 -0
  45. data/ext/cargo-vendor/cranelift-wasm-0.105.3/wasmtests/icall-simd.wat +7 -0
  46. data/ext/cargo-vendor/cranelift-wasm-0.105.3/wasmtests/icall.wat +7 -0
  47. data/ext/cargo-vendor/cranelift-wasm-0.105.3/wasmtests/unreachable_code.wat +77 -0
  48. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.19/.cargo-checksum.json +1 -0
  49. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.19/Cargo.toml +49 -0
  50. data/ext/cargo-vendor/rb-sys-0.9.89/.cargo-checksum.json +1 -0
  51. data/ext/cargo-vendor/rb-sys-0.9.89/Cargo.toml +54 -0
  52. data/ext/cargo-vendor/rb-sys-0.9.89/src/lib.rs +37 -0
  53. data/ext/cargo-vendor/rb-sys-0.9.89/src/symbol.rs +31 -0
  54. data/ext/cargo-vendor/rb-sys-build-0.9.89/.cargo-checksum.json +1 -0
  55. data/ext/cargo-vendor/rb-sys-build-0.9.89/Cargo.toml +62 -0
  56. data/ext/cargo-vendor/rb-sys-build-0.9.89/src/bindings.rs +250 -0
  57. data/ext/cargo-vendor/rb-sys-build-0.9.89/src/rb_config.rs +810 -0
  58. data/ext/cargo-vendor/tokio-1.36.0/.cargo-checksum.json +1 -0
  59. data/ext/cargo-vendor/tokio-1.36.0/CHANGELOG.md +3250 -0
  60. data/ext/cargo-vendor/tokio-1.36.0/Cargo.toml +237 -0
  61. data/ext/cargo-vendor/tokio-1.36.0/README.md +249 -0
  62. data/ext/cargo-vendor/tokio-1.36.0/src/doc/os.rs +68 -0
  63. data/ext/cargo-vendor/tokio-1.36.0/src/fs/open_options/mock_open_options.rs +39 -0
  64. data/ext/cargo-vendor/tokio-1.36.0/src/future/mod.rs +32 -0
  65. data/ext/cargo-vendor/tokio-1.36.0/src/io/async_fd.rs +1259 -0
  66. data/ext/cargo-vendor/tokio-1.36.0/src/io/bsd/poll_aio.rs +197 -0
  67. data/ext/cargo-vendor/tokio-1.36.0/src/io/interest.rs +345 -0
  68. data/ext/cargo-vendor/tokio-1.36.0/src/io/join.rs +117 -0
  69. data/ext/cargo-vendor/tokio-1.36.0/src/io/mod.rs +292 -0
  70. data/ext/cargo-vendor/tokio-1.36.0/src/io/poll_evented.rs +277 -0
  71. data/ext/cargo-vendor/tokio-1.36.0/src/io/stdio_common.rs +221 -0
  72. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/async_buf_read_ext.rs +351 -0
  73. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/buf_reader.rs +311 -0
  74. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/buf_writer.rs +310 -0
  75. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/chain.rs +144 -0
  76. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/copy.rs +290 -0
  77. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/empty.rs +150 -0
  78. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/flush.rs +47 -0
  79. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/mod.rs +111 -0
  80. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/read_exact.rs +69 -0
  81. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/read_line.rs +119 -0
  82. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/repeat.rs +75 -0
  83. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/shutdown.rs +46 -0
  84. data/ext/cargo-vendor/tokio-1.36.0/src/io/util/sink.rs +94 -0
  85. data/ext/cargo-vendor/tokio-1.36.0/src/lib.rs +694 -0
  86. data/ext/cargo-vendor/tokio-1.36.0/src/loom/std/atomic_u64.rs +19 -0
  87. data/ext/cargo-vendor/tokio-1.36.0/src/macros/cfg.rs +587 -0
  88. data/ext/cargo-vendor/tokio-1.36.0/src/macros/try_join.rs +218 -0
  89. data/ext/cargo-vendor/tokio-1.36.0/src/net/mod.rs +57 -0
  90. data/ext/cargo-vendor/tokio-1.36.0/src/net/tcp/listener.rs +451 -0
  91. data/ext/cargo-vendor/tokio-1.36.0/src/net/tcp/socket.rs +854 -0
  92. data/ext/cargo-vendor/tokio-1.36.0/src/net/tcp/stream.rs +1424 -0
  93. data/ext/cargo-vendor/tokio-1.36.0/src/net/udp.rs +2046 -0
  94. data/ext/cargo-vendor/tokio-1.36.0/src/net/unix/datagram/socket.rs +1593 -0
  95. data/ext/cargo-vendor/tokio-1.36.0/src/net/unix/listener.rs +221 -0
  96. data/ext/cargo-vendor/tokio-1.36.0/src/net/unix/mod.rs +39 -0
  97. data/ext/cargo-vendor/tokio-1.36.0/src/net/unix/pipe.rs +1442 -0
  98. data/ext/cargo-vendor/tokio-1.36.0/src/net/unix/socket.rs +271 -0
  99. data/ext/cargo-vendor/tokio-1.36.0/src/net/unix/stream.rs +1062 -0
  100. data/ext/cargo-vendor/tokio-1.36.0/src/net/windows/named_pipe.rs +2690 -0
  101. data/ext/cargo-vendor/tokio-1.36.0/src/process/mod.rs +1678 -0
  102. data/ext/cargo-vendor/tokio-1.36.0/src/process/unix/mod.rs +375 -0
  103. data/ext/cargo-vendor/tokio-1.36.0/src/process/unix/pidfd_reaper.rs +317 -0
  104. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/blocking/pool.rs +603 -0
  105. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/builder.rs +1335 -0
  106. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/context.rs +193 -0
  107. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/handle.rs +632 -0
  108. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/io/driver.rs +273 -0
  109. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/io/scheduled_io.rs +598 -0
  110. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/park.rs +339 -0
  111. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/current_thread/mod.rs +758 -0
  112. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/multi_thread/park.rs +232 -0
  113. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/multi_thread/queue.rs +608 -0
  114. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/multi_thread/stats.rs +140 -0
  115. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/multi_thread/worker.rs +1234 -0
  116. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/multi_thread_alt/queue.rs +595 -0
  117. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/multi_thread_alt/stats.rs +171 -0
  118. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/scheduler/multi_thread_alt/worker.rs +1597 -0
  119. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/task/core.rs +494 -0
  120. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/task/harness.rs +517 -0
  121. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/task/join.rs +370 -0
  122. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/task/list.rs +338 -0
  123. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/task/mod.rs +526 -0
  124. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/task/state.rs +616 -0
  125. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/task/trace/mod.rs +358 -0
  126. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/tests/loom_local.rs +47 -0
  127. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/tests/task_combinations.rs +488 -0
  128. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/time/entry.rs +646 -0
  129. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/time/source.rs +39 -0
  130. data/ext/cargo-vendor/tokio-1.36.0/src/runtime/time/wheel/level.rs +274 -0
  131. data/ext/cargo-vendor/tokio-1.36.0/src/signal/ctrl_c.rs +62 -0
  132. data/ext/cargo-vendor/tokio-1.36.0/src/signal/mod.rs +98 -0
  133. data/ext/cargo-vendor/tokio-1.36.0/src/signal/registry.rs +281 -0
  134. data/ext/cargo-vendor/tokio-1.36.0/src/signal/unix.rs +530 -0
  135. data/ext/cargo-vendor/tokio-1.36.0/src/signal/windows.rs +524 -0
  136. data/ext/cargo-vendor/tokio-1.36.0/src/sync/batch_semaphore.rs +752 -0
  137. data/ext/cargo-vendor/tokio-1.36.0/src/sync/broadcast.rs +1542 -0
  138. data/ext/cargo-vendor/tokio-1.36.0/src/sync/mpsc/bounded.rs +1692 -0
  139. data/ext/cargo-vendor/tokio-1.36.0/src/sync/mpsc/error.rs +149 -0
  140. data/ext/cargo-vendor/tokio-1.36.0/src/sync/mpsc/mod.rs +124 -0
  141. data/ext/cargo-vendor/tokio-1.36.0/src/sync/mpsc/unbounded.rs +603 -0
  142. data/ext/cargo-vendor/tokio-1.36.0/src/sync/mutex.rs +1395 -0
  143. data/ext/cargo-vendor/tokio-1.36.0/src/sync/oneshot.rs +1390 -0
  144. data/ext/cargo-vendor/tokio-1.36.0/src/sync/rwlock.rs +1119 -0
  145. data/ext/cargo-vendor/tokio-1.36.0/src/sync/semaphore.rs +977 -0
  146. data/ext/cargo-vendor/tokio-1.36.0/src/sync/watch.rs +1399 -0
  147. data/ext/cargo-vendor/tokio-1.36.0/src/task/join_set.rs +637 -0
  148. data/ext/cargo-vendor/tokio-1.36.0/src/task/local.rs +1233 -0
  149. data/ext/cargo-vendor/tokio-1.36.0/src/task/mod.rs +373 -0
  150. data/ext/cargo-vendor/tokio-1.36.0/src/util/idle_notified_set.rs +509 -0
  151. data/ext/cargo-vendor/tokio-1.36.0/src/util/rand.rs +95 -0
  152. data/ext/cargo-vendor/tokio-1.36.0/src/util/sharded_list.rs +149 -0
  153. data/ext/cargo-vendor/tokio-1.36.0/tests/io_async_fd.rs +836 -0
  154. data/ext/cargo-vendor/tokio-1.36.0/tests/io_copy.rs +102 -0
  155. data/ext/cargo-vendor/tokio-1.36.0/tests/io_copy_bidirectional.rs +165 -0
  156. data/ext/cargo-vendor/tokio-1.36.0/tests/io_join.rs +83 -0
  157. data/ext/cargo-vendor/tokio-1.36.0/tests/io_panic.rs +177 -0
  158. data/ext/cargo-vendor/tokio-1.36.0/tests/io_poll_aio.rs +338 -0
  159. data/ext/cargo-vendor/tokio-1.36.0/tests/io_repeat.rs +18 -0
  160. data/ext/cargo-vendor/tokio-1.36.0/tests/io_sink.rs +44 -0
  161. data/ext/cargo-vendor/tokio-1.36.0/tests/join_handle_panic.rs +21 -0
  162. data/ext/cargo-vendor/tokio-1.36.0/tests/macros_test.rs +94 -0
  163. data/ext/cargo-vendor/tokio-1.36.0/tests/macros_try_join.rs +185 -0
  164. data/ext/cargo-vendor/tokio-1.36.0/tests/net_named_pipe.rs +399 -0
  165. data/ext/cargo-vendor/tokio-1.36.0/tests/net_panic.rs +189 -0
  166. data/ext/cargo-vendor/tokio-1.36.0/tests/net_unix_pipe.rs +534 -0
  167. data/ext/cargo-vendor/tokio-1.36.0/tests/process_change_of_runtime.rs +34 -0
  168. data/ext/cargo-vendor/tokio-1.36.0/tests/process_issue_2174.rs +46 -0
  169. data/ext/cargo-vendor/tokio-1.36.0/tests/rt_basic.rs +458 -0
  170. data/ext/cargo-vendor/tokio-1.36.0/tests/rt_handle.rs +94 -0
  171. data/ext/cargo-vendor/tokio-1.36.0/tests/rt_panic.rs +78 -0
  172. data/ext/cargo-vendor/tokio-1.36.0/tests/rt_time_start_paused.rs +14 -0
  173. data/ext/cargo-vendor/tokio-1.36.0/tests/signal_panic.rs +30 -0
  174. data/ext/cargo-vendor/tokio-1.36.0/tests/sync_mpsc.rs +1020 -0
  175. data/ext/cargo-vendor/tokio-1.36.0/tests/sync_panic.rs +198 -0
  176. data/ext/cargo-vendor/tokio-1.36.0/tests/sync_watch.rs +334 -0
  177. data/ext/cargo-vendor/tokio-1.36.0/tests/task_id.rs +302 -0
  178. data/ext/cargo-vendor/tokio-1.36.0/tests/task_join_set.rs +306 -0
  179. data/ext/cargo-vendor/tokio-1.36.0/tests/task_local.rs +119 -0
  180. data/ext/cargo-vendor/tokio-1.36.0/tests/task_panic.rs +123 -0
  181. data/ext/cargo-vendor/tokio-1.36.0/tests/tcp_into_split.rs +131 -0
  182. data/ext/cargo-vendor/tokio-1.36.0/tests/time_panic.rs +94 -0
  183. data/ext/cargo-vendor/tokio-1.36.0/tests/time_pause.rs +332 -0
  184. data/ext/cargo-vendor/tokio-1.36.0/tests/uds_socket.rs +118 -0
  185. data/ext/cargo-vendor/wasi-common-18.0.3/.cargo-checksum.json +1 -0
  186. data/ext/cargo-vendor/wasi-common-18.0.3/Cargo.toml +223 -0
  187. data/ext/cargo-vendor/wasi-common-18.0.3/src/lib.rs +193 -0
  188. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/clocks.rs +41 -0
  189. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/dir.rs +462 -0
  190. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/file.rs +248 -0
  191. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/mod.rs +140 -0
  192. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/net.rs +400 -0
  193. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/sched/unix.rs +82 -0
  194. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/sched/windows.rs +221 -0
  195. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/sched.rs +40 -0
  196. data/ext/cargo-vendor/wasi-common-18.0.3/src/sync/stdio.rs +197 -0
  197. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/dir.rs +221 -0
  198. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/file.rs +244 -0
  199. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/mod.rs +137 -0
  200. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/net.rs +6 -0
  201. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/sched/unix.rs +96 -0
  202. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/sched/windows.rs +15 -0
  203. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/sched.rs +35 -0
  204. data/ext/cargo-vendor/wasi-common-18.0.3/src/tokio/stdio.rs +1 -0
  205. data/ext/cargo-vendor/wasi-common-18.0.3/tests/all/async_.rs +289 -0
  206. data/ext/cargo-vendor/wasi-common-18.0.3/tests/all/main.rs +21 -0
  207. data/ext/cargo-vendor/wasi-common-18.0.3/tests/all/sync.rs +275 -0
  208. data/ext/cargo-vendor/wasm-encoder-0.201.0/.cargo-checksum.json +1 -0
  209. data/ext/cargo-vendor/wasm-encoder-0.201.0/Cargo.toml +43 -0
  210. data/ext/cargo-vendor/wasm-encoder-0.201.0/src/component/names.rs +149 -0
  211. data/ext/cargo-vendor/wasm-encoder-0.201.0/src/component/types.rs +792 -0
  212. data/ext/cargo-vendor/wasm-encoder-0.201.0/src/core/code.rs +3444 -0
  213. data/ext/cargo-vendor/wasm-encoder-0.201.0/src/core/names.rs +298 -0
  214. data/ext/cargo-vendor/wasm-encoder-0.201.0/src/core/types.rs +673 -0
  215. data/ext/cargo-vendor/wasm-encoder-0.41.2/.cargo-checksum.json +1 -0
  216. data/ext/cargo-vendor/wasm-encoder-0.41.2/Cargo.toml +43 -0
  217. data/ext/cargo-vendor/wasm-encoder-0.41.2/README.md +80 -0
  218. data/ext/cargo-vendor/wasm-encoder-0.41.2/src/component/aliases.rs +160 -0
  219. data/ext/cargo-vendor/wasm-encoder-0.41.2/src/component/builder.rs +455 -0
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  892. data/ext/cargo-vendor/winch-codegen-0.15.1/src/codegen/call.rs +0 -345
  893. data/ext/cargo-vendor/winch-codegen-0.15.1/src/codegen/context.rs +0 -553
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  903. data/ext/cargo-vendor/winch-codegen-0.15.1/src/isa/x64/abi.rs +0 -524
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  911. data/ext/cargo-vendor/wit-parser-0.13.0/.cargo-checksum.json +0 -1
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  928. /data/ext/cargo-vendor/{cranelift-bforest-0.104.1 → cranelift-bforest-0.105.3}/src/node.rs +0 -0
  929. /data/ext/cargo-vendor/{cranelift-bforest-0.104.1 → cranelift-bforest-0.105.3}/src/path.rs +0 -0
  930. /data/ext/cargo-vendor/{cranelift-bforest-0.104.1 → cranelift-bforest-0.105.3}/src/pool.rs +0 -0
  931. /data/ext/cargo-vendor/{cranelift-bforest-0.104.1 → cranelift-bforest-0.105.3}/src/set.rs +0 -0
  932. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/LICENSE +0 -0
  933. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/README.md +0 -0
  934. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/benches/x64-evex-encoding.rs +0 -0
  935. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/alias_analysis.rs +0 -0
  936. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/binemit/mod.rs +0 -0
  937. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/binemit/stack_map.rs +0 -0
  938. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/bitset.rs +0 -0
  939. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/cfg_printer.rs +0 -0
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  941. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/context.rs +0 -0
  942. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/ctxhash.rs +0 -0
  943. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/cursor.rs +0 -0
  944. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/data_value.rs +0 -0
  945. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/dbg.rs +0 -0
  946. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/dce.rs +0 -0
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  951. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/fx.rs +0 -0
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  981. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/aarch64/abi.rs +0 -0
  982. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/aarch64/inst/args.rs +0 -0
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  986. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/aarch64/inst/mod.rs +0 -0
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  1031. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1032. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/s390x/lower/isle.rs +0 -0
  1033. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/s390x/lower.isle +0 -0
  1034. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/s390x/lower.rs +0 -0
  1035. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/s390x/mod.rs +0 -0
  1036. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/s390x/settings.rs +0 -0
  1037. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/unwind/systemv.rs +0 -0
  1038. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/unwind/winx64.rs +0 -0
  1039. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/unwind.rs +0 -0
  1040. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/abi.rs +0 -0
  1041. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/encoding/evex.rs +0 -0
  1042. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/encoding/mod.rs +0 -0
  1043. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/encoding/rex.rs +0 -0
  1044. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/encoding/vex.rs +0 -0
  1045. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/inst/args.rs +0 -0
  1046. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/inst/emit_state.rs +0 -0
  1047. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/inst/mod.rs +0 -0
  1048. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/inst/regs.rs +0 -0
  1049. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1050. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1051. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/inst/unwind.rs +0 -0
  1052. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1053. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/lower/isle.rs +0 -0
  1054. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/lower.rs +0 -0
  1055. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/pcc.rs +0 -0
  1056. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isa/x64/settings.rs +0 -0
  1057. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/isle_prelude.rs +0 -0
  1058. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/iterators.rs +0 -0
  1059. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/legalizer/globalvalue.rs +0 -0
  1060. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/legalizer/mod.rs +0 -0
  1061. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/legalizer/table.rs +0 -0
  1062. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/loop_analysis.rs +0 -0
  1063. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/abi.rs +0 -0
  1064. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/blockorder.rs +0 -0
  1065. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/buffer.rs +0 -0
  1066. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/compile.rs +0 -0
  1067. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/helpers.rs +0 -0
  1068. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/inst_common.rs +0 -0
  1069. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/isle.rs +0 -0
  1070. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/lower.rs +0 -0
  1071. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/mod.rs +0 -0
  1072. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/pcc.rs +0 -0
  1073. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/valueregs.rs +0 -0
  1074. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/machinst/vcode.rs +0 -0
  1075. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/nan_canonicalization.rs +0 -0
  1076. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/arithmetic.isle +0 -0
  1077. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/bitops.isle +0 -0
  1078. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/cprop.isle +0 -0
  1079. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/generated_code.rs +0 -0
  1080. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/remat.isle +0 -0
  1081. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/selects.isle +0 -0
  1082. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/shifts.isle +0 -0
  1083. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/spaceship.isle +0 -0
  1084. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts/vector.isle +0 -0
  1085. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/opts.rs +0 -0
  1086. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/prelude.isle +0 -0
  1087. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/prelude_lower.isle +0 -0
  1088. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/print_errors.rs +0 -0
  1089. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/remove_constant_phis.rs +0 -0
  1090. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/result.rs +0 -0
  1091. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/scoped_hash_map.rs +0 -0
  1092. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/settings.rs +0 -0
  1093. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/souper_harvest.rs +0 -0
  1094. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/timing.rs +0 -0
  1095. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/unionfind.rs +0 -0
  1096. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/unreachable_code.rs +0 -0
  1097. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/value_label.rs +0 -0
  1098. /data/ext/cargo-vendor/{cranelift-codegen-0.104.1 → cranelift-codegen-0.105.3}/src/write.rs +0 -0
  1099. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/LICENSE +0 -0
  1100. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/README.md +0 -0
  1101. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/formats.rs +0 -0
  1102. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/instructions.rs +0 -0
  1103. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/isa.rs +0 -0
  1104. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/mod.rs +0 -0
  1105. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/operands.rs +0 -0
  1106. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/settings.rs +0 -0
  1107. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/types.rs +0 -0
  1108. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/cdsl/typevar.rs +0 -0
  1109. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/constant_hash.rs +0 -0
  1110. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/error.rs +0 -0
  1111. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/gen_inst.rs +0 -0
  1112. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/gen_settings.rs +0 -0
  1113. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/gen_types.rs +0 -0
  1114. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/isa/arm64.rs +0 -0
  1115. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/isa/mod.rs +0 -0
  1116. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/isa/riscv64.rs +0 -0
  1117. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/isa/s390x.rs +0 -0
  1118. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/isa/x86.rs +0 -0
  1119. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/lib.rs +0 -0
  1120. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/shared/entities.rs +0 -0
  1121. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/shared/formats.rs +0 -0
  1122. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/shared/immediates.rs +0 -0
  1123. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/shared/instructions.rs +0 -0
  1124. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/shared/mod.rs +0 -0
  1125. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/shared/settings.rs +0 -0
  1126. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/shared/types.rs +0 -0
  1127. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/srcgen.rs +0 -0
  1128. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.104.1 → cranelift-codegen-meta-0.105.3}/src/unique_table.rs +0 -0
  1129. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.104.1 → cranelift-codegen-shared-0.105.3}/LICENSE +0 -0
  1130. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.104.1 → cranelift-codegen-shared-0.105.3}/README.md +0 -0
  1131. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.104.1 → cranelift-codegen-shared-0.105.3}/src/constant_hash.rs +0 -0
  1132. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.104.1 → cranelift-codegen-shared-0.105.3}/src/constants.rs +0 -0
  1133. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.104.1 → cranelift-codegen-shared-0.105.3}/src/lib.rs +0 -0
  1134. /data/ext/cargo-vendor/{cranelift-control-0.104.1 → cranelift-control-0.105.3}/LICENSE +0 -0
  1135. /data/ext/cargo-vendor/{cranelift-control-0.104.1 → cranelift-control-0.105.3}/README.md +0 -0
  1136. /data/ext/cargo-vendor/{cranelift-control-0.104.1 → cranelift-control-0.105.3}/src/chaos.rs +0 -0
  1137. /data/ext/cargo-vendor/{cranelift-control-0.104.1 → cranelift-control-0.105.3}/src/lib.rs +0 -0
  1138. /data/ext/cargo-vendor/{cranelift-control-0.104.1 → cranelift-control-0.105.3}/src/zero_sized.rs +0 -0
  1139. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/LICENSE +0 -0
  1140. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/README.md +0 -0
  1141. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/boxed_slice.rs +0 -0
  1142. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/iter.rs +0 -0
  1143. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/keys.rs +0 -0
  1144. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/lib.rs +0 -0
  1145. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/list.rs +0 -0
  1146. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/map.rs +0 -0
  1147. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/packed_option.rs +0 -0
  1148. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/primary.rs +0 -0
  1149. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/set.rs +0 -0
  1150. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/sparse.rs +0 -0
  1151. /data/ext/cargo-vendor/{cranelift-entity-0.104.1 → cranelift-entity-0.105.3}/src/unsigned.rs +0 -0
  1152. /data/ext/cargo-vendor/{cranelift-frontend-0.104.1 → cranelift-frontend-0.105.3}/LICENSE +0 -0
  1153. /data/ext/cargo-vendor/{cranelift-frontend-0.104.1 → cranelift-frontend-0.105.3}/README.md +0 -0
  1154. /data/ext/cargo-vendor/{cranelift-frontend-0.104.1 → cranelift-frontend-0.105.3}/src/frontend.rs +0 -0
  1155. /data/ext/cargo-vendor/{cranelift-frontend-0.104.1 → cranelift-frontend-0.105.3}/src/lib.rs +0 -0
  1156. /data/ext/cargo-vendor/{cranelift-frontend-0.104.1 → cranelift-frontend-0.105.3}/src/ssa.rs +0 -0
  1157. /data/ext/cargo-vendor/{cranelift-frontend-0.104.1 → cranelift-frontend-0.105.3}/src/switch.rs +0 -0
  1158. /data/ext/cargo-vendor/{cranelift-frontend-0.104.1 → cranelift-frontend-0.105.3}/src/variable.rs +0 -0
  1159. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/README.md +0 -0
  1160. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/build.rs +0 -0
  1161. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/bad_converters.isle +0 -0
  1162. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1163. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1164. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/error1.isle +0 -0
  1165. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/extra_parens.isle +0 -0
  1166. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/impure_expression.isle +0 -0
  1167. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/impure_rhs.isle +0 -0
  1168. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1169. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/fail/multi_prio.isle +0 -0
  1170. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/borrows.isle +0 -0
  1171. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/borrows_main.rs +0 -0
  1172. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/iflets.isle +0 -0
  1173. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/iflets_main.rs +0 -0
  1174. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/multi_constructor.isle +0 -0
  1175. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/multi_constructor_main.rs +0 -0
  1176. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/multi_extractor.isle +0 -0
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  1179. /data/ext/cargo-vendor/{cranelift-isle-0.104.1 → cranelift-isle-0.105.3}/isle_examples/link/test_main.rs +0 -0
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  1272. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.18 → deterministic-wasi-ctx-0.1.19}/src/clocks.rs +0 -0
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  1277. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.18 → deterministic-wasi-ctx-0.1.19}/tests/random.rs +0 -0
  1278. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.18 → deterministic-wasi-ctx-0.1.19}/tests/scheduler.rs +0 -0
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  1280. /data/ext/cargo-vendor/{rb-sys-0.9.86 → rb-sys-0.9.89}/LICENSE-MIT +0 -0
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  1329. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/mocks.rs +0 -0
  1330. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/mod.rs +0 -0
  1331. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/open_options.rs +0 -0
  1332. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/read.rs +0 -0
  1333. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/read_dir.rs +0 -0
  1334. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/read_link.rs +0 -0
  1335. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/read_to_string.rs +0 -0
  1336. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/remove_dir.rs +0 -0
  1337. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/remove_dir_all.rs +0 -0
  1338. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/remove_file.rs +0 -0
  1339. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/rename.rs +0 -0
  1340. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/set_permissions.rs +0 -0
  1341. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/symlink.rs +0 -0
  1342. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/symlink_dir.rs +0 -0
  1343. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/symlink_file.rs +0 -0
  1344. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/symlink_metadata.rs +0 -0
  1345. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/try_exists.rs +0 -0
  1346. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fs/write.rs +0 -0
  1347. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/future/block_on.rs +0 -0
  1348. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/future/maybe_done.rs +0 -0
  1349. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/future/poll_fn.rs +0 -0
  1350. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/future/trace.rs +0 -0
  1351. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/future/try_join.rs +0 -0
  1352. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/fuzz.rs +0 -0
  1353. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/async_buf_read.rs +0 -0
  1354. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/async_read.rs +0 -0
  1355. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/async_seek.rs +0 -0
  1356. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/async_write.rs +0 -0
  1357. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/blocking.rs +0 -0
  1358. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/read_buf.rs +0 -0
  1359. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/ready.rs +0 -0
  1360. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/seek.rs +0 -0
  1361. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/split.rs +0 -0
  1362. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/stderr.rs +0 -0
  1363. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/stdin.rs +0 -0
  1364. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/stdout.rs +0 -0
  1365. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/async_read_ext.rs +0 -0
  1366. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/async_seek_ext.rs +0 -0
  1367. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/async_write_ext.rs +0 -0
  1368. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/buf_stream.rs +0 -0
  1369. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/copy_bidirectional.rs +0 -0
  1370. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/copy_buf.rs +0 -0
  1371. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/fill_buf.rs +0 -0
  1372. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/lines.rs +0 -0
  1373. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/mem.rs +0 -0
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  1377. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/read_to_end.rs +0 -0
  1378. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/read_to_string.rs +0 -0
  1379. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/read_until.rs +0 -0
  1380. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/split.rs +0 -0
  1381. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/take.rs +0 -0
  1382. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/vec_with_initialized.rs +0 -0
  1383. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/write.rs +0 -0
  1384. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/write_all.rs +0 -0
  1385. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/write_all_buf.rs +0 -0
  1386. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/write_buf.rs +0 -0
  1387. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/write_int.rs +0 -0
  1388. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/io/util/write_vectored.rs +0 -0
  1389. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/loom/mocked.rs +0 -0
  1390. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/loom/mod.rs +0 -0
  1391. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/loom/std/atomic_u16.rs +0 -0
  1392. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/loom/std/atomic_u32.rs +0 -0
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  1397. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/loom/std/atomic_usize.rs +0 -0
  1398. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/loom/std/barrier.rs +0 -0
  1399. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/loom/std/mod.rs +0 -0
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  1405. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/macros/loom.rs +0 -0
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  1411. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/macros/thread_local.rs +0 -0
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  1414. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/net/lookup_host.rs +0 -0
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  1418. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/net/unix/datagram/mod.rs +0 -0
  1419. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/net/unix/socketaddr.rs +0 -0
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  1422. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/net/unix/ucred.rs +0 -0
  1423. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/net/windows/mod.rs +0 -0
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  1425. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/process/unix/orphan.rs +0 -0
  1426. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/process/unix/reap.rs +0 -0
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  1430. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/blocking/shutdown.rs +0 -0
  1431. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/blocking/task.rs +0 -0
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  1454. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/metrics/worker.rs +0 -0
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  1459. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/defer.rs +0 -0
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  1463. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/inject/shared.rs +0 -0
  1464. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/inject/synced.rs +0 -0
  1465. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/inject.rs +0 -0
  1466. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/lock.rs +0 -0
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  1468. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/counters.rs +0 -0
  1469. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/handle/metrics.rs +0 -0
  1470. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/handle/taskdump.rs +0 -0
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  1473. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/mod.rs +0 -0
  1474. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/overflow.rs +0 -0
  1475. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/trace.rs +0 -0
  1476. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/trace_mock.rs +0 -0
  1477. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/worker/metrics.rs +0 -0
  1478. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/worker/taskdump.rs +0 -0
  1479. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread/worker/taskdump_mock.rs +0 -0
  1480. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/counters.rs +0 -0
  1481. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/handle/metrics.rs +0 -0
  1482. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/handle/taskdump.rs +0 -0
  1483. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/handle.rs +0 -0
  1484. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/idle.rs +0 -0
  1485. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/mod.rs +0 -0
  1486. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/overflow.rs +0 -0
  1487. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/park.rs +0 -0
  1488. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/trace.rs +0 -0
  1489. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/trace_mock.rs +0 -0
  1490. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/worker/metrics.rs +0 -0
  1491. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/worker/taskdump.rs +0 -0
  1492. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/scheduler/multi_thread_alt/worker/taskdump_mock.rs +0 -0
  1493. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/signal/mod.rs +0 -0
  1494. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/task/abort.rs +0 -0
  1495. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/task/error.rs +0 -0
  1496. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/task/id.rs +0 -0
  1497. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/task/raw.rs +0 -0
  1498. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/task/trace/symbol.rs +0 -0
  1499. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/task/trace/tree.rs +0 -0
  1500. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/task/waker.rs +0 -0
  1501. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/inject.rs +0 -0
  1502. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_blocking.rs +0 -0
  1503. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_current_thread/yield_now.rs +0 -0
  1504. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_current_thread.rs +0 -0
  1505. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_join_set.rs +0 -0
  1506. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread/queue.rs +0 -0
  1507. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread/shutdown.rs +0 -0
  1508. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread/yield_now.rs +0 -0
  1509. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread.rs +0 -0
  1510. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread_alt/queue.rs +0 -0
  1511. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread_alt/shutdown.rs +0 -0
  1512. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread_alt/yield_now.rs +0 -0
  1513. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_multi_thread_alt.rs +0 -0
  1514. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/loom_oneshot.rs +0 -0
  1515. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/mod.rs +0 -0
  1516. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/queue.rs +0 -0
  1517. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/tests/task.rs +0 -0
  1518. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/thread_id.rs +0 -0
  1519. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/time/handle.rs +0 -0
  1520. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/time/mod.rs +0 -0
  1521. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/time/tests/mod.rs +0 -0
  1522. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/runtime/time/wheel/mod.rs +0 -0
  1523. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/signal/reusable_box.rs +0 -0
  1524. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/signal/windows/stub.rs +0 -0
  1525. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/signal/windows/sys.rs +0 -0
  1526. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/barrier.rs +0 -0
  1527. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/mod.rs +0 -0
  1528. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/mpsc/block.rs +0 -0
  1529. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/mpsc/chan.rs +0 -0
  1530. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/mpsc/list.rs +0 -0
  1531. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/notify.rs +0 -0
  1532. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/once_cell.rs +0 -0
  1533. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/rwlock/owned_read_guard.rs +0 -0
  1534. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/rwlock/owned_write_guard.rs +0 -0
  1535. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/rwlock/owned_write_guard_mapped.rs +0 -0
  1536. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/rwlock/read_guard.rs +0 -0
  1537. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/rwlock/write_guard.rs +0 -0
  1538. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/rwlock/write_guard_mapped.rs +0 -0
  1539. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/task/atomic_waker.rs +0 -0
  1540. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/task/mod.rs +0 -0
  1541. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/atomic_waker.rs +0 -0
  1542. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_atomic_waker.rs +0 -0
  1543. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_broadcast.rs +0 -0
  1544. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_list.rs +0 -0
  1545. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_mpsc.rs +0 -0
  1546. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_notify.rs +0 -0
  1547. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_oneshot.rs +0 -0
  1548. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_rwlock.rs +0 -0
  1549. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_semaphore_batch.rs +0 -0
  1550. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/loom_watch.rs +0 -0
  1551. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/mod.rs +0 -0
  1552. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/notify.rs +0 -0
  1553. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/sync/tests/semaphore_batch.rs +0 -0
  1554. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/task/blocking.rs +0 -0
  1555. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/task/builder.rs +0 -0
  1556. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/task/consume_budget.rs +0 -0
  1557. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/task/spawn.rs +0 -0
  1558. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/task/task_local.rs +0 -0
  1559. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/task/unconstrained.rs +0 -0
  1560. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/task/yield_now.rs +0 -0
  1561. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/time/clock.rs +0 -0
  1562. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/time/error.rs +0 -0
  1563. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/time/instant.rs +0 -0
  1564. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/time/interval.rs +0 -0
  1565. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/time/mod.rs +0 -0
  1566. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/time/sleep.rs +0 -0
  1567. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/time/timeout.rs +0 -0
  1568. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/atomic_cell.rs +0 -0
  1569. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/bit.rs +0 -0
  1570. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/cacheline.rs +0 -0
  1571. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/error.rs +0 -0
  1572. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/linked_list.rs +0 -0
  1573. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/markers.rs +0 -0
  1574. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/memchr.rs +0 -0
  1575. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/mod.rs +0 -0
  1576. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/once_cell.rs +0 -0
  1577. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/rand/rt.rs +0 -0
  1578. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/rand/rt_unstable.rs +0 -0
  1579. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/rc_cell.rs +0 -0
  1580. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/sync_wrapper.rs +0 -0
  1581. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/trace.rs +0 -0
  1582. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/try_lock.rs +0 -0
  1583. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/wake.rs +0 -0
  1584. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/src/util/wake_list.rs +0 -0
  1585. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/_require_full.rs +0 -0
  1586. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/async_send_sync.rs +0 -0
  1587. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/buffered.rs +0 -0
  1588. /data/ext/cargo-vendor/{tokio-1.35.1/tests/coop_budger.rs → tokio-1.36.0/tests/coop_budget.rs} +0 -0
  1589. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/dump.rs +0 -0
  1590. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/duplex_stream.rs +0 -0
  1591. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs.rs +0 -0
  1592. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_canonicalize_dir.rs +0 -0
  1593. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_copy.rs +0 -0
  1594. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_dir.rs +0 -0
  1595. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_file.rs +0 -0
  1596. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_link.rs +0 -0
  1597. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_open_options.rs +0 -0
  1598. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_open_options_windows.rs +0 -0
  1599. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_remove_dir_all.rs +0 -0
  1600. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_remove_file.rs +0 -0
  1601. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_rename.rs +0 -0
  1602. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_symlink_dir_windows.rs +0 -0
  1603. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_symlink_file_windows.rs +0 -0
  1604. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/fs_try_exists.rs +0 -0
  1605. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_async_read.rs +0 -0
  1606. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_buf_reader.rs +0 -0
  1607. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_buf_writer.rs +0 -0
  1608. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_chain.rs +0 -0
  1609. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_driver.rs +0 -0
  1610. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_driver_drop.rs +0 -0
  1611. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_fill_buf.rs +0 -0
  1612. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_lines.rs +0 -0
  1613. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_mem_stream.rs +0 -0
  1614. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_read.rs +0 -0
  1615. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_read_buf.rs +0 -0
  1616. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_read_exact.rs +0 -0
  1617. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_read_line.rs +0 -0
  1618. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_read_to_end.rs +0 -0
  1619. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_read_to_string.rs +0 -0
  1620. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_read_until.rs +0 -0
  1621. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_split.rs +0 -0
  1622. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_take.rs +0 -0
  1623. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_util_empty.rs +0 -0
  1624. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_write.rs +0 -0
  1625. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_write_all.rs +0 -0
  1626. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_write_all_buf.rs +0 -0
  1627. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_write_buf.rs +0 -0
  1628. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/io_write_int.rs +0 -0
  1629. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/macros_join.rs +0 -0
  1630. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/macros_pin.rs +0 -0
  1631. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/macros_rename_test.rs +0 -0
  1632. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/macros_select.rs +0 -0
  1633. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/net_bind_resource.rs +0 -0
  1634. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/net_lookup_host.rs +0 -0
  1635. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/no_rt.rs +0 -0
  1636. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/process_arg0.rs +0 -0
  1637. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/process_issue_42.rs +0 -0
  1638. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/process_kill_on_drop.rs +0 -0
  1639. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/process_raw_handle.rs +0 -0
  1640. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/process_smoke.rs +0 -0
  1641. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/rt_common.rs +0 -0
  1642. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/rt_handle_block_on.rs +0 -0
  1643. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/rt_metrics.rs +0 -0
  1644. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/rt_threaded.rs +0 -0
  1645. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/rt_threaded_alt.rs +0 -0
  1646. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_ctrl_c.rs +0 -0
  1647. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_drop_recv.rs +0 -0
  1648. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_drop_rt.rs +0 -0
  1649. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_drop_signal.rs +0 -0
  1650. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_multi_rt.rs +0 -0
  1651. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_no_rt.rs +0 -0
  1652. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_notify_both.rs +0 -0
  1653. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_twice.rs +0 -0
  1654. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/signal_usr1.rs +0 -0
  1655. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/support/io_vec.rs +0 -0
  1656. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/support/leaked_buffers.rs +0 -0
  1657. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/support/mpsc_stream.rs +0 -0
  1658. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/support/panic.rs +0 -0
  1659. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/support/signal.rs +0 -0
  1660. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_barrier.rs +0 -0
  1661. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_broadcast.rs +0 -0
  1662. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_errors.rs +0 -0
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  1665. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_mutex_owned.rs +0 -0
  1666. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_notify.rs +0 -0
  1667. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_once_cell.rs +0 -0
  1668. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_oneshot.rs +0 -0
  1669. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_rwlock.rs +0 -0
  1670. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_semaphore.rs +0 -0
  1671. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/sync_semaphore_owned.rs +0 -0
  1672. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/task_abort.rs +0 -0
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  1675. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/task_local_set.rs +0 -0
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  1677. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_accept.rs +0 -0
  1678. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_connect.rs +0 -0
  1679. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_echo.rs +0 -0
  1680. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_into_std.rs +0 -0
  1681. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_peek.rs +0 -0
  1682. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_shutdown.rs +0 -0
  1683. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_socket.rs +0 -0
  1684. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_split.rs +0 -0
  1685. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/tcp_stream.rs +0 -0
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  1689. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/time_sleep.rs +0 -0
  1690. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/time_timeout.rs +0 -0
  1691. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/udp.rs +0 -0
  1692. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/uds_cred.rs +0 -0
  1693. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/uds_datagram.rs +0 -0
  1694. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/uds_split.rs +0 -0
  1695. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/uds_stream.rs +0 -0
  1696. /data/ext/cargo-vendor/{tokio-1.35.1 → tokio-1.36.0}/tests/unwindsafe.rs +0 -0
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  1723. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/WASI/snapshots/README.md +0 -0
  1724. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/WASI/standard/README.md +0 -0
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  1727. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/ctx.rs +0 -0
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  1731. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/pipe.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/random.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/sched/subscription.rs +0 -0
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  1736. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/snapshots/preview_0.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/snapshots/preview_1/error.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/snapshots/preview_1.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/string_array.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasi-common-18.0.3}/src/table.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasi-common-17.0.1 → wasm-encoder-0.201.0}/LICENSE +0 -0
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  1744. /data/ext/cargo-vendor/{wasm-encoder-0.38.1 → wasm-encoder-0.201.0}/src/component/builder.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasm-encoder-0.38.1 → wasm-encoder-0.201.0}/src/component/canonicals.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasm-encoder-0.38.1 → wasm-encoder-0.201.0}/src/component/components.rs +0 -0
  1747. /data/ext/cargo-vendor/{wasm-encoder-0.38.1 → wasm-encoder-0.201.0}/src/component/exports.rs +0 -0
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  1774. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/parser.rs +0 -0
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  1776. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/component/canonicals.rs +0 -0
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  1779. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/component/instances.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/component/names.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/component/start.rs +0 -0
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  1783. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/component.rs +0 -0
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  1786. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/custom.rs +0 -0
  1787. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/data.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/elements.rs +0 -0
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  1791. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/globals.rs +0 -0
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  1794. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/memories.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/producers.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/tables.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/tags.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmparser-0.118.1 → wasmparser-0.121.2}/src/readers/core/types/matches.rs +0 -0
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  1807. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/component/matching.rs +0 -0
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  1810. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/component/storage.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/component/store.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/coredump.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/externals/global.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/externals/table.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/externals.rs +0 -0
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  1820. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/stack.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/store/context.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/store/data.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/store/func_refs.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/trampoline/global.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/unix.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/v128.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/values.rs +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-17.0.1/src → wasmtime-18.0.3/src/runtime}/windows.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-asm-macros-17.0.1 → wasmtime-asm-macros-18.0.3}/src/lib.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/LICENSE +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/build.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/src/config/tests.rs +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/src/config.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/src/lib.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/src/tests.rs +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/src/worker/tests/system_time_stub.rs +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/src/worker/tests.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/src/worker.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-cache-17.0.1 → wasmtime-cache-18.0.3}/tests/cache_write_default_config.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/src/component.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/src/lib.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/char.wit +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/conventions.wit +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/direct-import.wit +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/empty.wit +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/flags.wit +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/floats.wit +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/function-new.wit +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/integers.wit +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/lists.wit +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/many-arguments.wit +0 -0
  1852. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/multi-return.wit +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/multiversion/deps/v1/root.wit +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/multiversion/deps/v2/root.wit +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/multiversion/root.wit +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/records.wit +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/rename.wit +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/resources-export.wit +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/resources-import.wit +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/share-types.wit +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/simple-functions.wit +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/simple-lists.wit +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/simple-wasi.wit +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/small-anonymous.wit +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/smoke-default.wit +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/smoke-export.wit +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/smoke.wit +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/strings.wit +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/use-paths.wit +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/variants.wit +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen/worlds-with-types.wit +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-component-macro-17.0.1 → wasmtime-component-macro-18.0.3}/tests/codegen.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-component-util-17.0.1 → wasmtime-component-util-18.0.3}/src/lib.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/LICENSE +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/SECURITY.md +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/gc.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/address_transform.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/attr.rs +0 -0
  1879. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/expression.rs +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/line_program.rs +0 -0
  1881. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/mod.rs +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/range_info_builder.rs +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/refs.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/unit.rs +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/transform/utils.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug/write_debuginfo.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-cranelift-17.0.1 → wasmtime-cranelift-18.0.3}/src/debug.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-17.0.1 → wasmtime-cranelift-shared-18.0.3}/src/compiled_function.rs +0 -0
  1889. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-17.0.1 → wasmtime-cranelift-shared-18.0.3}/src/lib.rs +0 -0
  1890. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-17.0.1 → wasmtime-cranelift-shared-18.0.3}/src/obj.rs +0 -0
  1891. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/LICENSE +0 -0
  1892. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/examples/factc.rs +0 -0
  1893. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/address_map.rs +0 -0
  1894. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/builtin.rs +0 -0
  1895. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/compilation.rs +0 -0
  1896. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/component/compiler.rs +0 -0
  1897. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/component/translate/adapt.rs +0 -0
  1898. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/component/types/resources.rs +0 -0
  1899. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/component/vmcomponent_offsets.rs +0 -0
  1900. /data/ext/cargo-vendor/{wasmtime-jit-17.0.1 → wasmtime-environ-18.0.3}/src/demangling.rs +0 -0
  1901. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/fact/core_types.rs +0 -0
  1902. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/fact/signature.rs +0 -0
  1903. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/fact/trampoline.rs +0 -0
  1904. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/fact/transcode.rs +0 -0
  1905. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/fact/traps.rs +0 -0
  1906. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/fact.rs +0 -0
  1907. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/obj.rs +0 -0
  1908. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/ref_bits.rs +0 -0
  1909. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/scopevec.rs +0 -0
  1910. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/stack_map.rs +0 -0
  1911. /data/ext/cargo-vendor/{wasmtime-environ-17.0.1 → wasmtime-environ-18.0.3}/src/trap_encoding.rs +0 -0
  1912. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/LICENSE +0 -0
  1913. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/build.rs +0 -0
  1914. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/lib.rs +0 -0
  1915. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/unix/aarch64.rs +0 -0
  1916. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/unix/arm.rs +0 -0
  1917. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/unix/riscv64.rs +0 -0
  1918. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/unix/s390x.S +0 -0
  1919. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/unix/x86.rs +0 -0
  1920. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/unix/x86_64.rs +0 -0
  1921. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/unix.rs +0 -0
  1922. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/windows.c +0 -0
  1923. /data/ext/cargo-vendor/{wasmtime-fiber-17.0.1 → wasmtime-fiber-18.0.3}/src/windows.rs +0 -0
  1924. /data/ext/cargo-vendor/{wasmtime-jit-debug-17.0.1 → wasmtime-jit-debug-18.0.3}/README.md +0 -0
  1925. /data/ext/cargo-vendor/{wasmtime-jit-debug-17.0.1 → wasmtime-jit-debug-18.0.3}/src/gdb_jit_int.rs +0 -0
  1926. /data/ext/cargo-vendor/{wasmtime-jit-debug-17.0.1 → wasmtime-jit-debug-18.0.3}/src/lib.rs +0 -0
  1927. /data/ext/cargo-vendor/{wasmtime-jit-debug-17.0.1 → wasmtime-jit-debug-18.0.3}/src/perf_jitdump.rs +0 -0
  1928. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-17.0.1 → wasmtime-jit-icache-coherence-18.0.3}/src/lib.rs +0 -0
  1929. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-17.0.1 → wasmtime-jit-icache-coherence-18.0.3}/src/libc.rs +0 -0
  1930. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-17.0.1 → wasmtime-jit-icache-coherence-18.0.3}/src/miri.rs +0 -0
  1931. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-17.0.1 → wasmtime-jit-icache-coherence-18.0.3}/src/win.rs +0 -0
  1932. /data/ext/cargo-vendor/{wasmtime-jit-17.0.1 → wasmtime-runtime-18.0.3}/LICENSE +0 -0
  1933. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/build.rs +0 -0
  1934. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/proptest-regressions/instance/allocator/pooling/memory_pool.txt +0 -0
  1935. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/arch/aarch64.rs +0 -0
  1936. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/arch/mod.rs +0 -0
  1937. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/arch/riscv64.rs +0 -0
  1938. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/arch/s390x.S +0 -0
  1939. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/arch/s390x.rs +0 -0
  1940. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/arch/x86_64.rs +0 -0
  1941. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/component/libcalls.rs +0 -0
  1942. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/component/resources.rs +0 -0
  1943. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/cow.rs +0 -0
  1944. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/debug_builtins.rs +0 -0
  1945. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/export.rs +0 -0
  1946. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/externref.rs +0 -0
  1947. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/helpers.c +0 -0
  1948. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/imports.rs +0 -0
  1949. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/instance/allocator/on_demand.rs +0 -0
  1950. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1951. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/instance/allocator/pooling/stack_pool.rs +0 -0
  1952. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/instance/allocator/pooling/table_pool.rs +0 -0
  1953. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/libcalls.rs +0 -0
  1954. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/memory.rs +0 -0
  1955. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/mmap.rs +0 -0
  1956. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/mmap_vec.rs +0 -0
  1957. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/module_id.rs +0 -0
  1958. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/mpk/disabled.rs +0 -0
  1959. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/mpk/mod.rs +0 -0
  1960. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/mpk/sys.rs +0 -0
  1961. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/parking_spot.rs +0 -0
  1962. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/send_sync_ptr.rs +0 -0
  1963. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/store_box.rs +0 -0
  1964. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/miri/mmap.rs +0 -0
  1965. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/miri/mod.rs +0 -0
  1966. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/miri/traphandlers.rs +0 -0
  1967. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/miri/unwind.rs +0 -0
  1968. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/miri/vm.rs +0 -0
  1969. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/mod.rs +0 -0
  1970. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/unix/machports.rs +0 -0
  1971. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/unix/macos_traphandlers.rs +0 -0
  1972. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/unix/mmap.rs +0 -0
  1973. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/unix/mod.rs +0 -0
  1974. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/unix/unwind.rs +0 -0
  1975. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/unix/vm.rs +0 -0
  1976. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/windows/mmap.rs +0 -0
  1977. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/windows/mod.rs +0 -0
  1978. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/windows/traphandlers.rs +0 -0
  1979. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/windows/unwind.rs +0 -0
  1980. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/sys/windows/vm.rs +0 -0
  1981. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/table.rs +0 -0
  1982. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/traphandlers/backtrace.rs +0 -0
  1983. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/traphandlers/coredump.rs +0 -0
  1984. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/traphandlers.rs +0 -0
  1985. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-runtime-18.0.3}/src/vmcontext/vm_host_func_context.rs +0 -0
  1986. /data/ext/cargo-vendor/{wasmtime-runtime-17.0.1 → wasmtime-types-18.0.3}/LICENSE +0 -0
  1987. /data/ext/cargo-vendor/{wasmtime-types-17.0.1 → wasmtime-types-18.0.3}/src/error.rs +0 -0
  1988. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-17.0.1 → wasmtime-versioned-export-macros-18.0.3}/src/lib.rs +0 -0
  1989. /data/ext/cargo-vendor/{wasmtime-types-17.0.1 → wasmtime-wasi-18.0.3}/LICENSE +0 -0
  1990. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/README.md +0 -0
  1991. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/command.rs +0 -0
  1992. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/host/env.rs +0 -0
  1993. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/host/exit.rs +0 -0
  1994. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/host/filesystem/sync.rs +0 -0
  1995. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/host/mod.rs +0 -0
  1996. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/mod.rs +0 -0
  1997. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/network.rs +0 -0
  1998. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/stdio/worker_thread_stdin.rs +0 -0
  1999. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/stream.rs +0 -0
  2000. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/tcp.rs +0 -0
  2001. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/src/preview2/udp.rs +0 -0
  2002. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/tests/all/async_.rs +0 -0
  2003. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/tests/all/preview1.rs +0 -0
  2004. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/tests/all/sync.rs +0 -0
  2005. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/tests/process_stdin.rs +0 -0
  2006. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/command-extended.wit +0 -0
  2007. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/cli/command.wit +0 -0
  2008. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/cli/environment.wit +0 -0
  2009. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/cli/exit.wit +0 -0
  2010. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/cli/imports.wit +0 -0
  2011. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/cli/run.wit +0 -0
  2012. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/cli/stdio.wit +0 -0
  2013. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/cli/terminal.wit +0 -0
  2014. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/clocks/monotonic-clock.wit +0 -0
  2015. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/clocks/wall-clock.wit +0 -0
  2016. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/clocks/world.wit +0 -0
  2017. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/filesystem/preopens.wit +0 -0
  2018. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/filesystem/types.wit +0 -0
  2019. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/filesystem/world.wit +0 -0
  2020. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/http/handler.wit +0 -0
  2021. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/http/proxy.wit +0 -0
  2022. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/http/types.wit +0 -0
  2023. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/io/error.wit +0 -0
  2024. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/io/world.wit +0 -0
  2025. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/random/insecure-seed.wit +0 -0
  2026. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/random/insecure.wit +0 -0
  2027. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/random/random.wit +0 -0
  2028. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/random/world.wit +0 -0
  2029. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/sockets/instance-network.wit +0 -0
  2030. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/sockets/ip-name-lookup.wit +0 -0
  2031. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/sockets/network.wit +0 -0
  2032. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/sockets/tcp-create-socket.wit +0 -0
  2033. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/sockets/udp-create-socket.wit +0 -0
  2034. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/deps/sockets/world.wit +0 -0
  2035. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/wit/test.wit +0 -0
  2036. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/witx/preview0/typenames.witx +0 -0
  2037. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/witx/preview0/wasi_unstable.witx +0 -0
  2038. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/witx/preview1/typenames.witx +0 -0
  2039. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wasmtime-wasi-18.0.3}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  2040. /data/ext/cargo-vendor/{wasmtime-winch-17.0.1 → wasmtime-winch-18.0.3}/LICENSE +0 -0
  2041. /data/ext/cargo-vendor/{wasmtime-winch-17.0.1 → wasmtime-winch-18.0.3}/src/lib.rs +0 -0
  2042. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-17.0.1 → wasmtime-wit-bindgen-18.0.3}/src/rust.rs +0 -0
  2043. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-17.0.1 → wasmtime-wit-bindgen-18.0.3}/src/source.rs +0 -0
  2044. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-17.0.1 → wasmtime-wit-bindgen-18.0.3}/src/types.rs +0 -0
  2045. /data/ext/cargo-vendor/{wasmtime-wmemcheck-17.0.1 → wasmtime-wmemcheck-18.0.3}/src/lib.rs +0 -0
  2046. /data/ext/cargo-vendor/{wasmtime-wasi-17.0.1 → wast-201.0.0}/LICENSE +0 -0
  2047. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/README.md +0 -0
  2048. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/alias.rs +0 -0
  2049. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/binary.rs +0 -0
  2050. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/custom.rs +0 -0
  2051. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/expand.rs +0 -0
  2052. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/export.rs +0 -0
  2053. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/func.rs +0 -0
  2054. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/import.rs +0 -0
  2055. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/instance.rs +0 -0
  2056. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/item_ref.rs +0 -0
  2057. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/module.rs +0 -0
  2058. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/resolve.rs +0 -0
  2059. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/types.rs +0 -0
  2060. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component/wast.rs +0 -0
  2061. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/component.rs +0 -0
  2062. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/export.rs +0 -0
  2063. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/func.rs +0 -0
  2064. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/global.rs +0 -0
  2065. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/import.rs +0 -0
  2066. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/resolve/mod.rs +0 -0
  2067. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/resolve/types.rs +0 -0
  2068. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/tag.rs +0 -0
  2069. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core/wast.rs +0 -0
  2070. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/core.rs +0 -0
  2071. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/encode.rs +0 -0
  2072. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/error.rs +0 -0
  2073. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/gensym.rs +0 -0
  2074. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/src/wast.rs +0 -0
  2075. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/annotations.rs +0 -0
  2076. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/comments.rs +0 -0
  2077. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-core-func-alias.wat +0 -0
  2078. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-core-func-alias.wat.err +0 -0
  2079. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-func-alias.wat +0 -0
  2080. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-func-alias.wat.err +0 -0
  2081. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-index.wat +0 -0
  2082. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-index.wat.err +0 -0
  2083. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-name.wat +0 -0
  2084. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-name.wat.err +0 -0
  2085. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-name2.wat +0 -0
  2086. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-name2.wat.err +0 -0
  2087. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-name3.wat +0 -0
  2088. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/bad-name3.wat.err +0 -0
  2089. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/block1.wat +0 -0
  2090. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/block1.wat.err +0 -0
  2091. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/block2.wat +0 -0
  2092. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/block2.wat.err +0 -0
  2093. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/block3.wat +0 -0
  2094. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/block3.wat.err +0 -0
  2095. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment0.wat +0 -0
  2096. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment0.wat.err +0 -0
  2097. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment1.wat +0 -0
  2098. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment1.wat.err +0 -0
  2099. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment2.wat +0 -0
  2100. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment2.wat.err +0 -0
  2101. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment3.wat +0 -0
  2102. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment3.wat.err +0 -0
  2103. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment4.wat +0 -0
  2104. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment4.wat.err +0 -0
  2105. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment5.wat +0 -0
  2106. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment5.wat.err +0 -0
  2107. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment6.wat +0 -0
  2108. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment6.wat.err +0 -0
  2109. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment7.wat +0 -0
  2110. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment7.wat.err +0 -0
  2111. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment8.wat +0 -0
  2112. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-block-comment8.wat.err +0 -0
  2113. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment0.wat +0 -0
  2114. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment0.wat.err +0 -0
  2115. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment1.wat +0 -0
  2116. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment1.wat.err +0 -0
  2117. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment2.wat +0 -0
  2118. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment2.wat.err +0 -0
  2119. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment3.wat +0 -0
  2120. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment3.wat.err +0 -0
  2121. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment4.wat +0 -0
  2122. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment4.wat.err +0 -0
  2123. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment5.wat +0 -0
  2124. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment5.wat.err +0 -0
  2125. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment6.wat +0 -0
  2126. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment6.wat.err +0 -0
  2127. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment7.wat +0 -0
  2128. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment7.wat.err +0 -0
  2129. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment8.wat +0 -0
  2130. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-line-comment8.wat.err +0 -0
  2131. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string0.wat +0 -0
  2132. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string0.wat.err +0 -0
  2133. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string1.wat +0 -0
  2134. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string1.wat.err +0 -0
  2135. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string2.wat +0 -0
  2136. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string2.wat.err +0 -0
  2137. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string3.wat +0 -0
  2138. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string3.wat.err +0 -0
  2139. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string4.wat +0 -0
  2140. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string4.wat.err +0 -0
  2141. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string5.wat +0 -0
  2142. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string5.wat.err +0 -0
  2143. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string6.wat +0 -0
  2144. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string6.wat.err +0 -0
  2145. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string7.wat +0 -0
  2146. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string7.wat.err +0 -0
  2147. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string8.wat +0 -0
  2148. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/confusing-string8.wat.err +0 -0
  2149. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/inline1.wat +0 -0
  2150. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/inline1.wat.err +0 -0
  2151. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/newline-in-string.wat +0 -0
  2152. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/newline-in-string.wat.err +0 -0
  2153. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string1.wat +0 -0
  2154. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string1.wat.err +0 -0
  2155. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string10.wat +0 -0
  2156. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string10.wat.err +0 -0
  2157. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string11.wat +0 -0
  2158. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string11.wat.err +0 -0
  2159. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string12.wat +0 -0
  2160. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string12.wat.err +0 -0
  2161. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string13.wat +0 -0
  2162. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string13.wat.err +0 -0
  2163. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string14.wat +0 -0
  2164. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string14.wat.err +0 -0
  2165. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string15.wat +0 -0
  2166. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string15.wat.err +0 -0
  2167. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string16.wat +0 -0
  2168. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string16.wat.err +0 -0
  2169. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string2.wat +0 -0
  2170. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string2.wat.err +0 -0
  2171. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string3.wat +0 -0
  2172. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string3.wat.err +0 -0
  2173. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string4.wat +0 -0
  2174. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string4.wat.err +0 -0
  2175. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string5.wat +0 -0
  2176. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string5.wat.err +0 -0
  2177. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string6.wat +0 -0
  2178. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string6.wat.err +0 -0
  2179. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string7.wat +0 -0
  2180. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string7.wat.err +0 -0
  2181. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string8.wat +0 -0
  2182. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string8.wat.err +0 -0
  2183. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string9.wat +0 -0
  2184. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/string9.wat.err +0 -0
  2185. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/unbalanced.wat +0 -0
  2186. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail/unbalanced.wat.err +0 -0
  2187. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/parse-fail.rs +0 -0
  2188. /data/ext/cargo-vendor/{wast-69.0.1 → wast-201.0.0}/tests/recursive.rs +0 -0
  2189. /data/ext/cargo-vendor/{wast-69.0.1 → wat-1.201.0}/LICENSE +0 -0
  2190. /data/ext/cargo-vendor/{wat-1.0.82 → wat-1.201.0}/README.md +0 -0
  2191. /data/ext/cargo-vendor/{wat-1.0.82 → wiggle-18.0.3}/LICENSE +0 -0
  2192. /data/ext/cargo-vendor/{wiggle-17.0.1 → wiggle-18.0.3}/README.md +0 -0
  2193. /data/ext/cargo-vendor/{wiggle-17.0.1 → wiggle-18.0.3}/src/borrow.rs +0 -0
  2194. /data/ext/cargo-vendor/{wiggle-17.0.1 → wiggle-18.0.3}/src/error.rs +0 -0
  2195. /data/ext/cargo-vendor/{wiggle-17.0.1 → wiggle-18.0.3}/src/guest_type.rs +0 -0
  2196. /data/ext/cargo-vendor/{wiggle-17.0.1 → wiggle-18.0.3}/src/region.rs +0 -0
  2197. /data/ext/cargo-vendor/{wiggle-17.0.1 → wiggle-18.0.3}/src/wasmtime.rs +0 -0
  2198. /data/ext/cargo-vendor/{wiggle-17.0.1 → wiggle-generate-18.0.3}/LICENSE +0 -0
  2199. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/README.md +0 -0
  2200. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/codegen_settings.rs +0 -0
  2201. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/config.rs +0 -0
  2202. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/funcs.rs +0 -0
  2203. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/lib.rs +0 -0
  2204. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/lifetimes.rs +0 -0
  2205. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/module_trait.rs +0 -0
  2206. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/names.rs +0 -0
  2207. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/types/error.rs +0 -0
  2208. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/types/flags.rs +0 -0
  2209. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/types/handle.rs +0 -0
  2210. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/types/mod.rs +0 -0
  2211. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/types/record.rs +0 -0
  2212. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/types/variant.rs +0 -0
  2213. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-generate-18.0.3}/src/wasmtime.rs +0 -0
  2214. /data/ext/cargo-vendor/{wiggle-generate-17.0.1 → wiggle-macro-18.0.3}/LICENSE +0 -0
  2215. /data/ext/cargo-vendor/{wiggle-macro-17.0.1 → wiggle-macro-18.0.3}/src/lib.rs +0 -0
  2216. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/LICENSE +0 -0
  2217. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/build.rs +0 -0
  2218. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/isa/aarch64/address.rs +0 -0
  2219. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/isa/aarch64/asm.rs +0 -0
  2220. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/isa/aarch64/regs.rs +0 -0
  2221. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/isa/x64/address.rs +0 -0
  2222. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/isa/x64/regs.rs +0 -0
  2223. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/lib.rs +0 -0
  2224. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/regalloc.rs +0 -0
  2225. /data/ext/cargo-vendor/{winch-codegen-0.15.1 → winch-codegen-0.16.3}/src/regset.rs +0 -0
  2226. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/README.md +0 -0
  2227. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/src/abi.rs +0 -0
  2228. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/src/ast/toposort.rs +0 -0
  2229. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/src/lib.rs +0 -0
  2230. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/src/live.rs +0 -0
  2231. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/src/serde_.rs +0 -0
  2232. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/src/sizealign.rs +0 -0
  2233. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/all.rs +0 -0
  2234. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/comments.wit +0 -0
  2235. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/complex-include/deps/bar/root.wit +0 -0
  2236. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/complex-include/deps/baz/root.wit +0 -0
  2237. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/complex-include/root.wit +0 -0
  2238. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/complex-include.wit.json +0 -0
  2239. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/cross-package-resource/deps/foo/foo.wit +0 -0
  2240. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/cross-package-resource/foo.wit +0 -0
  2241. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/cross-package-resource.wit.json +0 -0
  2242. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/diamond1/deps/dep1/types.wit +0 -0
  2243. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/diamond1/deps/dep2/types.wit +0 -0
  2244. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/diamond1/join.wit +0 -0
  2245. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/diamond1.wit.json +0 -0
  2246. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/disambiguate-diamond/shared1.wit +0 -0
  2247. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/disambiguate-diamond/shared2.wit +0 -0
  2248. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/disambiguate-diamond/world.wit +0 -0
  2249. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/disambiguate-diamond.wit.json +0 -0
  2250. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/empty.wit +0 -0
  2251. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/empty.wit.json +0 -0
  2252. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -0
  2253. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/deps/corp/saas.wit +0 -0
  2254. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -0
  2255. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -0
  2256. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -0
  2257. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -0
  2258. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -0
  2259. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps/root.wit +0 -0
  2260. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/another-pkg/other-doc.wit +0 -0
  2261. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/corp/saas.wit +0 -0
  2262. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/different-pkg/the-doc.wit +0 -0
  2263. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/foreign-pkg/the-doc.wit +0 -0
  2264. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/some-pkg/some-doc.wit +0 -0
  2265. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/wasi/clocks.wit +0 -0
  2266. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/wasi/filesystem.wit +0 -0
  2267. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/deps/wasi/wasi.wit +0 -0
  2268. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union/root.wit +0 -0
  2269. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps-union.wit.json +0 -0
  2270. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/foreign-deps.wit.json +0 -0
  2271. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/functions.wit +0 -0
  2272. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/functions.wit.json +0 -0
  2273. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/ignore-files-deps/deps/bar/types.wit +0 -0
  2274. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/ignore-files-deps/deps/ignore-me.txt +0 -0
  2275. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/ignore-files-deps/world.wit +0 -0
  2276. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/ignore-files-deps.wit.json +0 -0
  2277. /data/ext/cargo-vendor/{wit-parser-0.13.0/tests/ui/parse-fail → wit-parser-0.13.2/tests/ui}/import-export-overlap1.wit +0 -0
  2278. /data/ext/cargo-vendor/{wit-parser-0.13.0/tests/ui/parse-fail → wit-parser-0.13.2/tests/ui}/import-export-overlap2.wit +0 -0
  2279. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/include-reps.wit +0 -0
  2280. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/include-reps.wit.json +0 -0
  2281. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/kebab-name-include-with.wit +0 -0
  2282. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/kebab-name-include-with.wit.json +0 -0
  2283. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/many-names/a.wit +0 -0
  2284. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/many-names/b.wit +0 -0
  2285. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/many-names.wit.json +0 -0
  2286. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/multi-file/bar.wit +0 -0
  2287. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/multi-file/cycle-a.wit +0 -0
  2288. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/multi-file/cycle-b.wit +0 -0
  2289. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/multi-file/foo.wit +0 -0
  2290. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/multi-file.wit.json +0 -0
  2291. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/name-both-resource-and-type/deps/dep/foo.wit +0 -0
  2292. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/name-both-resource-and-type/foo.wit +0 -0
  2293. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/name-both-resource-and-type.wit.json +0 -0
  2294. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/package-syntax1.wit +0 -0
  2295. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/package-syntax1.wit.json +0 -0
  2296. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/package-syntax3.wit +0 -0
  2297. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/package-syntax3.wit.json +0 -0
  2298. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/package-syntax4.wit +0 -0
  2299. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/package-syntax4.wit.json +0 -0
  2300. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  2301. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/alias-no-type.wit.result +0 -0
  2302. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/async.wit.result +0 -0
  2303. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/async1.wit.result +0 -0
  2304. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-function.wit +0 -0
  2305. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-function.wit.result +0 -0
  2306. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-function2.wit +0 -0
  2307. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-function2.wit.result +0 -0
  2308. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-include1.wit +0 -0
  2309. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-include1.wit.result +0 -0
  2310. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-include2.wit +0 -0
  2311. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-include2.wit.result +0 -0
  2312. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-include3.wit +0 -0
  2313. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-include3.wit.result +0 -0
  2314. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-list.wit +0 -0
  2315. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  2316. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg1/root.wit +0 -0
  2317. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg1.wit.result +0 -0
  2318. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +0 -0
  2319. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg2/root.wit +0 -0
  2320. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg2.wit.result +0 -0
  2321. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  2322. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg3/root.wit +0 -0
  2323. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg3.wit.result +0 -0
  2324. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -0
  2325. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg4/root.wit +0 -0
  2326. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg4.wit.result +0 -0
  2327. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -0
  2328. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg5/root.wit +0 -0
  2329. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg5.wit.result +0 -0
  2330. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  2331. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg6/root.wit +0 -0
  2332. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-pkg6.wit.result +0 -0
  2333. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource1.wit +0 -0
  2334. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource1.wit.result +0 -0
  2335. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource10.wit +0 -0
  2336. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource10.wit.result +0 -0
  2337. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource11.wit +0 -0
  2338. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource11.wit.result +0 -0
  2339. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource12.wit +0 -0
  2340. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource12.wit.result +0 -0
  2341. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource13.wit +0 -0
  2342. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource13.wit.result +0 -0
  2343. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource14.wit +0 -0
  2344. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource14.wit.result +0 -0
  2345. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource15/deps/foo/foo.wit +0 -0
  2346. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource15/foo.wit +0 -0
  2347. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource15.wit.result +0 -0
  2348. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource2.wit +0 -0
  2349. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource2.wit.result +0 -0
  2350. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource3.wit +0 -0
  2351. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource3.wit.result +0 -0
  2352. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource4.wit +0 -0
  2353. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource4.wit.result +0 -0
  2354. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource5.wit +0 -0
  2355. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource5.wit.result +0 -0
  2356. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource6.wit +0 -0
  2357. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource6.wit.result +0 -0
  2358. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource7.wit +0 -0
  2359. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource7.wit.result +0 -0
  2360. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource8.wit +0 -0
  2361. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource8.wit.result +0 -0
  2362. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource9.wit +0 -0
  2363. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-resource9.wit.result +0 -0
  2364. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-world-type1.wit +0 -0
  2365. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/bad-world-type1.wit.result +0 -0
  2366. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/conflicting-package/a.wit +0 -0
  2367. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/conflicting-package/b.wit +0 -0
  2368. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/conflicting-package.wit.result +0 -0
  2369. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle.wit +0 -0
  2370. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle.wit.result +0 -0
  2371. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle2.wit +0 -0
  2372. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle2.wit.result +0 -0
  2373. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle3.wit +0 -0
  2374. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle3.wit.result +0 -0
  2375. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle4.wit +0 -0
  2376. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle4.wit.result +0 -0
  2377. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle5.wit +0 -0
  2378. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/cycle5.wit.result +0 -0
  2379. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/dangling-type.wit +0 -0
  2380. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  2381. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-function-params.wit +0 -0
  2382. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-function-params.wit.result +0 -0
  2383. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-functions.wit +0 -0
  2384. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-functions.wit.result +0 -0
  2385. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-interface.wit +0 -0
  2386. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-interface.wit.result +0 -0
  2387. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-interface2/foo.wit +0 -0
  2388. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-interface2/foo2.wit +0 -0
  2389. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-interface2.wit.result +0 -0
  2390. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-type.wit +0 -0
  2391. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/duplicate-type.wit.result +0 -0
  2392. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/empty-enum.wit +0 -0
  2393. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/empty-enum.wit.result +0 -0
  2394. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/empty-variant1.wit +0 -0
  2395. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/empty-variant1.wit.result +0 -0
  2396. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/export-twice.wit +0 -0
  2397. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/export-twice.wit.result +0 -0
  2398. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export1.wit +0 -0
  2399. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export1.wit.result +0 -0
  2400. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export2.wit +0 -0
  2401. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export2.wit.result +0 -0
  2402. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export3.wit +0 -0
  2403. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export3.wit.result +0 -0
  2404. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export4.wit +0 -0
  2405. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export4.wit.result +0 -0
  2406. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export5.wit +0 -0
  2407. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-and-export5.wit.result +0 -0
  2408. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-twice.wit +0 -0
  2409. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/import-twice.wit.result +0 -0
  2410. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-cycle.wit +0 -0
  2411. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-cycle.wit.result +0 -0
  2412. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-foreign/deps/bar/empty.wit +0 -0
  2413. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-foreign/root.wit +0 -0
  2414. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-foreign.wit.result +0 -0
  2415. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-with-id.wit +0 -0
  2416. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-with-id.wit.result +0 -0
  2417. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-with-on-id.wit +0 -0
  2418. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/include-with-on-id.wit.result +0 -0
  2419. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  2420. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  2421. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/invalid-type-reference.wit +0 -0
  2422. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/invalid-type-reference.wit.result +0 -0
  2423. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/invalid-type-reference2.wit +0 -0
  2424. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/invalid-type-reference2.wit.result +0 -0
  2425. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/kebab-name-include-not-found.wit +0 -0
  2426. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/kebab-name-include-not-found.wit.result +0 -0
  2427. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/kebab-name-include.wit +0 -0
  2428. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/kebab-name-include.wit.result +0 -0
  2429. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/keyword.wit +0 -0
  2430. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/keyword.wit.result +0 -0
  2431. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/missing-package.wit +0 -0
  2432. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/missing-package.wit.result +0 -0
  2433. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/multiple-package-docs/a.wit +0 -0
  2434. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/multiple-package-docs/b.wit +0 -0
  2435. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/multiple-package-docs.wit.result +0 -0
  2436. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +0 -0
  2437. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +0 -0
  2438. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/no-access-to-sibling-use.wit.result +0 -0
  2439. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/non-existance-world-include/deps/bar/baz.wit +0 -0
  2440. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/non-existance-world-include/root.wit +0 -0
  2441. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/non-existance-world-include.wit.result +0 -0
  2442. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +0 -0
  2443. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/pkg-cycle/root.wit +0 -0
  2444. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/pkg-cycle.wit.result +0 -0
  2445. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +0 -0
  2446. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +0 -0
  2447. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/pkg-cycle2/root.wit +0 -0
  2448. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/pkg-cycle2.wit.result +0 -0
  2449. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/type-and-resource-same-name/deps/dep/foo.wit +0 -0
  2450. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/type-and-resource-same-name/foo.wit +0 -0
  2451. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/type-and-resource-same-name.wit.result +0 -0
  2452. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/undefined-typed.wit +0 -0
  2453. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/undefined-typed.wit.result +0 -0
  2454. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unknown-interface.wit +0 -0
  2455. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unknown-interface.wit.result +0 -0
  2456. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface1.wit +0 -0
  2457. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface1.wit.result +0 -0
  2458. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface2.wit +0 -0
  2459. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface2.wit.result +0 -0
  2460. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface3.wit +0 -0
  2461. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface3.wit.result +0 -0
  2462. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface4.wit +0 -0
  2463. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-interface4.wit.result +0 -0
  2464. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use1.wit +0 -0
  2465. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use1.wit.result +0 -0
  2466. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use10/bar.wit +0 -0
  2467. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  2468. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use10.wit.result +0 -0
  2469. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use2.wit +0 -0
  2470. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use2.wit.result +0 -0
  2471. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use3.wit +0 -0
  2472. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use3.wit.result +0 -0
  2473. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use7.wit +0 -0
  2474. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use7.wit.result +0 -0
  2475. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use8.wit +0 -0
  2476. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use8.wit.result +0 -0
  2477. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use9.wit +0 -0
  2478. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unresolved-use9.wit.result +0 -0
  2479. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
  2480. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-and-include-world/deps/bar/baz.wit +0 -0
  2481. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
  2482. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-and-include-world.wit.result +0 -0
  2483. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-conflict.wit +0 -0
  2484. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
  2485. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-conflict2.wit +0 -0
  2486. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
  2487. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-conflict3.wit +0 -0
  2488. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
  2489. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-cycle1.wit +0 -0
  2490. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
  2491. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-cycle4.wit +0 -0
  2492. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
  2493. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-shadow1.wit +0 -0
  2494. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
  2495. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
  2496. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-world/root.wit +0 -0
  2497. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/use-world.wit.result +0 -0
  2498. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
  2499. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
  2500. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
  2501. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
  2502. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
  2503. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
  2504. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
  2505. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
  2506. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
  2507. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
  2508. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/random.wit +0 -0
  2509. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/random.wit.json +0 -0
  2510. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-empty.wit +0 -0
  2511. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-empty.wit.json +0 -0
  2512. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-multiple-returns-borrow.wit +0 -0
  2513. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-multiple-returns-borrow.wit.json +0 -0
  2514. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-multiple-returns-own.wit +0 -0
  2515. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-multiple-returns-own.wit.json +0 -0
  2516. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-multiple.wit +0 -0
  2517. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-multiple.wit.json +0 -0
  2518. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-return-borrow.wit +0 -0
  2519. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-return-borrow.wit.json +0 -0
  2520. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-return-own.wit +0 -0
  2521. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources-return-own.wit.json +0 -0
  2522. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources.wit +0 -0
  2523. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources.wit.json +0 -0
  2524. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources1.wit +0 -0
  2525. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/resources1.wit.json +0 -0
  2526. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/shared-types.wit +0 -0
  2527. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/shared-types.wit.json +0 -0
  2528. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/stress-export-elaborate.wit +0 -0
  2529. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/stress-export-elaborate.wit.json +0 -0
  2530. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/type-then-eof.wit +0 -0
  2531. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/type-then-eof.wit.json +0 -0
  2532. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/union-fuzz-1.wit +0 -0
  2533. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/union-fuzz-1.wit.json +0 -0
  2534. /data/ext/cargo-vendor/{wit-parser-0.13.0/tests/ui/parse-fail → wit-parser-0.13.2/tests/ui}/union-fuzz-2.wit +0 -0
  2535. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/use-chain.wit +0 -0
  2536. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/use-chain.wit.json +0 -0
  2537. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/use.wit +0 -0
  2538. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/use.wit.json +0 -0
  2539. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/versions/deps/a1/foo.wit +0 -0
  2540. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/versions/deps/a2/foo.wit +0 -0
  2541. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/versions/foo.wit +0 -0
  2542. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/versions.wit.json +0 -0
  2543. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/wasi.wit +0 -0
  2544. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-diamond.wit +0 -0
  2545. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-diamond.wit.json +0 -0
  2546. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-iface-no-collide.wit +0 -0
  2547. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-iface-no-collide.wit.json +0 -0
  2548. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-implicit-import1.wit +0 -0
  2549. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-implicit-import1.wit.json +0 -0
  2550. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-implicit-import2.wit +0 -0
  2551. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-implicit-import2.wit.json +0 -0
  2552. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-implicit-import3.wit +0 -0
  2553. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-implicit-import3.wit.json +0 -0
  2554. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-same-fields4.wit +0 -0
  2555. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-same-fields4.wit.json +0 -0
  2556. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-top-level-funcs.wit +0 -0
  2557. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-top-level-funcs.wit.json +0 -0
  2558. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-top-level-resources.wit +0 -0
  2559. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/world-top-level-resources.wit.json +0 -0
  2560. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/worlds-union-dedup.wit +0 -0
  2561. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/worlds-union-dedup.wit.json +0 -0
  2562. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/worlds-with-types.wit +0 -0
  2563. /data/ext/cargo-vendor/{wit-parser-0.13.0 → wit-parser-0.13.2}/tests/ui/worlds-with-types.wit.json +0 -0
@@ -0,0 +1,4395 @@
1
+ use crate::binemit::{Addend, Reloc};
2
+ use crate::ir;
3
+ use crate::ir::immediates::{Ieee32, Ieee64};
4
+ use crate::ir::TrapCode;
5
+ use crate::ir::{KnownSymbol, LibCall, MemFlags};
6
+ use crate::isa::x64::encoding::evex::{EvexInstruction, EvexVectorLength, RegisterOrAmode};
7
+ use crate::isa::x64::encoding::rex::{
8
+ emit_simm, emit_std_enc_enc, emit_std_enc_mem, emit_std_reg_mem, emit_std_reg_reg, int_reg_enc,
9
+ low8_will_sign_extend_to_32, low8_will_sign_extend_to_64, reg_enc, LegacyPrefixes, OpcodeMap,
10
+ RexFlags,
11
+ };
12
+ use crate::isa::x64::encoding::vex::{VexInstruction, VexVectorLength};
13
+ use crate::isa::x64::inst::args::*;
14
+ use crate::isa::x64::inst::*;
15
+ use crate::machinst::{inst_common, MachBuffer, MachInstEmit, MachLabel, Reg, Writable};
16
+ use core::convert::TryInto;
17
+
18
+ /// A small helper to generate a signed conversion instruction.
19
+ fn emit_signed_cvt(
20
+ sink: &mut MachBuffer<Inst>,
21
+ info: &EmitInfo,
22
+ state: &mut EmitState,
23
+ // Required to be RealRegs.
24
+ src: Reg,
25
+ dst: Writable<Reg>,
26
+ to_f64: bool,
27
+ ) {
28
+ // Handle an unsigned int, which is the "easy" case: a signed conversion will do the
29
+ // right thing.
30
+ let op = if to_f64 {
31
+ SseOpcode::Cvtsi2sd
32
+ } else {
33
+ SseOpcode::Cvtsi2ss
34
+ };
35
+ Inst::CvtIntToFloat {
36
+ op,
37
+ dst: Writable::from_reg(Xmm::new(dst.to_reg()).unwrap()),
38
+ src1: Xmm::new(dst.to_reg()).unwrap(),
39
+ src2: GprMem::new(RegMem::reg(src)).unwrap(),
40
+ src2_size: OperandSize::Size64,
41
+ }
42
+ .emit(&[], sink, info, state);
43
+ }
44
+
45
+ /// Emits a one way conditional jump if CC is set (true).
46
+ fn one_way_jmp(sink: &mut MachBuffer<Inst>, cc: CC, label: MachLabel) {
47
+ let cond_start = sink.cur_offset();
48
+ let cond_disp_off = cond_start + 2;
49
+ sink.use_label_at_offset(cond_disp_off, label, LabelUse::JmpRel32);
50
+ sink.put1(0x0F);
51
+ sink.put1(0x80 + cc.get_enc());
52
+ sink.put4(0x0);
53
+ }
54
+
55
+ /// Emits a relocation, attaching the current source location as well.
56
+ fn emit_reloc(sink: &mut MachBuffer<Inst>, kind: Reloc, name: &ExternalName, addend: Addend) {
57
+ sink.add_reloc(kind, name, addend);
58
+ }
59
+
60
+ /// The top-level emit function.
61
+ ///
62
+ /// Important! Do not add improved (shortened) encoding cases to existing
63
+ /// instructions without also adding tests for those improved encodings. That
64
+ /// is a dangerous game that leads to hard-to-track-down errors in the emitted
65
+ /// code.
66
+ ///
67
+ /// For all instructions, make sure to have test coverage for all of the
68
+ /// following situations. Do this by creating the cross product resulting from
69
+ /// applying the following rules to each operand:
70
+ ///
71
+ /// (1) for any insn that mentions a register: one test using a register from
72
+ /// the group [rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi] and a second one
73
+ /// using a register from the group [r8, r9, r10, r11, r12, r13, r14, r15].
74
+ /// This helps detect incorrect REX prefix construction.
75
+ ///
76
+ /// (2) for any insn that mentions a byte register: one test for each of the
77
+ /// four encoding groups [al, cl, dl, bl], [spl, bpl, sil, dil],
78
+ /// [r8b .. r11b] and [r12b .. r15b]. This checks that
79
+ /// apparently-redundant REX prefixes are retained when required.
80
+ ///
81
+ /// (3) for any insn that contains an immediate field, check the following
82
+ /// cases: field is zero, field is in simm8 range (-128 .. 127), field is
83
+ /// in simm32 range (-0x8000_0000 .. 0x7FFF_FFFF). This is because some
84
+ /// instructions that require a 32-bit immediate have a short-form encoding
85
+ /// when the imm is in simm8 range.
86
+ ///
87
+ /// Rules (1), (2) and (3) don't apply for registers within address expressions
88
+ /// (`Addr`s). Those are already pretty well tested, and the registers in them
89
+ /// don't have any effect on the containing instruction (apart from possibly
90
+ /// require REX prefix bits).
91
+ ///
92
+ /// When choosing registers for a test, avoid using registers with the same
93
+ /// offset within a given group. For example, don't use rax and r8, since they
94
+ /// both have the lowest 3 bits as 000, and so the test won't detect errors
95
+ /// where those 3-bit register sub-fields are confused by the emitter. Instead
96
+ /// use (eg) rax (lo3 = 000) and r9 (lo3 = 001). Similarly, don't use (eg) cl
97
+ /// and bpl since they have the same offset in their group; use instead (eg) cl
98
+ /// and sil.
99
+ ///
100
+ /// For all instructions, also add a test that uses only low-half registers
101
+ /// (rax .. rdi, xmm0 .. xmm7) etc, so as to check that any redundant REX
102
+ /// prefixes are correctly omitted. This low-half restriction must apply to
103
+ /// _all_ registers in the insn, even those in address expressions.
104
+ ///
105
+ /// Following these rules creates large numbers of test cases, but it's the
106
+ /// only way to make the emitter reliable.
107
+ ///
108
+ /// Known possible improvements:
109
+ ///
110
+ /// * there's a shorter encoding for shl/shr/sar by a 1-bit immediate. (Do we
111
+ /// care?)
112
+ pub(crate) fn emit(
113
+ inst: &Inst,
114
+ allocs: &mut AllocationConsumer<'_>,
115
+ sink: &mut MachBuffer<Inst>,
116
+ info: &EmitInfo,
117
+ state: &mut EmitState,
118
+ ) {
119
+ let matches_isa_flags = |iset_requirement: &InstructionSet| -> bool {
120
+ match iset_requirement {
121
+ // Cranelift assumes SSE2 at least.
122
+ InstructionSet::SSE | InstructionSet::SSE2 => true,
123
+ InstructionSet::SSSE3 => info.isa_flags.use_ssse3(),
124
+ InstructionSet::SSE41 => info.isa_flags.use_sse41(),
125
+ InstructionSet::SSE42 => info.isa_flags.use_sse42(),
126
+ InstructionSet::Popcnt => info.isa_flags.use_popcnt(),
127
+ InstructionSet::Lzcnt => info.isa_flags.use_lzcnt(),
128
+ InstructionSet::BMI1 => info.isa_flags.use_bmi1(),
129
+ InstructionSet::BMI2 => info.isa_flags.has_bmi2(),
130
+ InstructionSet::FMA => info.isa_flags.has_fma(),
131
+ InstructionSet::AVX => info.isa_flags.has_avx(),
132
+ InstructionSet::AVX2 => info.isa_flags.has_avx2(),
133
+ InstructionSet::AVX512BITALG => info.isa_flags.has_avx512bitalg(),
134
+ InstructionSet::AVX512DQ => info.isa_flags.has_avx512dq(),
135
+ InstructionSet::AVX512F => info.isa_flags.has_avx512f(),
136
+ InstructionSet::AVX512VBMI => info.isa_flags.has_avx512vbmi(),
137
+ InstructionSet::AVX512VL => info.isa_flags.has_avx512vl(),
138
+ }
139
+ };
140
+
141
+ // Certain instructions may be present in more than one ISA feature set; we must at least match
142
+ // one of them in the target CPU.
143
+ let isa_requirements = inst.available_in_any_isa();
144
+ if !isa_requirements.is_empty() && !isa_requirements.iter().all(matches_isa_flags) {
145
+ panic!(
146
+ "Cannot emit inst '{:?}' for target; failed to match ISA requirements: {:?}",
147
+ inst, isa_requirements
148
+ )
149
+ }
150
+
151
+ match inst {
152
+ Inst::AluRmiR {
153
+ size,
154
+ op,
155
+ src1,
156
+ src2,
157
+ dst: reg_g,
158
+ } => {
159
+ let src1 = allocs.next(src1.to_reg());
160
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
161
+ debug_assert_eq!(src1, reg_g);
162
+ let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
163
+
164
+ let prefix = if *size == OperandSize::Size16 {
165
+ LegacyPrefixes::_66
166
+ } else {
167
+ LegacyPrefixes::None
168
+ };
169
+
170
+ let mut rex = RexFlags::from(*size);
171
+ if *op == AluRmiROpcode::Mul {
172
+ // We kinda freeloaded Mul into RMI_R_Op, but it doesn't fit the usual pattern, so
173
+ // we have to special-case it.
174
+ if *size == OperandSize::Size8 {
175
+ match src2 {
176
+ RegMemImm::Reg { reg: reg_e } => {
177
+ debug_assert!(reg_e.is_real());
178
+ rex.always_emit_if_8bit_needed(reg_e);
179
+ let enc_e = int_reg_enc(reg_e);
180
+ emit_std_enc_enc(sink, LegacyPrefixes::None, 0xF6, 1, 5, enc_e, rex);
181
+ }
182
+
183
+ RegMemImm::Mem { addr } => {
184
+ let amode = addr.finalize(state, sink);
185
+ emit_std_enc_mem(
186
+ sink,
187
+ LegacyPrefixes::None,
188
+ 0xF6,
189
+ 1,
190
+ 5,
191
+ &amode,
192
+ rex,
193
+ 0,
194
+ );
195
+ }
196
+
197
+ RegMemImm::Imm { .. } => {
198
+ panic!("Cannot emit 8bit imul with 8bit immediate");
199
+ }
200
+ }
201
+ } else {
202
+ match src2 {
203
+ RegMemImm::Reg { reg: reg_e } => {
204
+ emit_std_reg_reg(sink, prefix, 0x0FAF, 2, reg_g, reg_e, rex);
205
+ }
206
+
207
+ RegMemImm::Mem { addr } => {
208
+ let amode = addr.finalize(state, sink);
209
+ emit_std_reg_mem(sink, prefix, 0x0FAF, 2, reg_g, &amode, rex, 0);
210
+ }
211
+
212
+ RegMemImm::Imm { simm32 } => {
213
+ let imm_size = if low8_will_sign_extend_to_32(simm32) {
214
+ 1
215
+ } else {
216
+ if *size == OperandSize::Size16 {
217
+ 2
218
+ } else {
219
+ 4
220
+ }
221
+ };
222
+ let opcode = if imm_size == 1 { 0x6B } else { 0x69 };
223
+ // Yes, really, reg_g twice.
224
+ emit_std_reg_reg(sink, prefix, opcode, 1, reg_g, reg_g, rex);
225
+ emit_simm(sink, imm_size, simm32);
226
+ }
227
+ }
228
+ }
229
+ } else {
230
+ let (opcode_r, opcode_m, subopcode_i) = match op {
231
+ AluRmiROpcode::Add => (0x01, 0x03, 0),
232
+ AluRmiROpcode::Adc => (0x11, 0x03, 0),
233
+ AluRmiROpcode::Sub => (0x29, 0x2B, 5),
234
+ AluRmiROpcode::Sbb => (0x19, 0x2B, 5),
235
+ AluRmiROpcode::And => (0x21, 0x23, 4),
236
+ AluRmiROpcode::Or => (0x09, 0x0B, 1),
237
+ AluRmiROpcode::Xor => (0x31, 0x33, 6),
238
+ AluRmiROpcode::Mul => panic!("unreachable"),
239
+ };
240
+
241
+ let (opcode_r, opcode_m) = if *size == OperandSize::Size8 {
242
+ (opcode_r - 1, opcode_m - 1)
243
+ } else {
244
+ (opcode_r, opcode_m)
245
+ };
246
+
247
+ if *size == OperandSize::Size8 {
248
+ debug_assert!(reg_g.is_real());
249
+ rex.always_emit_if_8bit_needed(reg_g);
250
+ }
251
+
252
+ match src2 {
253
+ RegMemImm::Reg { reg: reg_e } => {
254
+ if *size == OperandSize::Size8 {
255
+ debug_assert!(reg_e.is_real());
256
+ rex.always_emit_if_8bit_needed(reg_e);
257
+ }
258
+
259
+ // GCC/llvm use the swapped operand encoding (viz., the R/RM vs RM/R
260
+ // duality). Do this too, so as to be able to compare generated machine
261
+ // code easily.
262
+ emit_std_reg_reg(sink, prefix, opcode_r, 1, reg_e, reg_g, rex);
263
+ }
264
+
265
+ RegMemImm::Mem { addr } => {
266
+ let amode = addr.finalize(state, sink);
267
+ // Here we revert to the "normal" G-E ordering.
268
+ emit_std_reg_mem(sink, prefix, opcode_m, 1, reg_g, &amode, rex, 0);
269
+ }
270
+
271
+ RegMemImm::Imm { simm32 } => {
272
+ let imm_size = if *size == OperandSize::Size8 {
273
+ 1
274
+ } else {
275
+ if low8_will_sign_extend_to_32(simm32) {
276
+ 1
277
+ } else {
278
+ if *size == OperandSize::Size16 {
279
+ 2
280
+ } else {
281
+ 4
282
+ }
283
+ }
284
+ };
285
+
286
+ let opcode = if *size == OperandSize::Size8 {
287
+ 0x80
288
+ } else if low8_will_sign_extend_to_32(simm32) {
289
+ 0x83
290
+ } else {
291
+ 0x81
292
+ };
293
+
294
+ // And also here we use the "normal" G-E ordering.
295
+ let enc_g = int_reg_enc(reg_g);
296
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode_i, enc_g, rex);
297
+ emit_simm(sink, imm_size, simm32);
298
+ }
299
+ }
300
+ }
301
+ }
302
+
303
+ Inst::AluConstOp { op, size, dst } => {
304
+ let dst = allocs.next(dst.to_reg().to_reg());
305
+ emit(
306
+ &Inst::AluRmiR {
307
+ size: *size,
308
+ op: *op,
309
+ dst: Writable::from_reg(Gpr::new(dst).unwrap()),
310
+ src1: Gpr::new(dst).unwrap(),
311
+ src2: Gpr::new(dst).unwrap().into(),
312
+ },
313
+ allocs,
314
+ sink,
315
+ info,
316
+ state,
317
+ );
318
+ }
319
+
320
+ Inst::AluRM {
321
+ size,
322
+ src1_dst,
323
+ src2,
324
+ op,
325
+ } => {
326
+ let src2 = allocs.next(src2.to_reg());
327
+ let src1_dst = src1_dst.finalize(state, sink).with_allocs(allocs);
328
+
329
+ let opcode = match op {
330
+ AluRmiROpcode::Add => 0x01,
331
+ AluRmiROpcode::Sub => 0x29,
332
+ AluRmiROpcode::And => 0x21,
333
+ AluRmiROpcode::Or => 0x09,
334
+ AluRmiROpcode::Xor => 0x31,
335
+ _ => panic!("Unsupported read-modify-write ALU opcode"),
336
+ };
337
+
338
+ let prefix = if *size == OperandSize::Size16 {
339
+ LegacyPrefixes::_66
340
+ } else {
341
+ LegacyPrefixes::None
342
+ };
343
+ let opcode = if *size == OperandSize::Size8 {
344
+ opcode - 1
345
+ } else {
346
+ opcode
347
+ };
348
+
349
+ let mut rex = RexFlags::from(*size);
350
+ if *size == OperandSize::Size8 {
351
+ debug_assert!(src2.is_real());
352
+ rex.always_emit_if_8bit_needed(src2);
353
+ }
354
+
355
+ let enc_g = int_reg_enc(src2);
356
+ emit_std_enc_mem(sink, prefix, opcode, 1, enc_g, &src1_dst, rex, 0);
357
+ }
358
+
359
+ Inst::AluRmRVex {
360
+ size,
361
+ op,
362
+ dst,
363
+ src1,
364
+ src2,
365
+ } => {
366
+ use AluRmROpcode::*;
367
+ use LegacyPrefixes as LP;
368
+
369
+ let dst = allocs.next(dst.to_reg().to_reg());
370
+ let src1 = allocs.next(src1.to_reg());
371
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
372
+ RegMem::Reg { reg } => {
373
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
374
+ }
375
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
376
+ };
377
+
378
+ let w = match size {
379
+ OperandSize::Size32 => false,
380
+ OperandSize::Size64 => true,
381
+
382
+ // the other cases would be rejected by isle constructors
383
+ _ => unreachable!(),
384
+ };
385
+
386
+ let (prefix, opcode) = match op {
387
+ Andn => (LP::None, 0xf2),
388
+ Sarx => (LP::_F3, 0xf7),
389
+ Shrx => (LP::_F2, 0xf7),
390
+ Shlx => (LP::_66, 0xf7),
391
+ Bzhi => (LP::None, 0xf5),
392
+ };
393
+
394
+ VexInstruction::new()
395
+ .prefix(prefix)
396
+ .map(OpcodeMap::_0F38)
397
+ .w(w)
398
+ .reg(dst.to_real_reg().unwrap().hw_enc())
399
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
400
+ .rm(src2)
401
+ .opcode(opcode)
402
+ .encode(sink);
403
+ }
404
+
405
+ Inst::UnaryRmR { size, op, src, dst } => {
406
+ let dst = allocs.next(dst.to_reg().to_reg());
407
+ let rex_flags = RexFlags::from(*size);
408
+ use UnaryRmROpcode::*;
409
+ let prefix = match size {
410
+ OperandSize::Size16 => match op {
411
+ Bsr | Bsf => LegacyPrefixes::_66,
412
+ Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_66F3,
413
+ },
414
+ OperandSize::Size32 | OperandSize::Size64 => match op {
415
+ Bsr | Bsf => LegacyPrefixes::None,
416
+ Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_F3,
417
+ },
418
+ _ => unreachable!(),
419
+ };
420
+
421
+ let (opcode, num_opcodes) = match op {
422
+ Bsr => (0x0fbd, 2),
423
+ Bsf => (0x0fbc, 2),
424
+ Lzcnt => (0x0fbd, 2),
425
+ Tzcnt => (0x0fbc, 2),
426
+ Popcnt => (0x0fb8, 2),
427
+ };
428
+
429
+ match src.clone().into() {
430
+ RegMem::Reg { reg: src } => {
431
+ let src = allocs.next(src);
432
+ emit_std_reg_reg(sink, prefix, opcode, num_opcodes, dst, src, rex_flags);
433
+ }
434
+ RegMem::Mem { addr: src } => {
435
+ let amode = src.finalize(state, sink).with_allocs(allocs);
436
+ emit_std_reg_mem(sink, prefix, opcode, num_opcodes, dst, &amode, rex_flags, 0);
437
+ }
438
+ }
439
+ }
440
+
441
+ Inst::UnaryRmRVex { size, op, src, dst } => {
442
+ let dst = allocs.next(dst.to_reg().to_reg());
443
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
444
+ RegMem::Reg { reg } => {
445
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
446
+ }
447
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
448
+ };
449
+
450
+ let (opcode, opcode_ext) = match op {
451
+ UnaryRmRVexOpcode::Blsr => (0xF3, 1),
452
+ UnaryRmRVexOpcode::Blsmsk => (0xF3, 2),
453
+ UnaryRmRVexOpcode::Blsi => (0xF3, 3),
454
+ };
455
+
456
+ VexInstruction::new()
457
+ .map(OpcodeMap::_0F38)
458
+ .w(*size == OperandSize::Size64)
459
+ .opcode(opcode)
460
+ .reg(opcode_ext)
461
+ .vvvv(dst.to_real_reg().unwrap().hw_enc())
462
+ .rm(src)
463
+ .encode(sink);
464
+ }
465
+
466
+ Inst::UnaryRmRImmVex {
467
+ size,
468
+ op,
469
+ src,
470
+ dst,
471
+ imm,
472
+ } => {
473
+ let dst = allocs.next(dst.to_reg().to_reg());
474
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
475
+ RegMem::Reg { reg } => {
476
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
477
+ }
478
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
479
+ };
480
+
481
+ let opcode = match op {
482
+ UnaryRmRImmVexOpcode::Rorx => 0xF0,
483
+ };
484
+
485
+ VexInstruction::new()
486
+ .prefix(LegacyPrefixes::_F2)
487
+ .map(OpcodeMap::_0F3A)
488
+ .w(*size == OperandSize::Size64)
489
+ .opcode(opcode)
490
+ .reg(dst.to_real_reg().unwrap().hw_enc())
491
+ .rm(src)
492
+ .imm(*imm)
493
+ .encode(sink);
494
+ }
495
+
496
+ Inst::Not { size, src, dst } => {
497
+ let src = allocs.next(src.to_reg());
498
+ let dst = allocs.next(dst.to_reg().to_reg());
499
+ debug_assert_eq!(src, dst);
500
+ let rex_flags = RexFlags::from((*size, dst));
501
+ let (opcode, prefix) = match size {
502
+ OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
503
+ OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
504
+ OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
505
+ OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
506
+ };
507
+
508
+ let subopcode = 2;
509
+ let enc_src = int_reg_enc(dst);
510
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
511
+ }
512
+
513
+ Inst::Neg { size, src, dst } => {
514
+ let src = allocs.next(src.to_reg());
515
+ let dst = allocs.next(dst.to_reg().to_reg());
516
+ debug_assert_eq!(src, dst);
517
+ let rex_flags = RexFlags::from((*size, dst));
518
+ let (opcode, prefix) = match size {
519
+ OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
520
+ OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
521
+ OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
522
+ OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
523
+ };
524
+
525
+ let subopcode = 3;
526
+ let enc_src = int_reg_enc(dst);
527
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
528
+ }
529
+
530
+ Inst::Div {
531
+ sign,
532
+ trap,
533
+ divisor,
534
+ ..
535
+ }
536
+ | Inst::Div8 {
537
+ sign,
538
+ trap,
539
+ divisor,
540
+ ..
541
+ } => {
542
+ let divisor = divisor.clone().to_reg_mem().with_allocs(allocs);
543
+ let size = match inst {
544
+ Inst::Div {
545
+ size,
546
+ dividend_lo,
547
+ dividend_hi,
548
+ dst_quotient,
549
+ dst_remainder,
550
+ ..
551
+ } => {
552
+ let dividend_lo = allocs.next(dividend_lo.to_reg());
553
+ let dividend_hi = allocs.next(dividend_hi.to_reg());
554
+ let dst_quotient = allocs.next(dst_quotient.to_reg().to_reg());
555
+ let dst_remainder = allocs.next(dst_remainder.to_reg().to_reg());
556
+ debug_assert_eq!(dividend_lo, regs::rax());
557
+ debug_assert_eq!(dividend_hi, regs::rdx());
558
+ debug_assert_eq!(dst_quotient, regs::rax());
559
+ debug_assert_eq!(dst_remainder, regs::rdx());
560
+ *size
561
+ }
562
+ Inst::Div8 { dividend, dst, .. } => {
563
+ let dividend = allocs.next(dividend.to_reg());
564
+ let dst = allocs.next(dst.to_reg().to_reg());
565
+ debug_assert_eq!(dividend, regs::rax());
566
+ debug_assert_eq!(dst, regs::rax());
567
+ OperandSize::Size8
568
+ }
569
+ _ => unreachable!(),
570
+ };
571
+
572
+ let (opcode, prefix) = match size {
573
+ OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
574
+ OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
575
+ OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
576
+ OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
577
+ };
578
+
579
+ sink.add_trap(*trap);
580
+
581
+ let subopcode = match sign {
582
+ DivSignedness::Signed => 7,
583
+ DivSignedness::Unsigned => 6,
584
+ };
585
+ match divisor {
586
+ RegMem::Reg { reg } => {
587
+ let src = int_reg_enc(reg);
588
+ emit_std_enc_enc(
589
+ sink,
590
+ prefix,
591
+ opcode,
592
+ 1,
593
+ subopcode,
594
+ src,
595
+ RexFlags::from((size, reg)),
596
+ )
597
+ }
598
+ RegMem::Mem { addr: src } => {
599
+ let amode = src.finalize(state, sink);
600
+ emit_std_enc_mem(
601
+ sink,
602
+ prefix,
603
+ opcode,
604
+ 1,
605
+ subopcode,
606
+ &amode,
607
+ RexFlags::from(size),
608
+ 0,
609
+ );
610
+ }
611
+ }
612
+ }
613
+
614
+ Inst::MulHi {
615
+ size,
616
+ signed,
617
+ src1,
618
+ src2,
619
+ dst_lo,
620
+ dst_hi,
621
+ } => {
622
+ let src1 = allocs.next(src1.to_reg());
623
+ let dst_lo = allocs.next(dst_lo.to_reg().to_reg());
624
+ let dst_hi = allocs.next(dst_hi.to_reg().to_reg());
625
+ debug_assert_eq!(src1, regs::rax());
626
+ debug_assert_eq!(dst_lo, regs::rax());
627
+ debug_assert_eq!(dst_hi, regs::rdx());
628
+
629
+ let rex_flags = RexFlags::from(*size);
630
+ let prefix = match size {
631
+ OperandSize::Size16 => LegacyPrefixes::_66,
632
+ OperandSize::Size32 => LegacyPrefixes::None,
633
+ OperandSize::Size64 => LegacyPrefixes::None,
634
+ _ => unreachable!(),
635
+ };
636
+
637
+ let subopcode = if *signed { 5 } else { 4 };
638
+ match src2.clone().to_reg_mem() {
639
+ RegMem::Reg { reg } => {
640
+ let reg = allocs.next(reg);
641
+ let src = int_reg_enc(reg);
642
+ emit_std_enc_enc(sink, prefix, 0xF7, 1, subopcode, src, rex_flags)
643
+ }
644
+ RegMem::Mem { addr: src } => {
645
+ let amode = src.finalize(state, sink).with_allocs(allocs);
646
+ emit_std_enc_mem(sink, prefix, 0xF7, 1, subopcode, &amode, rex_flags, 0);
647
+ }
648
+ }
649
+ }
650
+
651
+ Inst::UMulLo {
652
+ size,
653
+ src1,
654
+ src2,
655
+ dst,
656
+ } => {
657
+ let src1 = allocs.next(src1.to_reg());
658
+ let dst = allocs.next(dst.to_reg().to_reg());
659
+ debug_assert_eq!(src1, regs::rax());
660
+ debug_assert_eq!(dst, regs::rax());
661
+
662
+ let mut rex = RexFlags::from(*size);
663
+ let prefix = match size {
664
+ OperandSize::Size16 => LegacyPrefixes::_66,
665
+ _ => LegacyPrefixes::None,
666
+ };
667
+
668
+ let opcode = if *size == OperandSize::Size8 {
669
+ 0xF6
670
+ } else {
671
+ 0xF7
672
+ };
673
+
674
+ match src2.clone().to_reg_mem() {
675
+ RegMem::Reg { reg } => {
676
+ let reg = allocs.next(reg);
677
+ if *size == OperandSize::Size8 {
678
+ rex.always_emit_if_8bit_needed(reg);
679
+ }
680
+ let reg_e = int_reg_enc(reg);
681
+ emit_std_enc_enc(sink, prefix, opcode, 1, 4, reg_e, rex);
682
+ }
683
+ RegMem::Mem { addr: src } => {
684
+ let amode = src.finalize(state, sink).with_allocs(allocs);
685
+ emit_std_enc_mem(sink, prefix, opcode, 1, 4, &amode, rex, 0);
686
+ }
687
+ }
688
+ }
689
+
690
+ Inst::SignExtendData { size, src, dst } => {
691
+ let src = allocs.next(src.to_reg());
692
+ let dst = allocs.next(dst.to_reg().to_reg());
693
+ debug_assert_eq!(src, regs::rax());
694
+ if *size == OperandSize::Size8 {
695
+ debug_assert_eq!(dst, regs::rax());
696
+ } else {
697
+ debug_assert_eq!(dst, regs::rdx());
698
+ }
699
+ match size {
700
+ OperandSize::Size8 => {
701
+ sink.put1(0x66);
702
+ sink.put1(0x98);
703
+ }
704
+ OperandSize::Size16 => {
705
+ sink.put1(0x66);
706
+ sink.put1(0x99);
707
+ }
708
+ OperandSize::Size32 => sink.put1(0x99),
709
+ OperandSize::Size64 => {
710
+ sink.put1(0x48);
711
+ sink.put1(0x99);
712
+ }
713
+ }
714
+ }
715
+
716
+ Inst::CheckedSRemSeq { divisor, .. } | Inst::CheckedSRemSeq8 { divisor, .. } => {
717
+ let divisor = allocs.next(divisor.to_reg());
718
+
719
+ // Validate that the register constraints of the dividend and the
720
+ // destination are all as expected.
721
+ let (dst, size) = match inst {
722
+ Inst::CheckedSRemSeq {
723
+ dividend_lo,
724
+ dividend_hi,
725
+ dst_quotient,
726
+ dst_remainder,
727
+ size,
728
+ ..
729
+ } => {
730
+ let dividend_lo = allocs.next(dividend_lo.to_reg());
731
+ let dividend_hi = allocs.next(dividend_hi.to_reg());
732
+ let dst_quotient = allocs.next(dst_quotient.to_reg().to_reg());
733
+ let dst_remainder = allocs.next(dst_remainder.to_reg().to_reg());
734
+ debug_assert_eq!(dividend_lo, regs::rax());
735
+ debug_assert_eq!(dividend_hi, regs::rdx());
736
+ debug_assert_eq!(dst_quotient, regs::rax());
737
+ debug_assert_eq!(dst_remainder, regs::rdx());
738
+ (regs::rdx(), *size)
739
+ }
740
+ Inst::CheckedSRemSeq8 { dividend, dst, .. } => {
741
+ let dividend = allocs.next(dividend.to_reg());
742
+ let dst = allocs.next(dst.to_reg().to_reg());
743
+ debug_assert_eq!(dividend, regs::rax());
744
+ debug_assert_eq!(dst, regs::rax());
745
+ (regs::rax(), OperandSize::Size8)
746
+ }
747
+ _ => unreachable!(),
748
+ };
749
+
750
+ // Generates the following code sequence:
751
+ //
752
+ // cmp -1 %divisor
753
+ // jnz $do_op
754
+ //
755
+ // ;; for srem, result is 0
756
+ // mov #0, %dst
757
+ // j $done
758
+ //
759
+ // $do_op:
760
+ // idiv %divisor
761
+ //
762
+ // $done:
763
+
764
+ let do_op = sink.get_label();
765
+ let done_label = sink.get_label();
766
+
767
+ // Check if the divisor is -1, and if it isn't then immediately
768
+ // go to the `idiv`.
769
+ let inst = Inst::cmp_rmi_r(size, RegMemImm::imm(0xffffffff), divisor);
770
+ inst.emit(&[], sink, info, state);
771
+ one_way_jmp(sink, CC::NZ, do_op);
772
+
773
+ // ... otherwise the divisor is -1 and the result is always 0. This
774
+ // is written to the destination register which will be %rax for
775
+ // 8-bit srem and %rdx otherwise.
776
+ //
777
+ // Note that for 16-to-64-bit srem operations this leaves the
778
+ // second destination, %rax, unchanged. This isn't semantically
779
+ // correct if a lowering actually tries to use the `dst_quotient`
780
+ // output but for srem only the `dst_remainder` output is used for
781
+ // now.
782
+ let inst = Inst::imm(OperandSize::Size64, 0, Writable::from_reg(dst));
783
+ inst.emit(&[], sink, info, state);
784
+ let inst = Inst::jmp_known(done_label);
785
+ inst.emit(&[], sink, info, state);
786
+
787
+ // Here the `idiv` is executed, which is different depending on the
788
+ // size
789
+ sink.bind_label(do_op, state.ctrl_plane_mut());
790
+ let inst = match size {
791
+ OperandSize::Size8 => Inst::div8(
792
+ DivSignedness::Signed,
793
+ TrapCode::IntegerDivisionByZero,
794
+ RegMem::reg(divisor),
795
+ Gpr::new(regs::rax()).unwrap(),
796
+ Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
797
+ ),
798
+ _ => Inst::div(
799
+ size,
800
+ DivSignedness::Signed,
801
+ TrapCode::IntegerDivisionByZero,
802
+ RegMem::reg(divisor),
803
+ Gpr::new(regs::rax()).unwrap(),
804
+ Gpr::new(regs::rdx()).unwrap(),
805
+ Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
806
+ Writable::from_reg(Gpr::new(regs::rdx()).unwrap()),
807
+ ),
808
+ };
809
+ inst.emit(&[], sink, info, state);
810
+
811
+ sink.bind_label(done_label, state.ctrl_plane_mut());
812
+ }
813
+
814
+ Inst::Imm {
815
+ dst_size,
816
+ simm64,
817
+ dst,
818
+ } => {
819
+ let dst = allocs.next(dst.to_reg().to_reg());
820
+ let enc_dst = int_reg_enc(dst);
821
+ if *dst_size == OperandSize::Size64 {
822
+ if low32_will_sign_extend_to_64(*simm64) {
823
+ // Sign-extended move imm32.
824
+ emit_std_enc_enc(
825
+ sink,
826
+ LegacyPrefixes::None,
827
+ 0xC7,
828
+ 1,
829
+ /* subopcode */ 0,
830
+ enc_dst,
831
+ RexFlags::set_w(),
832
+ );
833
+ sink.put4(*simm64 as u32);
834
+ } else {
835
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
836
+ sink.put1(0xB8 | (enc_dst & 7));
837
+ sink.put8(*simm64);
838
+ }
839
+ } else {
840
+ if ((enc_dst >> 3) & 1) == 1 {
841
+ sink.put1(0x41);
842
+ }
843
+ sink.put1(0xB8 | (enc_dst & 7));
844
+ sink.put4(*simm64 as u32);
845
+ }
846
+ }
847
+
848
+ Inst::MovImmM { size, simm32, dst } => {
849
+ let dst = &dst.finalize(state, sink).with_allocs(allocs);
850
+ let default_rex = RexFlags::clear_w();
851
+ let default_opcode = 0xC7;
852
+ let bytes = size.to_bytes();
853
+ let prefix = LegacyPrefixes::None;
854
+
855
+ let (opcode, rex, size, prefix) = match *size {
856
+ // In the 8-bit case, we don't need to enforce REX flags via
857
+ // `always_emit_if_8bit_needed()` since the destination
858
+ // operand is a memory operand, not a possibly 8-bit register.
859
+ OperandSize::Size8 => (0xC6, default_rex, bytes, prefix),
860
+ OperandSize::Size16 => (0xC7, default_rex, bytes, LegacyPrefixes::_66),
861
+ OperandSize::Size64 => (default_opcode, RexFlags::from(*size), bytes, prefix),
862
+
863
+ _ => (default_opcode, default_rex, bytes, prefix),
864
+ };
865
+
866
+ // 8-bit C6 /0 ib
867
+ // 16-bit 0x66 C7 /0 iw
868
+ // 32-bit C7 /0 id
869
+ // 64-bit REX.W C7 /0 id
870
+ emit_std_enc_mem(sink, prefix, opcode, 1, /*subopcode*/ 0, dst, rex, 0);
871
+ emit_simm(sink, size, *simm32 as u32);
872
+ }
873
+
874
+ Inst::MovRR { size, src, dst } => {
875
+ let src = allocs.next(src.to_reg());
876
+ let dst = allocs.next(dst.to_reg().to_reg());
877
+ emit_std_reg_reg(
878
+ sink,
879
+ LegacyPrefixes::None,
880
+ 0x89,
881
+ 1,
882
+ src,
883
+ dst,
884
+ RexFlags::from(*size),
885
+ );
886
+ }
887
+
888
+ Inst::MovFromPReg { src, dst } => {
889
+ allocs.next_fixed_nonallocatable(*src);
890
+ let src: Reg = (*src).into();
891
+ debug_assert!([regs::rsp(), regs::rbp(), regs::pinned_reg()].contains(&src));
892
+ let src = Gpr::new(src).unwrap();
893
+ let size = OperandSize::Size64;
894
+ let dst = allocs.next(dst.to_reg().to_reg());
895
+ let dst = WritableGpr::from_writable_reg(Writable::from_reg(dst)).unwrap();
896
+ Inst::MovRR { size, src, dst }.emit(&[], sink, info, state);
897
+ }
898
+
899
+ Inst::MovToPReg { src, dst } => {
900
+ let src = allocs.next(src.to_reg());
901
+ let src = Gpr::new(src).unwrap();
902
+ allocs.next_fixed_nonallocatable(*dst);
903
+ let dst: Reg = (*dst).into();
904
+ debug_assert!([regs::rsp(), regs::rbp(), regs::pinned_reg()].contains(&dst));
905
+ let dst = WritableGpr::from_writable_reg(Writable::from_reg(dst)).unwrap();
906
+ let size = OperandSize::Size64;
907
+ Inst::MovRR { size, src, dst }.emit(&[], sink, info, state);
908
+ }
909
+
910
+ Inst::MovzxRmR { ext_mode, src, dst } => {
911
+ let dst = allocs.next(dst.to_reg().to_reg());
912
+ let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
913
+ ExtMode::BL => {
914
+ // MOVZBL is (REX.W==0) 0F B6 /r
915
+ (0x0FB6, 2, RexFlags::clear_w())
916
+ }
917
+ ExtMode::BQ => {
918
+ // MOVZBQ is (REX.W==1) 0F B6 /r
919
+ // I'm not sure why the Intel manual offers different
920
+ // encodings for MOVZBQ than for MOVZBL. AIUI they should
921
+ // achieve the same, since MOVZBL is just going to zero out
922
+ // the upper half of the destination anyway.
923
+ (0x0FB6, 2, RexFlags::set_w())
924
+ }
925
+ ExtMode::WL => {
926
+ // MOVZWL is (REX.W==0) 0F B7 /r
927
+ (0x0FB7, 2, RexFlags::clear_w())
928
+ }
929
+ ExtMode::WQ => {
930
+ // MOVZWQ is (REX.W==1) 0F B7 /r
931
+ (0x0FB7, 2, RexFlags::set_w())
932
+ }
933
+ ExtMode::LQ => {
934
+ // This is just a standard 32 bit load, and we rely on the
935
+ // default zero-extension rule to perform the extension.
936
+ // Note that in reg/reg mode, gcc seems to use the swapped form R/RM, which we
937
+ // don't do here, since it's the same encoding size.
938
+ // MOV r/m32, r32 is (REX.W==0) 8B /r
939
+ (0x8B, 1, RexFlags::clear_w())
940
+ }
941
+ };
942
+
943
+ match src.clone().to_reg_mem() {
944
+ RegMem::Reg { reg: src } => {
945
+ let src = allocs.next(src);
946
+ match ext_mode {
947
+ ExtMode::BL | ExtMode::BQ => {
948
+ // A redundant REX prefix must be emitted for certain register inputs.
949
+ rex_flags.always_emit_if_8bit_needed(src);
950
+ }
951
+ _ => {}
952
+ }
953
+ emit_std_reg_reg(
954
+ sink,
955
+ LegacyPrefixes::None,
956
+ opcodes,
957
+ num_opcodes,
958
+ dst,
959
+ src,
960
+ rex_flags,
961
+ )
962
+ }
963
+
964
+ RegMem::Mem { addr: src } => {
965
+ let src = &src.finalize(state, sink).with_allocs(allocs);
966
+
967
+ emit_std_reg_mem(
968
+ sink,
969
+ LegacyPrefixes::None,
970
+ opcodes,
971
+ num_opcodes,
972
+ dst,
973
+ src,
974
+ rex_flags,
975
+ 0,
976
+ )
977
+ }
978
+ }
979
+ }
980
+
981
+ Inst::Mov64MR { src, dst } => {
982
+ let dst = allocs.next(dst.to_reg().to_reg());
983
+ let src = &src.finalize(state, sink).with_allocs(allocs);
984
+
985
+ emit_std_reg_mem(
986
+ sink,
987
+ LegacyPrefixes::None,
988
+ 0x8B,
989
+ 1,
990
+ dst,
991
+ src,
992
+ RexFlags::set_w(),
993
+ 0,
994
+ )
995
+ }
996
+
997
+ Inst::LoadEffectiveAddress { addr, dst, size } => {
998
+ let dst = allocs.next(dst.to_reg().to_reg());
999
+ let amode = addr.finalize(state, sink).with_allocs(allocs);
1000
+
1001
+ // If this `lea` can actually get encoded as an `add` then do that
1002
+ // instead. Currently all candidate `iadd`s become an `lea`
1003
+ // pseudo-instruction here but maximizing the sue of `lea` is not
1004
+ // necessarily optimal. The `lea` instruction goes through dedicated
1005
+ // address units on cores which are finite and disjoint from the
1006
+ // general ALU, so if everything uses `lea` then those units can get
1007
+ // saturated while leaving the ALU idle.
1008
+ //
1009
+ // To help make use of more parts of a cpu, this attempts to use
1010
+ // `add` when it's semantically equivalent to `lea`, or otherwise
1011
+ // when the `dst` register is the same as the `base` or `index`
1012
+ // register.
1013
+ //
1014
+ // FIXME: ideally regalloc is informed of this constraint. Register
1015
+ // allocation of `lea` should "attempt" to put the `base` in the
1016
+ // same register as `dst` but not at the expense of generating a
1017
+ // `mov` instruction. Currently that's not possible but perhaps one
1018
+ // day it may be worth it.
1019
+ match amode {
1020
+ // If `base == dst` then this is `add $imm, %dst`, so encode
1021
+ // that instead.
1022
+ Amode::ImmReg {
1023
+ simm32,
1024
+ base,
1025
+ flags: _,
1026
+ } if base == dst => {
1027
+ let inst = Inst::alu_rmi_r(
1028
+ *size,
1029
+ AluRmiROpcode::Add,
1030
+ RegMemImm::imm(simm32 as u32),
1031
+ Writable::from_reg(dst),
1032
+ );
1033
+ inst.emit(&[], sink, info, state);
1034
+ }
1035
+ // If the offset is 0 and the shift is 0 (meaning multiplication
1036
+ // by 1) then:
1037
+ //
1038
+ // * If `base == dst`, then this is `add %index, %base`
1039
+ // * If `index == dst`, then this is `add %base, %index`
1040
+ //
1041
+ // Encode the appropriate instruction here in that case.
1042
+ Amode::ImmRegRegShift {
1043
+ simm32: 0,
1044
+ base,
1045
+ index,
1046
+ shift: 0,
1047
+ flags: _,
1048
+ } if base == dst || index == dst => {
1049
+ let (dst, operand) = if base == dst {
1050
+ (base, index)
1051
+ } else {
1052
+ (index, base)
1053
+ };
1054
+ let inst = Inst::alu_rmi_r(
1055
+ *size,
1056
+ AluRmiROpcode::Add,
1057
+ RegMemImm::reg(operand.to_reg()),
1058
+ Writable::from_reg(dst.to_reg()),
1059
+ );
1060
+ inst.emit(&[], sink, info, state);
1061
+ }
1062
+
1063
+ // If `lea`'s 3-operand mode is leveraged by regalloc, or if
1064
+ // it's fancy like imm-plus-shift-plus-base, then `lea` is
1065
+ // actually emitted.
1066
+ _ => {
1067
+ let flags = match size {
1068
+ OperandSize::Size32 => RexFlags::clear_w(),
1069
+ OperandSize::Size64 => RexFlags::set_w(),
1070
+ _ => unreachable!(),
1071
+ };
1072
+ emit_std_reg_mem(sink, LegacyPrefixes::None, 0x8D, 1, dst, &amode, flags, 0);
1073
+ }
1074
+ };
1075
+ }
1076
+
1077
+ Inst::MovsxRmR { ext_mode, src, dst } => {
1078
+ let dst = allocs.next(dst.to_reg().to_reg());
1079
+ let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
1080
+ ExtMode::BL => {
1081
+ // MOVSBL is (REX.W==0) 0F BE /r
1082
+ (0x0FBE, 2, RexFlags::clear_w())
1083
+ }
1084
+ ExtMode::BQ => {
1085
+ // MOVSBQ is (REX.W==1) 0F BE /r
1086
+ (0x0FBE, 2, RexFlags::set_w())
1087
+ }
1088
+ ExtMode::WL => {
1089
+ // MOVSWL is (REX.W==0) 0F BF /r
1090
+ (0x0FBF, 2, RexFlags::clear_w())
1091
+ }
1092
+ ExtMode::WQ => {
1093
+ // MOVSWQ is (REX.W==1) 0F BF /r
1094
+ (0x0FBF, 2, RexFlags::set_w())
1095
+ }
1096
+ ExtMode::LQ => {
1097
+ // MOVSLQ is (REX.W==1) 63 /r
1098
+ (0x63, 1, RexFlags::set_w())
1099
+ }
1100
+ };
1101
+
1102
+ match src.clone().to_reg_mem() {
1103
+ RegMem::Reg { reg: src } => {
1104
+ let src = allocs.next(src);
1105
+ match ext_mode {
1106
+ ExtMode::BL | ExtMode::BQ => {
1107
+ // A redundant REX prefix must be emitted for certain register inputs.
1108
+ rex_flags.always_emit_if_8bit_needed(src);
1109
+ }
1110
+ _ => {}
1111
+ }
1112
+ emit_std_reg_reg(
1113
+ sink,
1114
+ LegacyPrefixes::None,
1115
+ opcodes,
1116
+ num_opcodes,
1117
+ dst,
1118
+ src,
1119
+ rex_flags,
1120
+ )
1121
+ }
1122
+
1123
+ RegMem::Mem { addr: src } => {
1124
+ let src = &src.finalize(state, sink).with_allocs(allocs);
1125
+
1126
+ emit_std_reg_mem(
1127
+ sink,
1128
+ LegacyPrefixes::None,
1129
+ opcodes,
1130
+ num_opcodes,
1131
+ dst,
1132
+ src,
1133
+ rex_flags,
1134
+ 0,
1135
+ )
1136
+ }
1137
+ }
1138
+ }
1139
+
1140
+ Inst::MovRM { size, src, dst } => {
1141
+ let src = allocs.next(src.to_reg());
1142
+ let dst = &dst.finalize(state, sink).with_allocs(allocs);
1143
+
1144
+ let prefix = match size {
1145
+ OperandSize::Size16 => LegacyPrefixes::_66,
1146
+ _ => LegacyPrefixes::None,
1147
+ };
1148
+
1149
+ let opcode = match size {
1150
+ OperandSize::Size8 => 0x88,
1151
+ _ => 0x89,
1152
+ };
1153
+
1154
+ // This is one of the few places where the presence of a
1155
+ // redundant REX prefix changes the meaning of the
1156
+ // instruction.
1157
+ let rex = RexFlags::from((*size, src));
1158
+
1159
+ // 8-bit: MOV r8, r/m8 is (REX.W==0) 88 /r
1160
+ // 16-bit: MOV r16, r/m16 is 66 (REX.W==0) 89 /r
1161
+ // 32-bit: MOV r32, r/m32 is (REX.W==0) 89 /r
1162
+ // 64-bit: MOV r64, r/m64 is (REX.W==1) 89 /r
1163
+ emit_std_reg_mem(sink, prefix, opcode, 1, src, dst, rex, 0);
1164
+ }
1165
+
1166
+ Inst::ShiftR {
1167
+ size,
1168
+ kind,
1169
+ src,
1170
+ num_bits,
1171
+ dst,
1172
+ } => {
1173
+ let src = allocs.next(src.to_reg());
1174
+ let dst = allocs.next(dst.to_reg().to_reg());
1175
+ debug_assert_eq!(src, dst);
1176
+ let subopcode = match kind {
1177
+ ShiftKind::RotateLeft => 0,
1178
+ ShiftKind::RotateRight => 1,
1179
+ ShiftKind::ShiftLeft => 4,
1180
+ ShiftKind::ShiftRightLogical => 5,
1181
+ ShiftKind::ShiftRightArithmetic => 7,
1182
+ };
1183
+ let enc_dst = int_reg_enc(dst);
1184
+ let rex_flags = RexFlags::from((*size, dst));
1185
+ match num_bits.clone().to_imm8_reg() {
1186
+ Imm8Reg::Reg { reg } => {
1187
+ let reg = allocs.next(reg);
1188
+ debug_assert_eq!(reg, regs::rcx());
1189
+ let (opcode, prefix) = match size {
1190
+ OperandSize::Size8 => (0xD2, LegacyPrefixes::None),
1191
+ OperandSize::Size16 => (0xD3, LegacyPrefixes::_66),
1192
+ OperandSize::Size32 => (0xD3, LegacyPrefixes::None),
1193
+ OperandSize::Size64 => (0xD3, LegacyPrefixes::None),
1194
+ };
1195
+
1196
+ // SHL/SHR/SAR %cl, reg8 is (REX.W==0) D2 /subopcode
1197
+ // SHL/SHR/SAR %cl, reg16 is 66 (REX.W==0) D3 /subopcode
1198
+ // SHL/SHR/SAR %cl, reg32 is (REX.W==0) D3 /subopcode
1199
+ // SHL/SHR/SAR %cl, reg64 is (REX.W==1) D3 /subopcode
1200
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
1201
+ }
1202
+
1203
+ Imm8Reg::Imm8 { imm: num_bits } => {
1204
+ let (opcode, prefix) = match size {
1205
+ OperandSize::Size8 => (0xC0, LegacyPrefixes::None),
1206
+ OperandSize::Size16 => (0xC1, LegacyPrefixes::_66),
1207
+ OperandSize::Size32 => (0xC1, LegacyPrefixes::None),
1208
+ OperandSize::Size64 => (0xC1, LegacyPrefixes::None),
1209
+ };
1210
+
1211
+ // SHL/SHR/SAR $ib, reg8 is (REX.W==0) C0 /subopcode
1212
+ // SHL/SHR/SAR $ib, reg16 is 66 (REX.W==0) C1 /subopcode
1213
+ // SHL/SHR/SAR $ib, reg32 is (REX.W==0) C1 /subopcode ib
1214
+ // SHL/SHR/SAR $ib, reg64 is (REX.W==1) C1 /subopcode ib
1215
+ // When the shift amount is 1, there's an even shorter encoding, but we don't
1216
+ // bother with that nicety here.
1217
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
1218
+ sink.put1(num_bits);
1219
+ }
1220
+ }
1221
+ }
1222
+
1223
+ Inst::XmmRmiReg {
1224
+ opcode,
1225
+ src1,
1226
+ src2,
1227
+ dst,
1228
+ } => {
1229
+ let src1 = allocs.next(src1.to_reg());
1230
+ let dst = allocs.next(dst.to_reg().to_reg());
1231
+ debug_assert_eq!(src1, dst);
1232
+ let rex = RexFlags::clear_w();
1233
+ let prefix = LegacyPrefixes::_66;
1234
+ let src2 = src2.clone().to_reg_mem_imm();
1235
+ if let RegMemImm::Imm { simm32 } = src2 {
1236
+ let (opcode_bytes, reg_digit) = match opcode {
1237
+ SseOpcode::Psllw => (0x0F71, 6),
1238
+ SseOpcode::Pslld => (0x0F72, 6),
1239
+ SseOpcode::Psllq => (0x0F73, 6),
1240
+ SseOpcode::Psraw => (0x0F71, 4),
1241
+ SseOpcode::Psrad => (0x0F72, 4),
1242
+ SseOpcode::Psrlw => (0x0F71, 2),
1243
+ SseOpcode::Psrld => (0x0F72, 2),
1244
+ SseOpcode::Psrlq => (0x0F73, 2),
1245
+ _ => panic!("invalid opcode: {}", opcode),
1246
+ };
1247
+ let dst_enc = reg_enc(dst);
1248
+ emit_std_enc_enc(sink, prefix, opcode_bytes, 2, reg_digit, dst_enc, rex);
1249
+ let imm = (simm32)
1250
+ .try_into()
1251
+ .expect("the immediate must be convertible to a u8");
1252
+ sink.put1(imm);
1253
+ } else {
1254
+ let opcode_bytes = match opcode {
1255
+ SseOpcode::Psllw => 0x0FF1,
1256
+ SseOpcode::Pslld => 0x0FF2,
1257
+ SseOpcode::Psllq => 0x0FF3,
1258
+ SseOpcode::Psraw => 0x0FE1,
1259
+ SseOpcode::Psrad => 0x0FE2,
1260
+ SseOpcode::Psrlw => 0x0FD1,
1261
+ SseOpcode::Psrld => 0x0FD2,
1262
+ SseOpcode::Psrlq => 0x0FD3,
1263
+ _ => panic!("invalid opcode: {}", opcode),
1264
+ };
1265
+
1266
+ match src2 {
1267
+ RegMemImm::Reg { reg } => {
1268
+ let reg = allocs.next(reg);
1269
+ emit_std_reg_reg(sink, prefix, opcode_bytes, 2, dst, reg, rex);
1270
+ }
1271
+ RegMemImm::Mem { addr } => {
1272
+ let addr = &addr.finalize(state, sink).with_allocs(allocs);
1273
+ emit_std_reg_mem(sink, prefix, opcode_bytes, 2, dst, addr, rex, 0);
1274
+ }
1275
+ RegMemImm::Imm { .. } => unreachable!(),
1276
+ }
1277
+ };
1278
+ }
1279
+
1280
+ Inst::CmpRmiR {
1281
+ size,
1282
+ src: src_e,
1283
+ dst: reg_g,
1284
+ opcode,
1285
+ } => {
1286
+ let reg_g = allocs.next(reg_g.to_reg());
1287
+
1288
+ let is_cmp = match opcode {
1289
+ CmpOpcode::Cmp => true,
1290
+ CmpOpcode::Test => false,
1291
+ };
1292
+
1293
+ let mut prefix = LegacyPrefixes::None;
1294
+ if *size == OperandSize::Size16 {
1295
+ prefix = LegacyPrefixes::_66;
1296
+ }
1297
+ // A redundant REX prefix can change the meaning of this instruction.
1298
+ let mut rex = RexFlags::from((*size, reg_g));
1299
+
1300
+ match src_e.clone().to_reg_mem_imm() {
1301
+ RegMemImm::Reg { reg: reg_e } => {
1302
+ let reg_e = allocs.next(reg_e);
1303
+ if *size == OperandSize::Size8 {
1304
+ // Check whether the E register forces the use of a redundant REX.
1305
+ rex.always_emit_if_8bit_needed(reg_e);
1306
+ }
1307
+
1308
+ // Use the swapped operands encoding for CMP, to stay consistent with the output of
1309
+ // gcc/llvm.
1310
+ let opcode = match (*size, is_cmp) {
1311
+ (OperandSize::Size8, true) => 0x38,
1312
+ (_, true) => 0x39,
1313
+ (OperandSize::Size8, false) => 0x84,
1314
+ (_, false) => 0x85,
1315
+ };
1316
+ emit_std_reg_reg(sink, prefix, opcode, 1, reg_e, reg_g, rex);
1317
+ }
1318
+
1319
+ RegMemImm::Mem { addr } => {
1320
+ let addr = &addr.finalize(state, sink).with_allocs(allocs);
1321
+ // Whereas here we revert to the "normal" G-E ordering for CMP.
1322
+ let opcode = match (*size, is_cmp) {
1323
+ (OperandSize::Size8, true) => 0x3A,
1324
+ (_, true) => 0x3B,
1325
+ (OperandSize::Size8, false) => 0x84,
1326
+ (_, false) => 0x85,
1327
+ };
1328
+ emit_std_reg_mem(sink, prefix, opcode, 1, reg_g, addr, rex, 0);
1329
+ }
1330
+
1331
+ RegMemImm::Imm { simm32 } => {
1332
+ // FIXME JRS 2020Feb11: there are shorter encodings for
1333
+ // cmp $imm, rax/eax/ax/al.
1334
+ let use_imm8 = is_cmp && low8_will_sign_extend_to_32(simm32);
1335
+
1336
+ // And also here we use the "normal" G-E ordering.
1337
+ let opcode = if is_cmp {
1338
+ if *size == OperandSize::Size8 {
1339
+ 0x80
1340
+ } else if use_imm8 {
1341
+ 0x83
1342
+ } else {
1343
+ 0x81
1344
+ }
1345
+ } else {
1346
+ if *size == OperandSize::Size8 {
1347
+ 0xF6
1348
+ } else {
1349
+ 0xF7
1350
+ }
1351
+ };
1352
+ let subopcode = if is_cmp { 7 } else { 0 };
1353
+
1354
+ let enc_g = int_reg_enc(reg_g);
1355
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_g, rex);
1356
+ emit_simm(sink, if use_imm8 { 1 } else { size.to_bytes() }, simm32);
1357
+ }
1358
+ }
1359
+ }
1360
+
1361
+ Inst::Setcc { cc, dst } => {
1362
+ let dst = allocs.next(dst.to_reg().to_reg());
1363
+ let opcode = 0x0f90 + cc.get_enc() as u32;
1364
+ let mut rex_flags = RexFlags::clear_w();
1365
+ rex_flags.always_emit();
1366
+ emit_std_enc_enc(
1367
+ sink,
1368
+ LegacyPrefixes::None,
1369
+ opcode,
1370
+ 2,
1371
+ 0,
1372
+ reg_enc(dst),
1373
+ rex_flags,
1374
+ );
1375
+ }
1376
+
1377
+ Inst::Bswap { size, src, dst } => {
1378
+ let src = allocs.next(src.to_reg());
1379
+ let dst = allocs.next(dst.to_reg().to_reg());
1380
+ debug_assert_eq!(src, dst);
1381
+ let enc_reg = int_reg_enc(dst);
1382
+
1383
+ // BSWAP reg32 is (REX.W==0) 0F C8
1384
+ // BSWAP reg64 is (REX.W==1) 0F C8
1385
+ let rex_flags = RexFlags::from(*size);
1386
+ rex_flags.emit_one_op(sink, enc_reg);
1387
+
1388
+ sink.put1(0x0F);
1389
+ sink.put1(0xC8 | (enc_reg & 7));
1390
+ }
1391
+
1392
+ Inst::Cmove {
1393
+ size,
1394
+ cc,
1395
+ consequent,
1396
+ alternative,
1397
+ dst,
1398
+ } => {
1399
+ let alternative = allocs.next(alternative.to_reg());
1400
+ let dst = allocs.next(dst.to_reg().to_reg());
1401
+ debug_assert_eq!(alternative, dst);
1402
+ let rex_flags = RexFlags::from(*size);
1403
+ let prefix = match size {
1404
+ OperandSize::Size16 => LegacyPrefixes::_66,
1405
+ OperandSize::Size32 => LegacyPrefixes::None,
1406
+ OperandSize::Size64 => LegacyPrefixes::None,
1407
+ _ => unreachable!("invalid size spec for cmove"),
1408
+ };
1409
+ let opcode = 0x0F40 + cc.get_enc() as u32;
1410
+ match consequent.clone().to_reg_mem() {
1411
+ RegMem::Reg { reg } => {
1412
+ let reg = allocs.next(reg);
1413
+ emit_std_reg_reg(sink, prefix, opcode, 2, dst, reg, rex_flags);
1414
+ }
1415
+ RegMem::Mem { addr } => {
1416
+ let addr = &addr.finalize(state, sink).with_allocs(allocs);
1417
+ emit_std_reg_mem(sink, prefix, opcode, 2, dst, addr, rex_flags, 0);
1418
+ }
1419
+ }
1420
+ }
1421
+
1422
+ Inst::XmmCmove {
1423
+ ty,
1424
+ cc,
1425
+ consequent,
1426
+ alternative,
1427
+ dst,
1428
+ } => {
1429
+ let alternative = allocs.next(alternative.to_reg());
1430
+ let dst = allocs.next(dst.to_reg().to_reg());
1431
+ debug_assert_eq!(alternative, dst);
1432
+ let consequent = consequent.clone().to_reg_mem().with_allocs(allocs);
1433
+
1434
+ // Lowering of the Select IR opcode when the input is an fcmp relies on the fact that
1435
+ // this doesn't clobber flags. Make sure to not do so here.
1436
+ let next = sink.get_label();
1437
+
1438
+ // Jump if cc is *not* set.
1439
+ one_way_jmp(sink, cc.invert(), next);
1440
+
1441
+ let op = match *ty {
1442
+ types::F64 => SseOpcode::Movsd,
1443
+ types::F32 => SseOpcode::Movsd,
1444
+ types::F32X4 => SseOpcode::Movaps,
1445
+ types::F64X2 => SseOpcode::Movapd,
1446
+ ty => {
1447
+ debug_assert!(ty.is_vector() && ty.bytes() == 16);
1448
+ SseOpcode::Movdqa
1449
+ }
1450
+ };
1451
+ let inst = Inst::xmm_unary_rm_r(op, consequent, Writable::from_reg(dst));
1452
+ inst.emit(&[], sink, info, state);
1453
+
1454
+ sink.bind_label(next, state.ctrl_plane_mut());
1455
+ }
1456
+
1457
+ Inst::Push64 { src } => {
1458
+ let src = src.clone().to_reg_mem_imm().with_allocs(allocs);
1459
+
1460
+ match src {
1461
+ RegMemImm::Reg { reg } => {
1462
+ let enc_reg = int_reg_enc(reg);
1463
+ let rex = 0x40 | ((enc_reg >> 3) & 1);
1464
+ if rex != 0x40 {
1465
+ sink.put1(rex);
1466
+ }
1467
+ sink.put1(0x50 | (enc_reg & 7));
1468
+ }
1469
+
1470
+ RegMemImm::Mem { addr } => {
1471
+ let addr = &addr.finalize(state, sink);
1472
+ emit_std_enc_mem(
1473
+ sink,
1474
+ LegacyPrefixes::None,
1475
+ 0xFF,
1476
+ 1,
1477
+ 6, /*subopcode*/
1478
+ addr,
1479
+ RexFlags::clear_w(),
1480
+ 0,
1481
+ );
1482
+ }
1483
+
1484
+ RegMemImm::Imm { simm32 } => {
1485
+ if low8_will_sign_extend_to_64(simm32) {
1486
+ sink.put1(0x6A);
1487
+ sink.put1(simm32 as u8);
1488
+ } else {
1489
+ sink.put1(0x68);
1490
+ sink.put4(simm32);
1491
+ }
1492
+ }
1493
+ }
1494
+ }
1495
+
1496
+ Inst::Pop64 { dst } => {
1497
+ let dst = allocs.next(dst.to_reg().to_reg());
1498
+ let enc_dst = int_reg_enc(dst);
1499
+ if enc_dst >= 8 {
1500
+ // 0x41 == REX.{W=0, B=1}. It seems that REX.W is irrelevant here.
1501
+ sink.put1(0x41);
1502
+ }
1503
+ sink.put1(0x58 + (enc_dst & 7));
1504
+ }
1505
+
1506
+ Inst::StackProbeLoop {
1507
+ tmp,
1508
+ frame_size,
1509
+ guard_size,
1510
+ } => {
1511
+ assert!(info.flags.enable_probestack());
1512
+ assert!(guard_size.is_power_of_two());
1513
+
1514
+ let tmp = allocs.next_writable(*tmp);
1515
+
1516
+ // Number of probes that we need to perform
1517
+ let probe_count = align_to(*frame_size, *guard_size) / guard_size;
1518
+
1519
+ // The inline stack probe loop has 3 phases:
1520
+ //
1521
+ // We generate the "guard area" register which is essentially the frame_size aligned to
1522
+ // guard_size. We copy the stack pointer and subtract the guard area from it. This
1523
+ // gets us a register that we can use to compare when looping.
1524
+ //
1525
+ // After that we emit the loop. Essentially we just adjust the stack pointer one guard_size'd
1526
+ // distance at a time and then touch the stack by writing anything to it. We use the previously
1527
+ // created "guard area" register to know when to stop looping.
1528
+ //
1529
+ // When we have touched all the pages that we need, we have to restore the stack pointer
1530
+ // to where it was before.
1531
+ //
1532
+ // Generate the following code:
1533
+ // mov tmp_reg, rsp
1534
+ // sub tmp_reg, guard_size * probe_count
1535
+ // .loop_start:
1536
+ // sub rsp, guard_size
1537
+ // mov [rsp], rsp
1538
+ // cmp rsp, tmp_reg
1539
+ // jne .loop_start
1540
+ // add rsp, guard_size * probe_count
1541
+
1542
+ // Create the guard bound register
1543
+ // mov tmp_reg, rsp
1544
+ let inst = Inst::gen_move(tmp, regs::rsp(), types::I64);
1545
+ inst.emit(&[], sink, info, state);
1546
+
1547
+ // sub tmp_reg, GUARD_SIZE * probe_count
1548
+ let inst = Inst::alu_rmi_r(
1549
+ OperandSize::Size64,
1550
+ AluRmiROpcode::Sub,
1551
+ RegMemImm::imm(guard_size * probe_count),
1552
+ tmp,
1553
+ );
1554
+ inst.emit(&[], sink, info, state);
1555
+
1556
+ // Emit the main loop!
1557
+ let loop_start = sink.get_label();
1558
+ sink.bind_label(loop_start, state.ctrl_plane_mut());
1559
+
1560
+ // sub rsp, GUARD_SIZE
1561
+ let inst = Inst::alu_rmi_r(
1562
+ OperandSize::Size64,
1563
+ AluRmiROpcode::Sub,
1564
+ RegMemImm::imm(*guard_size),
1565
+ Writable::from_reg(regs::rsp()),
1566
+ );
1567
+ inst.emit(&[], sink, info, state);
1568
+
1569
+ // TODO: `mov [rsp], 0` would be better, but we don't have that instruction
1570
+ // Probe the stack! We don't use Inst::gen_store_stack here because we need a predictable
1571
+ // instruction size.
1572
+ // mov [rsp], rsp
1573
+ let inst = Inst::mov_r_m(
1574
+ OperandSize::Size32, // Use Size32 since it saves us one byte
1575
+ regs::rsp(),
1576
+ SyntheticAmode::Real(Amode::imm_reg(0, regs::rsp())),
1577
+ );
1578
+ inst.emit(&[], sink, info, state);
1579
+
1580
+ // Compare and jump if we are not done yet
1581
+ // cmp rsp, tmp_reg
1582
+ let inst = Inst::cmp_rmi_r(
1583
+ OperandSize::Size64,
1584
+ RegMemImm::reg(regs::rsp()),
1585
+ tmp.to_reg(),
1586
+ );
1587
+ inst.emit(&[], sink, info, state);
1588
+
1589
+ // jne .loop_start
1590
+ // TODO: Encoding the JmpIf as a short jump saves us 4 bytes here.
1591
+ one_way_jmp(sink, CC::NZ, loop_start);
1592
+
1593
+ // The regular prologue code is going to emit a `sub` after this, so we need to
1594
+ // reset the stack pointer
1595
+ //
1596
+ // TODO: It would be better if we could avoid the `add` + `sub` that is generated here
1597
+ // and in the stack adj portion of the prologue
1598
+ //
1599
+ // add rsp, GUARD_SIZE * probe_count
1600
+ let inst = Inst::alu_rmi_r(
1601
+ OperandSize::Size64,
1602
+ AluRmiROpcode::Add,
1603
+ RegMemImm::imm(guard_size * probe_count),
1604
+ Writable::from_reg(regs::rsp()),
1605
+ );
1606
+ inst.emit(&[], sink, info, state);
1607
+ }
1608
+
1609
+ Inst::CallKnown {
1610
+ dest,
1611
+ info: call_info,
1612
+ ..
1613
+ } => {
1614
+ if let Some(s) = state.take_stack_map() {
1615
+ sink.add_stack_map(StackMapExtent::UpcomingBytes(5), s);
1616
+ }
1617
+ sink.put1(0xE8);
1618
+ // The addend adjusts for the difference between the end of the instruction and the
1619
+ // beginning of the immediate field.
1620
+ emit_reloc(sink, Reloc::X86CallPCRel4, &dest, -4);
1621
+ sink.put4(0);
1622
+ if call_info.opcode.is_call() {
1623
+ sink.add_call_site(call_info.opcode);
1624
+ }
1625
+
1626
+ let callee_pop_size = i64::from(call_info.callee_pop_size);
1627
+ state.adjust_virtual_sp_offset(-callee_pop_size);
1628
+ }
1629
+
1630
+ Inst::ReturnCallKnown {
1631
+ callee,
1632
+ info: call_info,
1633
+ } => {
1634
+ emit_return_call_common_sequence(
1635
+ allocs,
1636
+ sink,
1637
+ info,
1638
+ state,
1639
+ call_info.new_stack_arg_size,
1640
+ call_info.old_stack_arg_size,
1641
+ call_info.ret_addr,
1642
+ call_info.fp,
1643
+ call_info.tmp,
1644
+ &call_info.uses,
1645
+ );
1646
+
1647
+ // Finally, jump to the callee!
1648
+ //
1649
+ // Note: this is not `Inst::Jmp { .. }.emit(..)` because we have
1650
+ // different metadata in this case: we don't have a label for the
1651
+ // target, but rather a function relocation.
1652
+ sink.put1(0xE9);
1653
+ // The addend adjusts for the difference between the end of the instruction and the
1654
+ // beginning of the immediate field.
1655
+ emit_reloc(sink, Reloc::X86CallPCRel4, &callee, -4);
1656
+ sink.put4(0);
1657
+ sink.add_call_site(ir::Opcode::ReturnCall);
1658
+ }
1659
+
1660
+ Inst::ReturnCallUnknown {
1661
+ callee,
1662
+ info: call_info,
1663
+ } => {
1664
+ let callee = callee.with_allocs(allocs);
1665
+
1666
+ emit_return_call_common_sequence(
1667
+ allocs,
1668
+ sink,
1669
+ info,
1670
+ state,
1671
+ call_info.new_stack_arg_size,
1672
+ call_info.old_stack_arg_size,
1673
+ call_info.ret_addr,
1674
+ call_info.fp,
1675
+ call_info.tmp,
1676
+ &call_info.uses,
1677
+ );
1678
+
1679
+ Inst::JmpUnknown { target: callee }.emit(&[], sink, info, state);
1680
+ sink.add_call_site(ir::Opcode::ReturnCallIndirect);
1681
+ }
1682
+
1683
+ Inst::CallUnknown {
1684
+ dest,
1685
+ info: call_info,
1686
+ ..
1687
+ } => {
1688
+ let dest = dest.with_allocs(allocs);
1689
+
1690
+ let start_offset = sink.cur_offset();
1691
+ match dest {
1692
+ RegMem::Reg { reg } => {
1693
+ let reg_enc = int_reg_enc(reg);
1694
+ emit_std_enc_enc(
1695
+ sink,
1696
+ LegacyPrefixes::None,
1697
+ 0xFF,
1698
+ 1,
1699
+ 2, /*subopcode*/
1700
+ reg_enc,
1701
+ RexFlags::clear_w(),
1702
+ );
1703
+ }
1704
+
1705
+ RegMem::Mem { addr } => {
1706
+ let addr = &addr.finalize(state, sink);
1707
+ emit_std_enc_mem(
1708
+ sink,
1709
+ LegacyPrefixes::None,
1710
+ 0xFF,
1711
+ 1,
1712
+ 2, /*subopcode*/
1713
+ addr,
1714
+ RexFlags::clear_w(),
1715
+ 0,
1716
+ );
1717
+ }
1718
+ }
1719
+ if let Some(s) = state.take_stack_map() {
1720
+ sink.add_stack_map(StackMapExtent::StartedAtOffset(start_offset), s);
1721
+ }
1722
+ if call_info.opcode.is_call() {
1723
+ sink.add_call_site(call_info.opcode);
1724
+ }
1725
+
1726
+ let callee_pop_size = i64::from(call_info.callee_pop_size);
1727
+ state.adjust_virtual_sp_offset(-callee_pop_size);
1728
+ }
1729
+
1730
+ Inst::Args { .. } => {}
1731
+ Inst::Rets { .. } => {}
1732
+
1733
+ Inst::Ret {
1734
+ stack_bytes_to_pop: 0,
1735
+ } => sink.put1(0xC3),
1736
+
1737
+ Inst::Ret { stack_bytes_to_pop } => {
1738
+ sink.put1(0xC2);
1739
+ sink.put2(u16::try_from(*stack_bytes_to_pop).unwrap());
1740
+ }
1741
+
1742
+ Inst::JmpKnown { dst } => {
1743
+ let br_start = sink.cur_offset();
1744
+ let br_disp_off = br_start + 1;
1745
+ let br_end = br_start + 5;
1746
+
1747
+ sink.use_label_at_offset(br_disp_off, *dst, LabelUse::JmpRel32);
1748
+ sink.add_uncond_branch(br_start, br_end, *dst);
1749
+
1750
+ sink.put1(0xE9);
1751
+ // Placeholder for the label value.
1752
+ sink.put4(0x0);
1753
+ }
1754
+
1755
+ Inst::JmpIf { cc, taken } => {
1756
+ let cond_start = sink.cur_offset();
1757
+ let cond_disp_off = cond_start + 2;
1758
+
1759
+ sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
1760
+ // Since this is not a terminator, don't enroll in the branch inversion mechanism.
1761
+
1762
+ sink.put1(0x0F);
1763
+ sink.put1(0x80 + cc.get_enc());
1764
+ // Placeholder for the label value.
1765
+ sink.put4(0x0);
1766
+ }
1767
+
1768
+ Inst::JmpCond {
1769
+ cc,
1770
+ taken,
1771
+ not_taken,
1772
+ } => {
1773
+ // If taken.
1774
+ let cond_start = sink.cur_offset();
1775
+ let cond_disp_off = cond_start + 2;
1776
+ let cond_end = cond_start + 6;
1777
+
1778
+ sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
1779
+ let inverted: [u8; 6] = [0x0F, 0x80 + (cc.invert().get_enc()), 0x00, 0x00, 0x00, 0x00];
1780
+ sink.add_cond_branch(cond_start, cond_end, *taken, &inverted[..]);
1781
+
1782
+ sink.put1(0x0F);
1783
+ sink.put1(0x80 + cc.get_enc());
1784
+ // Placeholder for the label value.
1785
+ sink.put4(0x0);
1786
+
1787
+ // If not taken.
1788
+ let uncond_start = sink.cur_offset();
1789
+ let uncond_disp_off = uncond_start + 1;
1790
+ let uncond_end = uncond_start + 5;
1791
+
1792
+ sink.use_label_at_offset(uncond_disp_off, *not_taken, LabelUse::JmpRel32);
1793
+ sink.add_uncond_branch(uncond_start, uncond_end, *not_taken);
1794
+
1795
+ sink.put1(0xE9);
1796
+ // Placeholder for the label value.
1797
+ sink.put4(0x0);
1798
+ }
1799
+
1800
+ Inst::JmpUnknown { target } => {
1801
+ let target = target.with_allocs(allocs);
1802
+
1803
+ match target {
1804
+ RegMem::Reg { reg } => {
1805
+ let reg_enc = int_reg_enc(reg);
1806
+ emit_std_enc_enc(
1807
+ sink,
1808
+ LegacyPrefixes::None,
1809
+ 0xFF,
1810
+ 1,
1811
+ 4, /*subopcode*/
1812
+ reg_enc,
1813
+ RexFlags::clear_w(),
1814
+ );
1815
+ }
1816
+
1817
+ RegMem::Mem { addr } => {
1818
+ let addr = &addr.finalize(state, sink);
1819
+ emit_std_enc_mem(
1820
+ sink,
1821
+ LegacyPrefixes::None,
1822
+ 0xFF,
1823
+ 1,
1824
+ 4, /*subopcode*/
1825
+ addr,
1826
+ RexFlags::clear_w(),
1827
+ 0,
1828
+ );
1829
+ }
1830
+ }
1831
+ }
1832
+
1833
+ Inst::JmpTableSeq {
1834
+ idx,
1835
+ tmp1,
1836
+ tmp2,
1837
+ ref targets,
1838
+ default_target,
1839
+ ..
1840
+ } => {
1841
+ let idx = allocs.next(*idx);
1842
+ let tmp1 = Writable::from_reg(allocs.next(tmp1.to_reg()));
1843
+ let tmp2 = Writable::from_reg(allocs.next(tmp2.to_reg()));
1844
+
1845
+ // This sequence is *one* instruction in the vcode, and is expanded only here at
1846
+ // emission time, because we cannot allow the regalloc to insert spills/reloads in
1847
+ // the middle; we depend on hardcoded PC-rel addressing below.
1848
+ //
1849
+ // We don't have to worry about emitting islands, because the only label-use type has a
1850
+ // maximum range of 2 GB. If we later consider using shorter-range label references,
1851
+ // this will need to be revisited.
1852
+
1853
+ // We generate the following sequence. Note that the only read of %idx is before the
1854
+ // write to %tmp2, so regalloc may use the same register for both; fix x64/inst/mod.rs
1855
+ // if you change this.
1856
+ // lea start_of_jump_table_offset(%rip), %tmp1
1857
+ // movslq [%tmp1, %idx, 4], %tmp2 ;; shift of 2, viz. multiply index by 4
1858
+ // addq %tmp2, %tmp1
1859
+ // j *%tmp1
1860
+ // $start_of_jump_table:
1861
+ // -- jump table entries
1862
+
1863
+ // Load base address of jump table.
1864
+ let start_of_jumptable = sink.get_label();
1865
+ let inst = Inst::lea(Amode::rip_relative(start_of_jumptable), tmp1);
1866
+ inst.emit(&[], sink, info, state);
1867
+
1868
+ // Load value out of the jump table. It's a relative offset to the target block, so it
1869
+ // might be negative; use a sign-extension.
1870
+ let inst = Inst::movsx_rm_r(
1871
+ ExtMode::LQ,
1872
+ RegMem::mem(Amode::imm_reg_reg_shift(
1873
+ 0,
1874
+ Gpr::new(tmp1.to_reg()).unwrap(),
1875
+ Gpr::new(idx).unwrap(),
1876
+ 2,
1877
+ )),
1878
+ tmp2,
1879
+ );
1880
+ inst.emit(&[], sink, info, state);
1881
+
1882
+ // Add base of jump table to jump-table-sourced block offset.
1883
+ let inst = Inst::alu_rmi_r(
1884
+ OperandSize::Size64,
1885
+ AluRmiROpcode::Add,
1886
+ RegMemImm::reg(tmp2.to_reg()),
1887
+ tmp1,
1888
+ );
1889
+ inst.emit(&[], sink, info, state);
1890
+
1891
+ // Branch to computed address.
1892
+ let inst = Inst::jmp_unknown(RegMem::reg(tmp1.to_reg()));
1893
+ inst.emit(&[], sink, info, state);
1894
+
1895
+ // Emit jump table (table of 32-bit offsets).
1896
+ sink.bind_label(start_of_jumptable, state.ctrl_plane_mut());
1897
+ let jt_off = sink.cur_offset();
1898
+ for &target in targets.iter().chain(std::iter::once(default_target)) {
1899
+ let word_off = sink.cur_offset();
1900
+ // off_into_table is an addend here embedded in the label to be later patched at
1901
+ // the end of codegen. The offset is initially relative to this jump table entry;
1902
+ // with the extra addend, it'll be relative to the jump table's start, after
1903
+ // patching.
1904
+ let off_into_table = word_off - jt_off;
1905
+ sink.use_label_at_offset(word_off, target, LabelUse::PCRel32);
1906
+ sink.put4(off_into_table);
1907
+ }
1908
+ }
1909
+
1910
+ Inst::TrapIf { cc, trap_code } => {
1911
+ let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1912
+ one_way_jmp(sink, *cc, trap_label);
1913
+ }
1914
+
1915
+ Inst::TrapIfAnd {
1916
+ cc1,
1917
+ cc2,
1918
+ trap_code,
1919
+ } => {
1920
+ let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1921
+ let else_label = sink.get_label();
1922
+
1923
+ // Jump to the end if the first condition isn't true, and then if
1924
+ // the second condition is true go to the trap.
1925
+ one_way_jmp(sink, cc1.invert(), else_label);
1926
+ one_way_jmp(sink, *cc2, trap_label);
1927
+
1928
+ sink.bind_label(else_label, state.ctrl_plane_mut());
1929
+ }
1930
+
1931
+ Inst::TrapIfOr {
1932
+ cc1,
1933
+ cc2,
1934
+ trap_code,
1935
+ } => {
1936
+ let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1937
+
1938
+ // Emit two jumps to the same trap if either condition code is true.
1939
+ one_way_jmp(sink, *cc1, trap_label);
1940
+ one_way_jmp(sink, *cc2, trap_label);
1941
+ }
1942
+
1943
+ Inst::XmmUnaryRmR { op, src, dst } => {
1944
+ emit(
1945
+ &Inst::XmmUnaryRmRUnaligned {
1946
+ op: *op,
1947
+ src: XmmMem::new(src.clone().into()).unwrap(),
1948
+ dst: *dst,
1949
+ },
1950
+ allocs,
1951
+ sink,
1952
+ info,
1953
+ state,
1954
+ );
1955
+ }
1956
+
1957
+ Inst::XmmUnaryRmRUnaligned {
1958
+ op,
1959
+ src: src_e,
1960
+ dst: reg_g,
1961
+ } => {
1962
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
1963
+ let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
1964
+
1965
+ let rex = RexFlags::clear_w();
1966
+
1967
+ let (prefix, opcode, num_opcodes) = match op {
1968
+ SseOpcode::Cvtdq2pd => (LegacyPrefixes::_F3, 0x0FE6, 2),
1969
+ SseOpcode::Cvtpd2ps => (LegacyPrefixes::_66, 0x0F5A, 2),
1970
+ SseOpcode::Cvtps2pd => (LegacyPrefixes::None, 0x0F5A, 2),
1971
+ SseOpcode::Cvtdq2ps => (LegacyPrefixes::None, 0x0F5B, 2),
1972
+ SseOpcode::Cvttpd2dq => (LegacyPrefixes::_66, 0x0FE6, 2),
1973
+ SseOpcode::Cvttps2dq => (LegacyPrefixes::_F3, 0x0F5B, 2),
1974
+ SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F28, 2),
1975
+ SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F28, 2),
1976
+ SseOpcode::Movdqa => (LegacyPrefixes::_66, 0x0F6F, 2),
1977
+ SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F6F, 2),
1978
+ SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
1979
+ SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F10, 2),
1980
+ SseOpcode::Movups => (LegacyPrefixes::None, 0x0F10, 2),
1981
+ SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F10, 2),
1982
+ SseOpcode::Pabsb => (LegacyPrefixes::_66, 0x0F381C, 3),
1983
+ SseOpcode::Pabsw => (LegacyPrefixes::_66, 0x0F381D, 3),
1984
+ SseOpcode::Pabsd => (LegacyPrefixes::_66, 0x0F381E, 3),
1985
+ SseOpcode::Pmovsxbd => (LegacyPrefixes::_66, 0x0F3821, 3),
1986
+ SseOpcode::Pmovsxbw => (LegacyPrefixes::_66, 0x0F3820, 3),
1987
+ SseOpcode::Pmovsxbq => (LegacyPrefixes::_66, 0x0F3822, 3),
1988
+ SseOpcode::Pmovsxwd => (LegacyPrefixes::_66, 0x0F3823, 3),
1989
+ SseOpcode::Pmovsxwq => (LegacyPrefixes::_66, 0x0F3824, 3),
1990
+ SseOpcode::Pmovsxdq => (LegacyPrefixes::_66, 0x0F3825, 3),
1991
+ SseOpcode::Pmovzxbd => (LegacyPrefixes::_66, 0x0F3831, 3),
1992
+ SseOpcode::Pmovzxbw => (LegacyPrefixes::_66, 0x0F3830, 3),
1993
+ SseOpcode::Pmovzxbq => (LegacyPrefixes::_66, 0x0F3832, 3),
1994
+ SseOpcode::Pmovzxwd => (LegacyPrefixes::_66, 0x0F3833, 3),
1995
+ SseOpcode::Pmovzxwq => (LegacyPrefixes::_66, 0x0F3834, 3),
1996
+ SseOpcode::Pmovzxdq => (LegacyPrefixes::_66, 0x0F3835, 3),
1997
+ SseOpcode::Sqrtps => (LegacyPrefixes::None, 0x0F51, 2),
1998
+ SseOpcode::Sqrtpd => (LegacyPrefixes::_66, 0x0F51, 2),
1999
+ SseOpcode::Movddup => (LegacyPrefixes::_F2, 0x0F12, 2),
2000
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2001
+ };
2002
+
2003
+ match src_e {
2004
+ RegMem::Reg { reg: reg_e } => {
2005
+ emit_std_reg_reg(sink, prefix, opcode, num_opcodes, reg_g, reg_e, rex);
2006
+ }
2007
+ RegMem::Mem { addr } => {
2008
+ let addr = &addr.finalize(state, sink);
2009
+ emit_std_reg_mem(sink, prefix, opcode, num_opcodes, reg_g, addr, rex, 0);
2010
+ }
2011
+ };
2012
+ }
2013
+
2014
+ Inst::XmmUnaryRmRImm { op, src, dst, imm } => {
2015
+ let dst = allocs.next(dst.to_reg().to_reg());
2016
+ let src = src.clone().to_reg_mem().with_allocs(allocs);
2017
+ let rex = RexFlags::clear_w();
2018
+
2019
+ let (prefix, opcode, len) = match op {
2020
+ SseOpcode::Roundps => (LegacyPrefixes::_66, 0x0F3A08, 3),
2021
+ SseOpcode::Roundss => (LegacyPrefixes::_66, 0x0F3A0A, 3),
2022
+ SseOpcode::Roundpd => (LegacyPrefixes::_66, 0x0F3A09, 3),
2023
+ SseOpcode::Roundsd => (LegacyPrefixes::_66, 0x0F3A0B, 3),
2024
+ SseOpcode::Pshufd => (LegacyPrefixes::_66, 0x0F70, 2),
2025
+ SseOpcode::Pshuflw => (LegacyPrefixes::_F2, 0x0F70, 2),
2026
+ SseOpcode::Pshufhw => (LegacyPrefixes::_F3, 0x0F70, 2),
2027
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2028
+ };
2029
+ match src {
2030
+ RegMem::Reg { reg } => {
2031
+ emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
2032
+ }
2033
+ RegMem::Mem { addr } => {
2034
+ let addr = &addr.finalize(state, sink);
2035
+ // N.B.: bytes_at_end == 1, because of the `imm` byte below.
2036
+ emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 1);
2037
+ }
2038
+ }
2039
+ sink.put1(*imm);
2040
+ }
2041
+
2042
+ Inst::XmmUnaryRmREvex { op, src, dst } => {
2043
+ let dst = allocs.next(dst.to_reg().to_reg());
2044
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2045
+ RegMem::Reg { reg } => {
2046
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2047
+ }
2048
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2049
+ };
2050
+
2051
+ let (prefix, map, w, opcode) = match op {
2052
+ Avx512Opcode::Vcvtudq2ps => (LegacyPrefixes::_F2, OpcodeMap::_0F, false, 0x7a),
2053
+ Avx512Opcode::Vpabsq => (LegacyPrefixes::_66, OpcodeMap::_0F38, true, 0x1f),
2054
+ Avx512Opcode::Vpopcntb => (LegacyPrefixes::_66, OpcodeMap::_0F38, false, 0x54),
2055
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2056
+ };
2057
+ EvexInstruction::new()
2058
+ .length(EvexVectorLength::V128)
2059
+ .prefix(prefix)
2060
+ .map(map)
2061
+ .w(w)
2062
+ .opcode(opcode)
2063
+ .tuple_type(op.tuple_type())
2064
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2065
+ .rm(src)
2066
+ .encode(sink);
2067
+ }
2068
+
2069
+ Inst::XmmUnaryRmRImmEvex { op, src, dst, imm } => {
2070
+ let dst = allocs.next(dst.to_reg().to_reg());
2071
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2072
+ RegMem::Reg { reg } => {
2073
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2074
+ }
2075
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2076
+ };
2077
+
2078
+ let (opcode, opcode_ext, w) = match op {
2079
+ Avx512Opcode::VpsraqImm => (0x72, 4, true),
2080
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2081
+ };
2082
+ EvexInstruction::new()
2083
+ .length(EvexVectorLength::V128)
2084
+ .prefix(LegacyPrefixes::_66)
2085
+ .map(OpcodeMap::_0F)
2086
+ .w(w)
2087
+ .opcode(opcode)
2088
+ .reg(opcode_ext)
2089
+ .vvvvv(dst.to_real_reg().unwrap().hw_enc())
2090
+ .tuple_type(op.tuple_type())
2091
+ .rm(src)
2092
+ .imm(*imm)
2093
+ .encode(sink);
2094
+ }
2095
+
2096
+ Inst::XmmRmR {
2097
+ op,
2098
+ src1,
2099
+ src2,
2100
+ dst,
2101
+ } => emit(
2102
+ &Inst::XmmRmRUnaligned {
2103
+ op: *op,
2104
+ dst: *dst,
2105
+ src1: *src1,
2106
+ src2: XmmMem::new(src2.clone().to_reg_mem()).unwrap(),
2107
+ },
2108
+ allocs,
2109
+ sink,
2110
+ info,
2111
+ state,
2112
+ ),
2113
+
2114
+ Inst::XmmRmRUnaligned {
2115
+ op,
2116
+ src1,
2117
+ src2: src_e,
2118
+ dst: reg_g,
2119
+ } => {
2120
+ let src1 = allocs.next(src1.to_reg());
2121
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
2122
+ let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
2123
+ debug_assert_eq!(src1, reg_g);
2124
+
2125
+ let rex = RexFlags::clear_w();
2126
+ let (prefix, opcode, length) = match op {
2127
+ SseOpcode::Addps => (LegacyPrefixes::None, 0x0F58, 2),
2128
+ SseOpcode::Addpd => (LegacyPrefixes::_66, 0x0F58, 2),
2129
+ SseOpcode::Addss => (LegacyPrefixes::_F3, 0x0F58, 2),
2130
+ SseOpcode::Addsd => (LegacyPrefixes::_F2, 0x0F58, 2),
2131
+ SseOpcode::Andps => (LegacyPrefixes::None, 0x0F54, 2),
2132
+ SseOpcode::Andpd => (LegacyPrefixes::_66, 0x0F54, 2),
2133
+ SseOpcode::Andnps => (LegacyPrefixes::None, 0x0F55, 2),
2134
+ SseOpcode::Andnpd => (LegacyPrefixes::_66, 0x0F55, 2),
2135
+ SseOpcode::Divps => (LegacyPrefixes::None, 0x0F5E, 2),
2136
+ SseOpcode::Divpd => (LegacyPrefixes::_66, 0x0F5E, 2),
2137
+ SseOpcode::Divss => (LegacyPrefixes::_F3, 0x0F5E, 2),
2138
+ SseOpcode::Divsd => (LegacyPrefixes::_F2, 0x0F5E, 2),
2139
+ SseOpcode::Maxps => (LegacyPrefixes::None, 0x0F5F, 2),
2140
+ SseOpcode::Maxpd => (LegacyPrefixes::_66, 0x0F5F, 2),
2141
+ SseOpcode::Maxss => (LegacyPrefixes::_F3, 0x0F5F, 2),
2142
+ SseOpcode::Maxsd => (LegacyPrefixes::_F2, 0x0F5F, 2),
2143
+ SseOpcode::Minps => (LegacyPrefixes::None, 0x0F5D, 2),
2144
+ SseOpcode::Minpd => (LegacyPrefixes::_66, 0x0F5D, 2),
2145
+ SseOpcode::Minss => (LegacyPrefixes::_F3, 0x0F5D, 2),
2146
+ SseOpcode::Minsd => (LegacyPrefixes::_F2, 0x0F5D, 2),
2147
+ SseOpcode::Movlhps => (LegacyPrefixes::None, 0x0F16, 2),
2148
+ SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
2149
+ SseOpcode::Mulps => (LegacyPrefixes::None, 0x0F59, 2),
2150
+ SseOpcode::Mulpd => (LegacyPrefixes::_66, 0x0F59, 2),
2151
+ SseOpcode::Mulss => (LegacyPrefixes::_F3, 0x0F59, 2),
2152
+ SseOpcode::Mulsd => (LegacyPrefixes::_F2, 0x0F59, 2),
2153
+ SseOpcode::Orpd => (LegacyPrefixes::_66, 0x0F56, 2),
2154
+ SseOpcode::Orps => (LegacyPrefixes::None, 0x0F56, 2),
2155
+ SseOpcode::Packssdw => (LegacyPrefixes::_66, 0x0F6B, 2),
2156
+ SseOpcode::Packsswb => (LegacyPrefixes::_66, 0x0F63, 2),
2157
+ SseOpcode::Packusdw => (LegacyPrefixes::_66, 0x0F382B, 3),
2158
+ SseOpcode::Packuswb => (LegacyPrefixes::_66, 0x0F67, 2),
2159
+ SseOpcode::Paddb => (LegacyPrefixes::_66, 0x0FFC, 2),
2160
+ SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2),
2161
+ SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2),
2162
+ SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2),
2163
+ SseOpcode::Paddsb => (LegacyPrefixes::_66, 0x0FEC, 2),
2164
+ SseOpcode::Paddsw => (LegacyPrefixes::_66, 0x0FED, 2),
2165
+ SseOpcode::Paddusb => (LegacyPrefixes::_66, 0x0FDC, 2),
2166
+ SseOpcode::Paddusw => (LegacyPrefixes::_66, 0x0FDD, 2),
2167
+ SseOpcode::Pmaddubsw => (LegacyPrefixes::_66, 0x0F3804, 3),
2168
+ SseOpcode::Pand => (LegacyPrefixes::_66, 0x0FDB, 2),
2169
+ SseOpcode::Pandn => (LegacyPrefixes::_66, 0x0FDF, 2),
2170
+ SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),
2171
+ SseOpcode::Pavgw => (LegacyPrefixes::_66, 0x0FE3, 2),
2172
+ SseOpcode::Pcmpeqb => (LegacyPrefixes::_66, 0x0F74, 2),
2173
+ SseOpcode::Pcmpeqw => (LegacyPrefixes::_66, 0x0F75, 2),
2174
+ SseOpcode::Pcmpeqd => (LegacyPrefixes::_66, 0x0F76, 2),
2175
+ SseOpcode::Pcmpeqq => (LegacyPrefixes::_66, 0x0F3829, 3),
2176
+ SseOpcode::Pcmpgtb => (LegacyPrefixes::_66, 0x0F64, 2),
2177
+ SseOpcode::Pcmpgtw => (LegacyPrefixes::_66, 0x0F65, 2),
2178
+ SseOpcode::Pcmpgtd => (LegacyPrefixes::_66, 0x0F66, 2),
2179
+ SseOpcode::Pcmpgtq => (LegacyPrefixes::_66, 0x0F3837, 3),
2180
+ SseOpcode::Pmaddwd => (LegacyPrefixes::_66, 0x0FF5, 2),
2181
+ SseOpcode::Pmaxsb => (LegacyPrefixes::_66, 0x0F383C, 3),
2182
+ SseOpcode::Pmaxsw => (LegacyPrefixes::_66, 0x0FEE, 2),
2183
+ SseOpcode::Pmaxsd => (LegacyPrefixes::_66, 0x0F383D, 3),
2184
+ SseOpcode::Pmaxub => (LegacyPrefixes::_66, 0x0FDE, 2),
2185
+ SseOpcode::Pmaxuw => (LegacyPrefixes::_66, 0x0F383E, 3),
2186
+ SseOpcode::Pmaxud => (LegacyPrefixes::_66, 0x0F383F, 3),
2187
+ SseOpcode::Pminsb => (LegacyPrefixes::_66, 0x0F3838, 3),
2188
+ SseOpcode::Pminsw => (LegacyPrefixes::_66, 0x0FEA, 2),
2189
+ SseOpcode::Pminsd => (LegacyPrefixes::_66, 0x0F3839, 3),
2190
+ SseOpcode::Pminub => (LegacyPrefixes::_66, 0x0FDA, 2),
2191
+ SseOpcode::Pminuw => (LegacyPrefixes::_66, 0x0F383A, 3),
2192
+ SseOpcode::Pminud => (LegacyPrefixes::_66, 0x0F383B, 3),
2193
+ SseOpcode::Pmuldq => (LegacyPrefixes::_66, 0x0F3828, 3),
2194
+ SseOpcode::Pmulhw => (LegacyPrefixes::_66, 0x0FE5, 2),
2195
+ SseOpcode::Pmulhrsw => (LegacyPrefixes::_66, 0x0F380B, 3),
2196
+ SseOpcode::Pmulhuw => (LegacyPrefixes::_66, 0x0FE4, 2),
2197
+ SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
2198
+ SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
2199
+ SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),
2200
+ SseOpcode::Por => (LegacyPrefixes::_66, 0x0FEB, 2),
2201
+ SseOpcode::Pshufb => (LegacyPrefixes::_66, 0x0F3800, 3),
2202
+ SseOpcode::Psubb => (LegacyPrefixes::_66, 0x0FF8, 2),
2203
+ SseOpcode::Psubd => (LegacyPrefixes::_66, 0x0FFA, 2),
2204
+ SseOpcode::Psubq => (LegacyPrefixes::_66, 0x0FFB, 2),
2205
+ SseOpcode::Psubw => (LegacyPrefixes::_66, 0x0FF9, 2),
2206
+ SseOpcode::Psubsb => (LegacyPrefixes::_66, 0x0FE8, 2),
2207
+ SseOpcode::Psubsw => (LegacyPrefixes::_66, 0x0FE9, 2),
2208
+ SseOpcode::Psubusb => (LegacyPrefixes::_66, 0x0FD8, 2),
2209
+ SseOpcode::Psubusw => (LegacyPrefixes::_66, 0x0FD9, 2),
2210
+ SseOpcode::Punpckhbw => (LegacyPrefixes::_66, 0x0F68, 2),
2211
+ SseOpcode::Punpckhwd => (LegacyPrefixes::_66, 0x0F69, 2),
2212
+ SseOpcode::Punpcklbw => (LegacyPrefixes::_66, 0x0F60, 2),
2213
+ SseOpcode::Punpcklwd => (LegacyPrefixes::_66, 0x0F61, 2),
2214
+ SseOpcode::Punpckldq => (LegacyPrefixes::_66, 0x0F62, 2),
2215
+ SseOpcode::Punpcklqdq => (LegacyPrefixes::_66, 0x0F6C, 2),
2216
+ SseOpcode::Punpckhdq => (LegacyPrefixes::_66, 0x0F6A, 2),
2217
+ SseOpcode::Punpckhqdq => (LegacyPrefixes::_66, 0x0F6D, 2),
2218
+ SseOpcode::Pxor => (LegacyPrefixes::_66, 0x0FEF, 2),
2219
+ SseOpcode::Subps => (LegacyPrefixes::None, 0x0F5C, 2),
2220
+ SseOpcode::Subpd => (LegacyPrefixes::_66, 0x0F5C, 2),
2221
+ SseOpcode::Subss => (LegacyPrefixes::_F3, 0x0F5C, 2),
2222
+ SseOpcode::Subsd => (LegacyPrefixes::_F2, 0x0F5C, 2),
2223
+ SseOpcode::Unpcklps => (LegacyPrefixes::None, 0x0F14, 2),
2224
+ SseOpcode::Unpckhps => (LegacyPrefixes::None, 0x0F15, 2),
2225
+ SseOpcode::Xorps => (LegacyPrefixes::None, 0x0F57, 2),
2226
+ SseOpcode::Xorpd => (LegacyPrefixes::_66, 0x0F57, 2),
2227
+ SseOpcode::Phaddw => (LegacyPrefixes::_66, 0x0F3801, 3),
2228
+ SseOpcode::Phaddd => (LegacyPrefixes::_66, 0x0F3802, 3),
2229
+ SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F10, 2),
2230
+ SseOpcode::Cvtss2sd => (LegacyPrefixes::_F3, 0x0F5A, 2),
2231
+ SseOpcode::Cvtsd2ss => (LegacyPrefixes::_F2, 0x0F5A, 2),
2232
+ SseOpcode::Sqrtss => (LegacyPrefixes::_F3, 0x0F51, 2),
2233
+ SseOpcode::Sqrtsd => (LegacyPrefixes::_F2, 0x0F51, 2),
2234
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2235
+ };
2236
+
2237
+ match src_e {
2238
+ RegMem::Reg { reg: reg_e } => {
2239
+ emit_std_reg_reg(sink, prefix, opcode, length, reg_g, reg_e, rex);
2240
+ }
2241
+ RegMem::Mem { addr } => {
2242
+ let addr = &addr.finalize(state, sink);
2243
+ emit_std_reg_mem(sink, prefix, opcode, length, reg_g, addr, rex, 0);
2244
+ }
2245
+ }
2246
+ }
2247
+
2248
+ Inst::XmmRmRBlend {
2249
+ op,
2250
+ src1,
2251
+ src2,
2252
+ dst,
2253
+ mask,
2254
+ } => {
2255
+ let src1 = allocs.next(src1.to_reg());
2256
+ let mask = allocs.next(mask.to_reg());
2257
+ debug_assert_eq!(mask, regs::xmm0());
2258
+ let reg_g = allocs.next(dst.to_reg().to_reg());
2259
+ debug_assert_eq!(src1, reg_g);
2260
+ let src_e = src2.clone().to_reg_mem().with_allocs(allocs);
2261
+
2262
+ let rex = RexFlags::clear_w();
2263
+ let (prefix, opcode, length) = match op {
2264
+ SseOpcode::Blendvps => (LegacyPrefixes::_66, 0x0F3814, 3),
2265
+ SseOpcode::Blendvpd => (LegacyPrefixes::_66, 0x0F3815, 3),
2266
+ SseOpcode::Pblendvb => (LegacyPrefixes::_66, 0x0F3810, 3),
2267
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2268
+ };
2269
+
2270
+ match src_e {
2271
+ RegMem::Reg { reg: reg_e } => {
2272
+ emit_std_reg_reg(sink, prefix, opcode, length, reg_g, reg_e, rex);
2273
+ }
2274
+ RegMem::Mem { addr } => {
2275
+ let addr = &addr.finalize(state, sink);
2276
+ emit_std_reg_mem(sink, prefix, opcode, length, reg_g, addr, rex, 0);
2277
+ }
2278
+ }
2279
+ }
2280
+
2281
+ Inst::XmmRmiRVex {
2282
+ op,
2283
+ src1,
2284
+ src2,
2285
+ dst,
2286
+ } => {
2287
+ use LegacyPrefixes as LP;
2288
+ use OpcodeMap as OM;
2289
+
2290
+ let dst = allocs.next(dst.to_reg().to_reg());
2291
+ let src1 = allocs.next(src1.to_reg());
2292
+ let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
2293
+
2294
+ // When the opcode is commutative, src1 is xmm{0..7}, and src2 is
2295
+ // xmm{8..15}, then we can swap the operands to save one byte on the
2296
+ // instruction's encoding.
2297
+ let (src1, src2) = match (src1, src2) {
2298
+ (src1, RegMemImm::Reg { reg: src2 })
2299
+ if op.is_commutative()
2300
+ && src1.to_real_reg().unwrap().hw_enc() < 8
2301
+ && src2.to_real_reg().unwrap().hw_enc() >= 8 =>
2302
+ {
2303
+ (src2, RegMemImm::Reg { reg: src1 })
2304
+ }
2305
+ (src1, src2) => (src1, src2),
2306
+ };
2307
+
2308
+ let src2 = match src2 {
2309
+ // For opcodes where one of the operands is an immediate the
2310
+ // encoding is a bit different, notably the usage of
2311
+ // `opcode_ext`, so handle that specially here.
2312
+ RegMemImm::Imm { simm32 } => {
2313
+ let (opcode, opcode_ext, prefix) = match op {
2314
+ AvxOpcode::Vpsrlw => (0x71, 2, LegacyPrefixes::_66),
2315
+ AvxOpcode::Vpsrld => (0x72, 2, LegacyPrefixes::_66),
2316
+ AvxOpcode::Vpsrlq => (0x73, 2, LegacyPrefixes::_66),
2317
+ AvxOpcode::Vpsllw => (0x71, 6, LegacyPrefixes::_66),
2318
+ AvxOpcode::Vpslld => (0x72, 6, LegacyPrefixes::_66),
2319
+ AvxOpcode::Vpsllq => (0x73, 6, LegacyPrefixes::_66),
2320
+ AvxOpcode::Vpsraw => (0x71, 4, LegacyPrefixes::_66),
2321
+ AvxOpcode::Vpsrad => (0x72, 4, LegacyPrefixes::_66),
2322
+ _ => panic!("unexpected rmi_r_vex opcode with immediate {op:?}"),
2323
+ };
2324
+ VexInstruction::new()
2325
+ .length(VexVectorLength::V128)
2326
+ .prefix(prefix)
2327
+ .map(OpcodeMap::_0F)
2328
+ .opcode(opcode)
2329
+ .opcode_ext(opcode_ext)
2330
+ .vvvv(dst.to_real_reg().unwrap().hw_enc())
2331
+ .prefix(LegacyPrefixes::_66)
2332
+ .rm(src1.to_real_reg().unwrap().hw_enc())
2333
+ .imm(simm32.try_into().unwrap())
2334
+ .encode(sink);
2335
+ return;
2336
+ }
2337
+ RegMemImm::Reg { reg } => {
2338
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2339
+ }
2340
+ RegMemImm::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2341
+ };
2342
+
2343
+ let (prefix, map, opcode) = match op {
2344
+ AvxOpcode::Vminps => (LP::None, OM::_0F, 0x5D),
2345
+ AvxOpcode::Vminpd => (LP::_66, OM::_0F, 0x5D),
2346
+ AvxOpcode::Vmaxps => (LP::None, OM::_0F, 0x5F),
2347
+ AvxOpcode::Vmaxpd => (LP::_66, OM::_0F, 0x5F),
2348
+ AvxOpcode::Vandnps => (LP::None, OM::_0F, 0x55),
2349
+ AvxOpcode::Vandnpd => (LP::_66, OM::_0F, 0x55),
2350
+ AvxOpcode::Vpandn => (LP::_66, OM::_0F, 0xDF),
2351
+ AvxOpcode::Vpsrlw => (LP::_66, OM::_0F, 0xD1),
2352
+ AvxOpcode::Vpsrld => (LP::_66, OM::_0F, 0xD2),
2353
+ AvxOpcode::Vpsrlq => (LP::_66, OM::_0F, 0xD3),
2354
+ AvxOpcode::Vpaddb => (LP::_66, OM::_0F, 0xFC),
2355
+ AvxOpcode::Vpaddw => (LP::_66, OM::_0F, 0xFD),
2356
+ AvxOpcode::Vpaddd => (LP::_66, OM::_0F, 0xFE),
2357
+ AvxOpcode::Vpaddq => (LP::_66, OM::_0F, 0xD4),
2358
+ AvxOpcode::Vpaddsb => (LP::_66, OM::_0F, 0xEC),
2359
+ AvxOpcode::Vpaddsw => (LP::_66, OM::_0F, 0xED),
2360
+ AvxOpcode::Vpaddusb => (LP::_66, OM::_0F, 0xDC),
2361
+ AvxOpcode::Vpaddusw => (LP::_66, OM::_0F, 0xDD),
2362
+ AvxOpcode::Vpsubb => (LP::_66, OM::_0F, 0xF8),
2363
+ AvxOpcode::Vpsubw => (LP::_66, OM::_0F, 0xF9),
2364
+ AvxOpcode::Vpsubd => (LP::_66, OM::_0F, 0xFA),
2365
+ AvxOpcode::Vpsubq => (LP::_66, OM::_0F, 0xFB),
2366
+ AvxOpcode::Vpsubsb => (LP::_66, OM::_0F, 0xE8),
2367
+ AvxOpcode::Vpsubsw => (LP::_66, OM::_0F, 0xE9),
2368
+ AvxOpcode::Vpsubusb => (LP::_66, OM::_0F, 0xD8),
2369
+ AvxOpcode::Vpsubusw => (LP::_66, OM::_0F, 0xD9),
2370
+ AvxOpcode::Vpavgb => (LP::_66, OM::_0F, 0xE0),
2371
+ AvxOpcode::Vpavgw => (LP::_66, OM::_0F, 0xE3),
2372
+ AvxOpcode::Vpand => (LP::_66, OM::_0F, 0xDB),
2373
+ AvxOpcode::Vandps => (LP::None, OM::_0F, 0x54),
2374
+ AvxOpcode::Vandpd => (LP::_66, OM::_0F, 0x54),
2375
+ AvxOpcode::Vpor => (LP::_66, OM::_0F, 0xEB),
2376
+ AvxOpcode::Vorps => (LP::None, OM::_0F, 0x56),
2377
+ AvxOpcode::Vorpd => (LP::_66, OM::_0F, 0x56),
2378
+ AvxOpcode::Vpxor => (LP::_66, OM::_0F, 0xEF),
2379
+ AvxOpcode::Vxorps => (LP::None, OM::_0F, 0x57),
2380
+ AvxOpcode::Vxorpd => (LP::_66, OM::_0F, 0x57),
2381
+ AvxOpcode::Vpmullw => (LP::_66, OM::_0F, 0xD5),
2382
+ AvxOpcode::Vpmulld => (LP::_66, OM::_0F38, 0x40),
2383
+ AvxOpcode::Vpmulhw => (LP::_66, OM::_0F, 0xE5),
2384
+ AvxOpcode::Vpmulhrsw => (LP::_66, OM::_0F38, 0x0B),
2385
+ AvxOpcode::Vpmulhuw => (LP::_66, OM::_0F, 0xE4),
2386
+ AvxOpcode::Vpmuldq => (LP::_66, OM::_0F38, 0x28),
2387
+ AvxOpcode::Vpmuludq => (LP::_66, OM::_0F, 0xF4),
2388
+ AvxOpcode::Vpunpckhwd => (LP::_66, OM::_0F, 0x69),
2389
+ AvxOpcode::Vpunpcklwd => (LP::_66, OM::_0F, 0x61),
2390
+ AvxOpcode::Vunpcklps => (LP::None, OM::_0F, 0x14),
2391
+ AvxOpcode::Vunpckhps => (LP::None, OM::_0F, 0x15),
2392
+ AvxOpcode::Vaddps => (LP::None, OM::_0F, 0x58),
2393
+ AvxOpcode::Vaddpd => (LP::_66, OM::_0F, 0x58),
2394
+ AvxOpcode::Vsubps => (LP::None, OM::_0F, 0x5C),
2395
+ AvxOpcode::Vsubpd => (LP::_66, OM::_0F, 0x5C),
2396
+ AvxOpcode::Vmulps => (LP::None, OM::_0F, 0x59),
2397
+ AvxOpcode::Vmulpd => (LP::_66, OM::_0F, 0x59),
2398
+ AvxOpcode::Vdivps => (LP::None, OM::_0F, 0x5E),
2399
+ AvxOpcode::Vdivpd => (LP::_66, OM::_0F, 0x5E),
2400
+ AvxOpcode::Vpcmpeqb => (LP::_66, OM::_0F, 0x74),
2401
+ AvxOpcode::Vpcmpeqw => (LP::_66, OM::_0F, 0x75),
2402
+ AvxOpcode::Vpcmpeqd => (LP::_66, OM::_0F, 0x76),
2403
+ AvxOpcode::Vpcmpeqq => (LP::_66, OM::_0F38, 0x29),
2404
+ AvxOpcode::Vpcmpgtb => (LP::_66, OM::_0F, 0x64),
2405
+ AvxOpcode::Vpcmpgtw => (LP::_66, OM::_0F, 0x65),
2406
+ AvxOpcode::Vpcmpgtd => (LP::_66, OM::_0F, 0x66),
2407
+ AvxOpcode::Vpcmpgtq => (LP::_66, OM::_0F38, 0x37),
2408
+ AvxOpcode::Vmovlhps => (LP::None, OM::_0F, 0x16),
2409
+ AvxOpcode::Vpminsb => (LP::_66, OM::_0F38, 0x38),
2410
+ AvxOpcode::Vpminsw => (LP::_66, OM::_0F, 0xEA),
2411
+ AvxOpcode::Vpminsd => (LP::_66, OM::_0F38, 0x39),
2412
+ AvxOpcode::Vpmaxsb => (LP::_66, OM::_0F38, 0x3C),
2413
+ AvxOpcode::Vpmaxsw => (LP::_66, OM::_0F, 0xEE),
2414
+ AvxOpcode::Vpmaxsd => (LP::_66, OM::_0F38, 0x3D),
2415
+ AvxOpcode::Vpminub => (LP::_66, OM::_0F, 0xDA),
2416
+ AvxOpcode::Vpminuw => (LP::_66, OM::_0F38, 0x3A),
2417
+ AvxOpcode::Vpminud => (LP::_66, OM::_0F38, 0x3B),
2418
+ AvxOpcode::Vpmaxub => (LP::_66, OM::_0F, 0xDE),
2419
+ AvxOpcode::Vpmaxuw => (LP::_66, OM::_0F38, 0x3E),
2420
+ AvxOpcode::Vpmaxud => (LP::_66, OM::_0F38, 0x3F),
2421
+ AvxOpcode::Vpunpcklbw => (LP::_66, OM::_0F, 0x60),
2422
+ AvxOpcode::Vpunpckhbw => (LP::_66, OM::_0F, 0x68),
2423
+ AvxOpcode::Vpacksswb => (LP::_66, OM::_0F, 0x63),
2424
+ AvxOpcode::Vpackssdw => (LP::_66, OM::_0F, 0x6B),
2425
+ AvxOpcode::Vpackuswb => (LP::_66, OM::_0F, 0x67),
2426
+ AvxOpcode::Vpackusdw => (LP::_66, OM::_0F38, 0x2B),
2427
+ AvxOpcode::Vpmaddwd => (LP::_66, OM::_0F, 0xF5),
2428
+ AvxOpcode::Vpmaddubsw => (LP::_66, OM::_0F38, 0x04),
2429
+ AvxOpcode::Vpshufb => (LP::_66, OM::_0F38, 0x00),
2430
+ AvxOpcode::Vpsllw => (LP::_66, OM::_0F, 0xF1),
2431
+ AvxOpcode::Vpslld => (LP::_66, OM::_0F, 0xF2),
2432
+ AvxOpcode::Vpsllq => (LP::_66, OM::_0F, 0xF3),
2433
+ AvxOpcode::Vpsraw => (LP::_66, OM::_0F, 0xE1),
2434
+ AvxOpcode::Vpsrad => (LP::_66, OM::_0F, 0xE2),
2435
+ AvxOpcode::Vaddss => (LP::_F3, OM::_0F, 0x58),
2436
+ AvxOpcode::Vaddsd => (LP::_F2, OM::_0F, 0x58),
2437
+ AvxOpcode::Vmulss => (LP::_F3, OM::_0F, 0x59),
2438
+ AvxOpcode::Vmulsd => (LP::_F2, OM::_0F, 0x59),
2439
+ AvxOpcode::Vsubss => (LP::_F3, OM::_0F, 0x5C),
2440
+ AvxOpcode::Vsubsd => (LP::_F2, OM::_0F, 0x5C),
2441
+ AvxOpcode::Vdivss => (LP::_F3, OM::_0F, 0x5E),
2442
+ AvxOpcode::Vdivsd => (LP::_F2, OM::_0F, 0x5E),
2443
+ AvxOpcode::Vminss => (LP::_F3, OM::_0F, 0x5D),
2444
+ AvxOpcode::Vminsd => (LP::_F2, OM::_0F, 0x5D),
2445
+ AvxOpcode::Vmaxss => (LP::_F3, OM::_0F, 0x5F),
2446
+ AvxOpcode::Vmaxsd => (LP::_F2, OM::_0F, 0x5F),
2447
+ AvxOpcode::Vphaddw => (LP::_66, OM::_0F38, 0x01),
2448
+ AvxOpcode::Vphaddd => (LP::_66, OM::_0F38, 0x02),
2449
+ AvxOpcode::Vpunpckldq => (LP::_66, OM::_0F, 0x62),
2450
+ AvxOpcode::Vpunpckhdq => (LP::_66, OM::_0F, 0x6A),
2451
+ AvxOpcode::Vpunpcklqdq => (LP::_66, OM::_0F, 0x6C),
2452
+ AvxOpcode::Vpunpckhqdq => (LP::_66, OM::_0F, 0x6D),
2453
+ AvxOpcode::Vmovsd => (LP::_F2, OM::_0F, 0x10),
2454
+ AvxOpcode::Vmovss => (LP::_F3, OM::_0F, 0x10),
2455
+ AvxOpcode::Vcvtss2sd => (LP::_F3, OM::_0F, 0x5A),
2456
+ AvxOpcode::Vcvtsd2ss => (LP::_F2, OM::_0F, 0x5A),
2457
+ AvxOpcode::Vsqrtss => (LP::_F3, OM::_0F, 0x51),
2458
+ AvxOpcode::Vsqrtsd => (LP::_F2, OM::_0F, 0x51),
2459
+ _ => panic!("unexpected rmir vex opcode {op:?}"),
2460
+ };
2461
+ VexInstruction::new()
2462
+ .length(VexVectorLength::V128)
2463
+ .prefix(prefix)
2464
+ .map(map)
2465
+ .opcode(opcode)
2466
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2467
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2468
+ .rm(src2)
2469
+ .encode(sink);
2470
+ }
2471
+
2472
+ Inst::XmmRmRImmVex {
2473
+ op,
2474
+ src1,
2475
+ src2,
2476
+ dst,
2477
+ imm,
2478
+ } => {
2479
+ let dst = allocs.next(dst.to_reg().to_reg());
2480
+ let src1 = allocs.next(src1.to_reg());
2481
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2482
+ RegMem::Reg { reg } => {
2483
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2484
+ }
2485
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2486
+ };
2487
+
2488
+ let (w, prefix, map, opcode) = match op {
2489
+ AvxOpcode::Vcmpps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC2),
2490
+ AvxOpcode::Vcmppd => (false, LegacyPrefixes::_66, OpcodeMap::_0F, 0xC2),
2491
+ AvxOpcode::Vpalignr => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0F),
2492
+ AvxOpcode::Vinsertps => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x21),
2493
+ AvxOpcode::Vshufps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC6),
2494
+ AvxOpcode::Vpblendw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0E),
2495
+ _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2496
+ };
2497
+
2498
+ VexInstruction::new()
2499
+ .length(VexVectorLength::V128)
2500
+ .prefix(prefix)
2501
+ .map(map)
2502
+ .w(w)
2503
+ .opcode(opcode)
2504
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2505
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2506
+ .rm(src2)
2507
+ .imm(*imm)
2508
+ .encode(sink);
2509
+ }
2510
+
2511
+ Inst::XmmVexPinsr {
2512
+ op,
2513
+ src1,
2514
+ src2,
2515
+ dst,
2516
+ imm,
2517
+ } => {
2518
+ let dst = allocs.next(dst.to_reg().to_reg());
2519
+ let src1 = allocs.next(src1.to_reg());
2520
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2521
+ RegMem::Reg { reg } => {
2522
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2523
+ }
2524
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2525
+ };
2526
+
2527
+ let (w, map, opcode) = match op {
2528
+ AvxOpcode::Vpinsrb => (false, OpcodeMap::_0F3A, 0x20),
2529
+ AvxOpcode::Vpinsrw => (false, OpcodeMap::_0F, 0xC4),
2530
+ AvxOpcode::Vpinsrd => (false, OpcodeMap::_0F3A, 0x22),
2531
+ AvxOpcode::Vpinsrq => (true, OpcodeMap::_0F3A, 0x22),
2532
+ _ => panic!("unexpected vex_pinsr opcode {op:?}"),
2533
+ };
2534
+
2535
+ VexInstruction::new()
2536
+ .length(VexVectorLength::V128)
2537
+ .prefix(LegacyPrefixes::_66)
2538
+ .map(map)
2539
+ .w(w)
2540
+ .opcode(opcode)
2541
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2542
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2543
+ .rm(src2)
2544
+ .imm(*imm)
2545
+ .encode(sink);
2546
+ }
2547
+
2548
+ Inst::XmmRmRVex3 {
2549
+ op,
2550
+ src1,
2551
+ src2,
2552
+ src3,
2553
+ dst,
2554
+ } => {
2555
+ let src1 = allocs.next(src1.to_reg());
2556
+ let dst = allocs.next(dst.to_reg().to_reg());
2557
+ debug_assert_eq!(src1, dst);
2558
+ let src2 = allocs.next(src2.to_reg());
2559
+ let src3 = match src3.clone().to_reg_mem().with_allocs(allocs) {
2560
+ RegMem::Reg { reg } => {
2561
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2562
+ }
2563
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2564
+ };
2565
+
2566
+ let (w, map, opcode) = match op {
2567
+ AvxOpcode::Vfmadd132ss => (false, OpcodeMap::_0F38, 0x99),
2568
+ AvxOpcode::Vfmadd213ss => (false, OpcodeMap::_0F38, 0xA9),
2569
+ AvxOpcode::Vfnmadd132ss => (false, OpcodeMap::_0F38, 0x9D),
2570
+ AvxOpcode::Vfnmadd213ss => (false, OpcodeMap::_0F38, 0xAD),
2571
+ AvxOpcode::Vfmadd132sd => (true, OpcodeMap::_0F38, 0x99),
2572
+ AvxOpcode::Vfmadd213sd => (true, OpcodeMap::_0F38, 0xA9),
2573
+ AvxOpcode::Vfnmadd132sd => (true, OpcodeMap::_0F38, 0x9D),
2574
+ AvxOpcode::Vfnmadd213sd => (true, OpcodeMap::_0F38, 0xAD),
2575
+ AvxOpcode::Vfmadd132ps => (false, OpcodeMap::_0F38, 0x98),
2576
+ AvxOpcode::Vfmadd213ps => (false, OpcodeMap::_0F38, 0xA8),
2577
+ AvxOpcode::Vfnmadd132ps => (false, OpcodeMap::_0F38, 0x9C),
2578
+ AvxOpcode::Vfnmadd213ps => (false, OpcodeMap::_0F38, 0xAC),
2579
+ AvxOpcode::Vfmadd132pd => (true, OpcodeMap::_0F38, 0x98),
2580
+ AvxOpcode::Vfmadd213pd => (true, OpcodeMap::_0F38, 0xA8),
2581
+ AvxOpcode::Vfnmadd132pd => (true, OpcodeMap::_0F38, 0x9C),
2582
+ AvxOpcode::Vfnmadd213pd => (true, OpcodeMap::_0F38, 0xAC),
2583
+ AvxOpcode::Vblendvps => (false, OpcodeMap::_0F3A, 0x4A),
2584
+ AvxOpcode::Vblendvpd => (false, OpcodeMap::_0F3A, 0x4B),
2585
+ AvxOpcode::Vpblendvb => (false, OpcodeMap::_0F3A, 0x4C),
2586
+ _ => unreachable!(),
2587
+ };
2588
+
2589
+ VexInstruction::new()
2590
+ .length(VexVectorLength::V128)
2591
+ .prefix(LegacyPrefixes::_66)
2592
+ .map(map)
2593
+ .w(w)
2594
+ .opcode(opcode)
2595
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2596
+ .rm(src3)
2597
+ .vvvv(src2.to_real_reg().unwrap().hw_enc())
2598
+ .encode(sink);
2599
+ }
2600
+
2601
+ Inst::XmmRmRBlendVex {
2602
+ op,
2603
+ src1,
2604
+ src2,
2605
+ mask,
2606
+ dst,
2607
+ } => {
2608
+ let dst = allocs.next(dst.to_reg().to_reg());
2609
+ let src1 = allocs.next(src1.to_reg());
2610
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2611
+ RegMem::Reg { reg } => {
2612
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2613
+ }
2614
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2615
+ };
2616
+ let mask = allocs.next(mask.to_reg());
2617
+
2618
+ let opcode = match op {
2619
+ AvxOpcode::Vblendvps => 0x4A,
2620
+ AvxOpcode::Vblendvpd => 0x4B,
2621
+ AvxOpcode::Vpblendvb => 0x4C,
2622
+ _ => unreachable!(),
2623
+ };
2624
+
2625
+ VexInstruction::new()
2626
+ .length(VexVectorLength::V128)
2627
+ .prefix(LegacyPrefixes::_66)
2628
+ .map(OpcodeMap::_0F3A)
2629
+ .opcode(opcode)
2630
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2631
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2632
+ .rm(src2)
2633
+ .imm(mask.to_real_reg().unwrap().hw_enc() << 4)
2634
+ .encode(sink);
2635
+ }
2636
+
2637
+ Inst::XmmUnaryRmRVex { op, src, dst } => {
2638
+ let dst = allocs.next(dst.to_reg().to_reg());
2639
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2640
+ RegMem::Reg { reg } => {
2641
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2642
+ }
2643
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2644
+ };
2645
+
2646
+ let (prefix, map, opcode) = match op {
2647
+ AvxOpcode::Vpmovsxbw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x20),
2648
+ AvxOpcode::Vpmovzxbw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x30),
2649
+ AvxOpcode::Vpmovsxwd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x23),
2650
+ AvxOpcode::Vpmovzxwd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x33),
2651
+ AvxOpcode::Vpmovsxdq => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x25),
2652
+ AvxOpcode::Vpmovzxdq => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x35),
2653
+ AvxOpcode::Vpabsb => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1C),
2654
+ AvxOpcode::Vpabsw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1D),
2655
+ AvxOpcode::Vpabsd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1E),
2656
+ AvxOpcode::Vsqrtps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x51),
2657
+ AvxOpcode::Vsqrtpd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x51),
2658
+ AvxOpcode::Vcvtdq2pd => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0xE6),
2659
+ AvxOpcode::Vcvtdq2ps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x5B),
2660
+ AvxOpcode::Vcvtpd2ps => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x5A),
2661
+ AvxOpcode::Vcvtps2pd => (LegacyPrefixes::None, OpcodeMap::_0F, 0x5A),
2662
+ AvxOpcode::Vcvttpd2dq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0xE6),
2663
+ AvxOpcode::Vcvttps2dq => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x5B),
2664
+ AvxOpcode::Vmovdqu => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x6F),
2665
+ AvxOpcode::Vmovups => (LegacyPrefixes::None, OpcodeMap::_0F, 0x10),
2666
+ AvxOpcode::Vmovupd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x10),
2667
+
2668
+ // Note that for `vmov{s,d}` the `inst.isle` rules should
2669
+ // statically ensure that only `Amode` operands are used here.
2670
+ // Otherwise the other encodings of `vmovss` are more like
2671
+ // 2-operand instructions which this unary encoding does not
2672
+ // have.
2673
+ AvxOpcode::Vmovss => match &src {
2674
+ RegisterOrAmode::Amode(_) => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x10),
2675
+ _ => unreachable!(),
2676
+ },
2677
+ AvxOpcode::Vmovsd => match &src {
2678
+ RegisterOrAmode::Amode(_) => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x10),
2679
+ _ => unreachable!(),
2680
+ },
2681
+
2682
+ AvxOpcode::Vpbroadcastb => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x78),
2683
+ AvxOpcode::Vpbroadcastw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x79),
2684
+ AvxOpcode::Vpbroadcastd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x58),
2685
+ AvxOpcode::Vbroadcastss => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x18),
2686
+ AvxOpcode::Vmovddup => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x12),
2687
+
2688
+ _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2689
+ };
2690
+
2691
+ VexInstruction::new()
2692
+ .length(VexVectorLength::V128)
2693
+ .prefix(prefix)
2694
+ .map(map)
2695
+ .opcode(opcode)
2696
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2697
+ .rm(src)
2698
+ .encode(sink);
2699
+ }
2700
+
2701
+ Inst::XmmUnaryRmRImmVex { op, src, dst, imm } => {
2702
+ let dst = allocs.next(dst.to_reg().to_reg());
2703
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2704
+ RegMem::Reg { reg } => {
2705
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2706
+ }
2707
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2708
+ };
2709
+
2710
+ let (prefix, map, opcode) = match op {
2711
+ AvxOpcode::Vroundps => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x08),
2712
+ AvxOpcode::Vroundpd => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x09),
2713
+ AvxOpcode::Vpshuflw => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x70),
2714
+ AvxOpcode::Vpshufhw => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x70),
2715
+ AvxOpcode::Vpshufd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x70),
2716
+ AvxOpcode::Vroundss => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0A),
2717
+ AvxOpcode::Vroundsd => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0B),
2718
+ _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2719
+ };
2720
+
2721
+ let vex = VexInstruction::new()
2722
+ .length(VexVectorLength::V128)
2723
+ .prefix(prefix)
2724
+ .map(map)
2725
+ .opcode(opcode)
2726
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2727
+ .rm(src)
2728
+ .imm(*imm);
2729
+
2730
+ // See comments in similar block above in `XmmUnaryRmRVex` for what
2731
+ // this is doing.
2732
+ let vex = match op {
2733
+ AvxOpcode::Vroundss | AvxOpcode::Vroundsd => {
2734
+ vex.vvvv(dst.to_real_reg().unwrap().hw_enc())
2735
+ }
2736
+ _ => vex,
2737
+ };
2738
+ vex.encode(sink);
2739
+ }
2740
+
2741
+ Inst::XmmMovRMVex { op, src, dst } => {
2742
+ let src = allocs.next(src.to_reg());
2743
+ let dst = dst.with_allocs(allocs).finalize(state, sink);
2744
+
2745
+ let (prefix, map, opcode) = match op {
2746
+ AvxOpcode::Vmovdqu => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x7F),
2747
+ AvxOpcode::Vmovss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x11),
2748
+ AvxOpcode::Vmovsd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x11),
2749
+ AvxOpcode::Vmovups => (LegacyPrefixes::None, OpcodeMap::_0F, 0x11),
2750
+ AvxOpcode::Vmovupd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x11),
2751
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2752
+ };
2753
+ VexInstruction::new()
2754
+ .length(VexVectorLength::V128)
2755
+ .prefix(prefix)
2756
+ .map(map)
2757
+ .opcode(opcode)
2758
+ .rm(dst)
2759
+ .reg(src.to_real_reg().unwrap().hw_enc())
2760
+ .encode(sink);
2761
+ }
2762
+
2763
+ Inst::XmmMovRMImmVex { op, src, dst, imm } => {
2764
+ let src = allocs.next(src.to_reg());
2765
+ let dst = dst.with_allocs(allocs).finalize(state, sink);
2766
+
2767
+ let (w, prefix, map, opcode) = match op {
2768
+ AvxOpcode::Vpextrb => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x14),
2769
+ AvxOpcode::Vpextrw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x15),
2770
+ AvxOpcode::Vpextrd => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2771
+ AvxOpcode::Vpextrq => (true, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2772
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2773
+ };
2774
+ VexInstruction::new()
2775
+ .length(VexVectorLength::V128)
2776
+ .w(w)
2777
+ .prefix(prefix)
2778
+ .map(map)
2779
+ .opcode(opcode)
2780
+ .rm(dst)
2781
+ .reg(src.to_real_reg().unwrap().hw_enc())
2782
+ .imm(*imm)
2783
+ .encode(sink);
2784
+ }
2785
+
2786
+ Inst::XmmToGprImmVex { op, src, dst, imm } => {
2787
+ let src = allocs.next(src.to_reg());
2788
+ let dst = allocs.next(dst.to_reg().to_reg());
2789
+
2790
+ let (w, prefix, map, opcode) = match op {
2791
+ AvxOpcode::Vpextrb => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x14),
2792
+ AvxOpcode::Vpextrw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x15),
2793
+ AvxOpcode::Vpextrd => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2794
+ AvxOpcode::Vpextrq => (true, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2795
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2796
+ };
2797
+ VexInstruction::new()
2798
+ .length(VexVectorLength::V128)
2799
+ .w(w)
2800
+ .prefix(prefix)
2801
+ .map(map)
2802
+ .opcode(opcode)
2803
+ .rm(dst.to_real_reg().unwrap().hw_enc())
2804
+ .reg(src.to_real_reg().unwrap().hw_enc())
2805
+ .imm(*imm)
2806
+ .encode(sink);
2807
+ }
2808
+
2809
+ Inst::XmmToGprVex {
2810
+ op,
2811
+ src,
2812
+ dst,
2813
+ dst_size,
2814
+ } => {
2815
+ let src = allocs.next(src.to_reg());
2816
+ let dst = allocs.next(dst.to_reg().to_reg());
2817
+
2818
+ let (prefix, map, opcode) = match op {
2819
+ // vmovd/vmovq are differentiated by `w`
2820
+ AvxOpcode::Vmovd | AvxOpcode::Vmovq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x7E),
2821
+ AvxOpcode::Vmovmskps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x50),
2822
+ AvxOpcode::Vmovmskpd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x50),
2823
+ AvxOpcode::Vpmovmskb => (LegacyPrefixes::_66, OpcodeMap::_0F, 0xD7),
2824
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2825
+ };
2826
+ let w = match dst_size {
2827
+ OperandSize::Size64 => true,
2828
+ _ => false,
2829
+ };
2830
+ let mut vex = VexInstruction::new()
2831
+ .length(VexVectorLength::V128)
2832
+ .w(w)
2833
+ .prefix(prefix)
2834
+ .map(map)
2835
+ .opcode(opcode);
2836
+ vex = match op {
2837
+ // The `vmovq/vmovd` reverse the order of the destination/source
2838
+ // relative to other opcodes using this shape of instruction.
2839
+ AvxOpcode::Vmovd | AvxOpcode::Vmovq => vex
2840
+ .rm(dst.to_real_reg().unwrap().hw_enc())
2841
+ .reg(src.to_real_reg().unwrap().hw_enc()),
2842
+ _ => vex
2843
+ .rm(src.to_real_reg().unwrap().hw_enc())
2844
+ .reg(dst.to_real_reg().unwrap().hw_enc()),
2845
+ };
2846
+ vex.encode(sink);
2847
+ }
2848
+
2849
+ Inst::GprToXmmVex {
2850
+ op,
2851
+ src,
2852
+ dst,
2853
+ src_size,
2854
+ } => {
2855
+ let dst = allocs.next(dst.to_reg().to_reg());
2856
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2857
+ RegMem::Reg { reg } => {
2858
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2859
+ }
2860
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2861
+ };
2862
+
2863
+ let (prefix, map, opcode) = match op {
2864
+ // vmovd/vmovq are differentiated by `w`
2865
+ AvxOpcode::Vmovd | AvxOpcode::Vmovq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x6E),
2866
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2867
+ };
2868
+ let w = match src_size {
2869
+ OperandSize::Size64 => true,
2870
+ _ => false,
2871
+ };
2872
+ VexInstruction::new()
2873
+ .length(VexVectorLength::V128)
2874
+ .w(w)
2875
+ .prefix(prefix)
2876
+ .map(map)
2877
+ .opcode(opcode)
2878
+ .rm(src)
2879
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2880
+ .encode(sink);
2881
+ }
2882
+
2883
+ Inst::XmmRmREvex {
2884
+ op,
2885
+ src1,
2886
+ src2,
2887
+ dst,
2888
+ }
2889
+ | Inst::XmmRmREvex3 {
2890
+ op,
2891
+ src1: _, // `dst` reuses `src1`.
2892
+ src2: src1,
2893
+ src3: src2,
2894
+ dst,
2895
+ } => {
2896
+ let reused_src = match inst {
2897
+ Inst::XmmRmREvex3 { src1, .. } => Some(allocs.next(src1.to_reg())),
2898
+ _ => None,
2899
+ };
2900
+ let src1 = allocs.next(src1.to_reg());
2901
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2902
+ RegMem::Reg { reg } => {
2903
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2904
+ }
2905
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2906
+ };
2907
+ let dst = allocs.next(dst.to_reg().to_reg());
2908
+ if let Some(src1) = reused_src {
2909
+ debug_assert_eq!(src1, dst);
2910
+ }
2911
+
2912
+ let (w, opcode, map) = match op {
2913
+ Avx512Opcode::Vpermi2b => (false, 0x75, OpcodeMap::_0F38),
2914
+ Avx512Opcode::Vpmullq => (true, 0x40, OpcodeMap::_0F38),
2915
+ Avx512Opcode::Vpsraq => (true, 0xE2, OpcodeMap::_0F),
2916
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2917
+ };
2918
+ EvexInstruction::new()
2919
+ .length(EvexVectorLength::V128)
2920
+ .prefix(LegacyPrefixes::_66)
2921
+ .map(map)
2922
+ .w(w)
2923
+ .opcode(opcode)
2924
+ .tuple_type(op.tuple_type())
2925
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2926
+ .vvvvv(src1.to_real_reg().unwrap().hw_enc())
2927
+ .rm(src2)
2928
+ .encode(sink);
2929
+ }
2930
+
2931
+ Inst::XmmMinMaxSeq {
2932
+ size,
2933
+ is_min,
2934
+ lhs,
2935
+ rhs,
2936
+ dst,
2937
+ } => {
2938
+ let rhs = allocs.next(rhs.to_reg());
2939
+ let lhs = allocs.next(lhs.to_reg());
2940
+ let dst = allocs.next(dst.to_reg().to_reg());
2941
+ debug_assert_eq!(rhs, dst);
2942
+
2943
+ // Generates the following sequence:
2944
+ // cmpss/cmpsd %lhs, %rhs_dst
2945
+ // jnz do_min_max
2946
+ // jp propagate_nan
2947
+ //
2948
+ // ;; ordered and equal: propagate the sign bit (for -0 vs 0):
2949
+ // {and,or}{ss,sd} %lhs, %rhs_dst
2950
+ // j done
2951
+ //
2952
+ // ;; to get the desired NaN behavior (signalling NaN transformed into a quiet NaN, the
2953
+ // ;; NaN value is returned), we add both inputs.
2954
+ // propagate_nan:
2955
+ // add{ss,sd} %lhs, %rhs_dst
2956
+ // j done
2957
+ //
2958
+ // do_min_max:
2959
+ // {min,max}{ss,sd} %lhs, %rhs_dst
2960
+ //
2961
+ // done:
2962
+ let done = sink.get_label();
2963
+ let propagate_nan = sink.get_label();
2964
+ let do_min_max = sink.get_label();
2965
+
2966
+ let (add_op, cmp_op, and_op, or_op, min_max_op) = match size {
2967
+ OperandSize::Size32 => (
2968
+ SseOpcode::Addss,
2969
+ SseOpcode::Ucomiss,
2970
+ SseOpcode::Andps,
2971
+ SseOpcode::Orps,
2972
+ if *is_min {
2973
+ SseOpcode::Minss
2974
+ } else {
2975
+ SseOpcode::Maxss
2976
+ },
2977
+ ),
2978
+ OperandSize::Size64 => (
2979
+ SseOpcode::Addsd,
2980
+ SseOpcode::Ucomisd,
2981
+ SseOpcode::Andpd,
2982
+ SseOpcode::Orpd,
2983
+ if *is_min {
2984
+ SseOpcode::Minsd
2985
+ } else {
2986
+ SseOpcode::Maxsd
2987
+ },
2988
+ ),
2989
+ _ => unreachable!(),
2990
+ };
2991
+
2992
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(lhs), dst);
2993
+ inst.emit(&[], sink, info, state);
2994
+
2995
+ one_way_jmp(sink, CC::NZ, do_min_max);
2996
+ one_way_jmp(sink, CC::P, propagate_nan);
2997
+
2998
+ // Ordered and equal. The operands are bit-identical unless they are zero
2999
+ // and negative zero. These instructions merge the sign bits in that
3000
+ // case, and are no-ops otherwise.
3001
+ let op = if *is_min { or_op } else { and_op };
3002
+ let inst = Inst::xmm_rm_r(op, RegMem::reg(lhs), Writable::from_reg(dst));
3003
+ inst.emit(&[], sink, info, state);
3004
+
3005
+ let inst = Inst::jmp_known(done);
3006
+ inst.emit(&[], sink, info, state);
3007
+
3008
+ // x86's min/max are not symmetric; if either operand is a NaN, they return the
3009
+ // read-only operand: perform an addition between the two operands, which has the
3010
+ // desired NaN propagation effects.
3011
+ sink.bind_label(propagate_nan, state.ctrl_plane_mut());
3012
+ let inst = Inst::xmm_rm_r(add_op, RegMem::reg(lhs), Writable::from_reg(dst));
3013
+ inst.emit(&[], sink, info, state);
3014
+
3015
+ one_way_jmp(sink, CC::P, done);
3016
+
3017
+ sink.bind_label(do_min_max, state.ctrl_plane_mut());
3018
+
3019
+ let inst = Inst::xmm_rm_r(min_max_op, RegMem::reg(lhs), Writable::from_reg(dst));
3020
+ inst.emit(&[], sink, info, state);
3021
+
3022
+ sink.bind_label(done, state.ctrl_plane_mut());
3023
+ }
3024
+
3025
+ Inst::XmmRmRImm {
3026
+ op,
3027
+ src1,
3028
+ src2,
3029
+ dst,
3030
+ imm,
3031
+ size,
3032
+ } => {
3033
+ let src1 = allocs.next(*src1);
3034
+ let dst = allocs.next(dst.to_reg());
3035
+ let src2 = src2.with_allocs(allocs);
3036
+ debug_assert_eq!(src1, dst);
3037
+
3038
+ let (prefix, opcode, len) = match op {
3039
+ SseOpcode::Cmpps => (LegacyPrefixes::None, 0x0FC2, 2),
3040
+ SseOpcode::Cmppd => (LegacyPrefixes::_66, 0x0FC2, 2),
3041
+ SseOpcode::Cmpss => (LegacyPrefixes::_F3, 0x0FC2, 2),
3042
+ SseOpcode::Cmpsd => (LegacyPrefixes::_F2, 0x0FC2, 2),
3043
+ SseOpcode::Insertps => (LegacyPrefixes::_66, 0x0F3A21, 3),
3044
+ SseOpcode::Palignr => (LegacyPrefixes::_66, 0x0F3A0F, 3),
3045
+ SseOpcode::Pinsrb => (LegacyPrefixes::_66, 0x0F3A20, 3),
3046
+ SseOpcode::Pinsrw => (LegacyPrefixes::_66, 0x0FC4, 2),
3047
+ SseOpcode::Pinsrd => (LegacyPrefixes::_66, 0x0F3A22, 3),
3048
+ SseOpcode::Shufps => (LegacyPrefixes::None, 0x0FC6, 2),
3049
+ SseOpcode::Pblendw => (LegacyPrefixes::_66, 0x0F3A0E, 3),
3050
+ _ => unimplemented!("Opcode {:?} not implemented", op),
3051
+ };
3052
+ let rex = RexFlags::from(*size);
3053
+ let regs_swapped = match *op {
3054
+ // These opcodes (and not the SSE2 version of PEXTRW) flip the operand
3055
+ // encoding: `dst` in ModRM's r/m, `src` in ModRM's reg field.
3056
+ SseOpcode::Pextrb | SseOpcode::Pextrd => true,
3057
+ // The rest of the opcodes have the customary encoding: `dst` in ModRM's reg,
3058
+ // `src` in ModRM's r/m field.
3059
+ _ => false,
3060
+ };
3061
+ match src2 {
3062
+ RegMem::Reg { reg } => {
3063
+ if regs_swapped {
3064
+ emit_std_reg_reg(sink, prefix, opcode, len, reg, dst, rex);
3065
+ } else {
3066
+ emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
3067
+ }
3068
+ }
3069
+ RegMem::Mem { addr } => {
3070
+ let addr = &addr.finalize(state, sink);
3071
+ assert!(
3072
+ !regs_swapped,
3073
+ "No existing way to encode a mem argument in the ModRM r/m field."
3074
+ );
3075
+ // N.B.: bytes_at_end == 1, because of the `imm` byte below.
3076
+ emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 1);
3077
+ }
3078
+ }
3079
+ sink.put1(*imm);
3080
+ }
3081
+
3082
+ Inst::XmmUninitializedValue { .. } => {
3083
+ // This instruction format only exists to declare a register as a `def`; no code is
3084
+ // emitted.
3085
+ }
3086
+
3087
+ Inst::XmmMovRM { op, src, dst } => {
3088
+ let src = allocs.next(src.to_reg());
3089
+ let dst = dst.with_allocs(allocs);
3090
+
3091
+ let (prefix, opcode) = match op {
3092
+ SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F29),
3093
+ SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F29),
3094
+ SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F7F),
3095
+ SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F11),
3096
+ SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F11),
3097
+ SseOpcode::Movups => (LegacyPrefixes::None, 0x0F11),
3098
+ SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F11),
3099
+ _ => unimplemented!("Opcode {:?} not implemented", op),
3100
+ };
3101
+ let dst = &dst.finalize(state, sink);
3102
+ emit_std_reg_mem(sink, prefix, opcode, 2, src, dst, RexFlags::clear_w(), 0);
3103
+ }
3104
+
3105
+ Inst::XmmMovRMImm { op, src, dst, imm } => {
3106
+ let src = allocs.next(src.to_reg());
3107
+ let dst = dst.with_allocs(allocs);
3108
+
3109
+ let (w, prefix, opcode) = match op {
3110
+ SseOpcode::Pextrb => (false, LegacyPrefixes::_66, 0x0F3A14),
3111
+ SseOpcode::Pextrw => (false, LegacyPrefixes::_66, 0x0F3A15),
3112
+ SseOpcode::Pextrd => (false, LegacyPrefixes::_66, 0x0F3A16),
3113
+ SseOpcode::Pextrq => (true, LegacyPrefixes::_66, 0x0F3A16),
3114
+ _ => unimplemented!("Opcode {:?} not implemented", op),
3115
+ };
3116
+ let rex = if w {
3117
+ RexFlags::set_w()
3118
+ } else {
3119
+ RexFlags::clear_w()
3120
+ };
3121
+ let dst = &dst.finalize(state, sink);
3122
+ emit_std_reg_mem(sink, prefix, opcode, 3, src, dst, rex, 1);
3123
+ sink.put1(*imm);
3124
+ }
3125
+
3126
+ Inst::XmmToGpr {
3127
+ op,
3128
+ src,
3129
+ dst,
3130
+ dst_size,
3131
+ } => {
3132
+ let src = allocs.next(src.to_reg());
3133
+ let dst = allocs.next(dst.to_reg().to_reg());
3134
+
3135
+ let (prefix, opcode, dst_first) = match op {
3136
+ SseOpcode::Cvttss2si => (LegacyPrefixes::_F3, 0x0F2C, true),
3137
+ SseOpcode::Cvttsd2si => (LegacyPrefixes::_F2, 0x0F2C, true),
3138
+ // Movd and movq use the same opcode; the presence of the REX prefix (set below)
3139
+ // actually determines which is used.
3140
+ SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F7E, false),
3141
+ SseOpcode::Movmskps => (LegacyPrefixes::None, 0x0F50, true),
3142
+ SseOpcode::Movmskpd => (LegacyPrefixes::_66, 0x0F50, true),
3143
+ SseOpcode::Pmovmskb => (LegacyPrefixes::_66, 0x0FD7, true),
3144
+ _ => panic!("unexpected opcode {:?}", op),
3145
+ };
3146
+ let rex = RexFlags::from(*dst_size);
3147
+ let (src, dst) = if dst_first { (dst, src) } else { (src, dst) };
3148
+
3149
+ emit_std_reg_reg(sink, prefix, opcode, 2, src, dst, rex);
3150
+ }
3151
+
3152
+ Inst::XmmToGprImm { op, src, dst, imm } => {
3153
+ use OperandSize as OS;
3154
+
3155
+ let src = allocs.next(src.to_reg());
3156
+ let dst = allocs.next(dst.to_reg().to_reg());
3157
+
3158
+ let (prefix, opcode, opcode_bytes, dst_size, dst_first) = match op {
3159
+ SseOpcode::Pextrb => (LegacyPrefixes::_66, 0x0F3A14, 3, OS::Size32, false),
3160
+ SseOpcode::Pextrw => (LegacyPrefixes::_66, 0x0FC5, 2, OS::Size32, true),
3161
+ SseOpcode::Pextrd => (LegacyPrefixes::_66, 0x0F3A16, 3, OS::Size32, false),
3162
+ SseOpcode::Pextrq => (LegacyPrefixes::_66, 0x0F3A16, 3, OS::Size64, false),
3163
+ _ => panic!("unexpected opcode {:?}", op),
3164
+ };
3165
+ let rex = RexFlags::from(dst_size);
3166
+ let (src, dst) = if dst_first { (dst, src) } else { (src, dst) };
3167
+
3168
+ emit_std_reg_reg(sink, prefix, opcode, opcode_bytes, src, dst, rex);
3169
+ sink.put1(*imm);
3170
+ }
3171
+
3172
+ Inst::GprToXmm {
3173
+ op,
3174
+ src: src_e,
3175
+ dst: reg_g,
3176
+ src_size,
3177
+ } => {
3178
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
3179
+ let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
3180
+
3181
+ let (prefix, opcode) = match op {
3182
+ // Movd and movq use the same opcode; the presence of the REX prefix (set below)
3183
+ // actually determines which is used.
3184
+ SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F6E),
3185
+ _ => panic!("unexpected opcode {:?}", op),
3186
+ };
3187
+ let rex = RexFlags::from(*src_size);
3188
+ match src_e {
3189
+ RegMem::Reg { reg: reg_e } => {
3190
+ emit_std_reg_reg(sink, prefix, opcode, 2, reg_g, reg_e, rex);
3191
+ }
3192
+ RegMem::Mem { addr } => {
3193
+ let addr = &addr.finalize(state, sink);
3194
+ emit_std_reg_mem(sink, prefix, opcode, 2, reg_g, addr, rex, 0);
3195
+ }
3196
+ }
3197
+ }
3198
+
3199
+ Inst::XmmCmpRmR { op, src, dst } => {
3200
+ let dst = allocs.next(dst.to_reg());
3201
+ let src = src.clone().to_reg_mem().with_allocs(allocs);
3202
+
3203
+ let rex = RexFlags::clear_w();
3204
+ let (prefix, opcode, len) = match op {
3205
+ SseOpcode::Ptest => (LegacyPrefixes::_66, 0x0F3817, 3),
3206
+ SseOpcode::Ucomisd => (LegacyPrefixes::_66, 0x0F2E, 2),
3207
+ SseOpcode::Ucomiss => (LegacyPrefixes::None, 0x0F2E, 2),
3208
+ _ => unimplemented!("Emit xmm cmp rm r"),
3209
+ };
3210
+
3211
+ match src {
3212
+ RegMem::Reg { reg } => {
3213
+ emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
3214
+ }
3215
+ RegMem::Mem { addr } => {
3216
+ let addr = &addr.finalize(state, sink);
3217
+ emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 0);
3218
+ }
3219
+ }
3220
+ }
3221
+
3222
+ Inst::CvtIntToFloat {
3223
+ op,
3224
+ src1,
3225
+ src2,
3226
+ dst,
3227
+ src2_size,
3228
+ } => {
3229
+ let src1 = allocs.next(src1.to_reg());
3230
+ let dst = allocs.next(dst.to_reg().to_reg());
3231
+ assert_eq!(src1, dst);
3232
+ let src2 = src2.clone().to_reg_mem().with_allocs(allocs);
3233
+
3234
+ let (prefix, opcode) = match op {
3235
+ SseOpcode::Cvtsi2ss => (LegacyPrefixes::_F3, 0x0F2A),
3236
+ SseOpcode::Cvtsi2sd => (LegacyPrefixes::_F2, 0x0F2A),
3237
+ _ => panic!("unexpected opcode {:?}", op),
3238
+ };
3239
+ let rex = RexFlags::from(*src2_size);
3240
+ match src2 {
3241
+ RegMem::Reg { reg: src2 } => {
3242
+ emit_std_reg_reg(sink, prefix, opcode, 2, dst, src2, rex);
3243
+ }
3244
+ RegMem::Mem { addr } => {
3245
+ let addr = &addr.finalize(state, sink);
3246
+ emit_std_reg_mem(sink, prefix, opcode, 2, dst, addr, rex, 0);
3247
+ }
3248
+ }
3249
+ }
3250
+
3251
+ Inst::CvtIntToFloatVex {
3252
+ op,
3253
+ src1,
3254
+ src2,
3255
+ dst,
3256
+ src2_size,
3257
+ } => {
3258
+ let dst = allocs.next(dst.to_reg().to_reg());
3259
+ let src1 = allocs.next(src1.to_reg());
3260
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
3261
+ RegMem::Reg { reg } => {
3262
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
3263
+ }
3264
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
3265
+ };
3266
+
3267
+ let (prefix, map, opcode) = match op {
3268
+ AvxOpcode::Vcvtsi2ss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x2A),
3269
+ AvxOpcode::Vcvtsi2sd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x2A),
3270
+ _ => unimplemented!("Opcode {:?} not implemented", op),
3271
+ };
3272
+ let w = match src2_size {
3273
+ OperandSize::Size64 => true,
3274
+ _ => false,
3275
+ };
3276
+ VexInstruction::new()
3277
+ .length(VexVectorLength::V128)
3278
+ .w(w)
3279
+ .prefix(prefix)
3280
+ .map(map)
3281
+ .opcode(opcode)
3282
+ .rm(src2)
3283
+ .reg(dst.to_real_reg().unwrap().hw_enc())
3284
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
3285
+ .encode(sink);
3286
+ }
3287
+
3288
+ Inst::CvtUint64ToFloatSeq {
3289
+ dst_size,
3290
+ src,
3291
+ dst,
3292
+ tmp_gpr1,
3293
+ tmp_gpr2,
3294
+ } => {
3295
+ let src = allocs.next(src.to_reg());
3296
+ let dst = allocs.next(dst.to_reg().to_reg());
3297
+ let tmp_gpr1 = allocs.next(tmp_gpr1.to_reg().to_reg());
3298
+ let tmp_gpr2 = allocs.next(tmp_gpr2.to_reg().to_reg());
3299
+
3300
+ // Note: this sequence is specific to 64-bit mode; a 32-bit mode would require a
3301
+ // different sequence.
3302
+ //
3303
+ // Emit the following sequence:
3304
+ //
3305
+ // cmp 0, %src
3306
+ // jl handle_negative
3307
+ //
3308
+ // ;; handle positive, which can't overflow
3309
+ // cvtsi2sd/cvtsi2ss %src, %dst
3310
+ // j done
3311
+ //
3312
+ // ;; handle negative: see below for an explanation of what it's doing.
3313
+ // handle_negative:
3314
+ // mov %src, %tmp_gpr1
3315
+ // shr $1, %tmp_gpr1
3316
+ // mov %src, %tmp_gpr2
3317
+ // and $1, %tmp_gpr2
3318
+ // or %tmp_gpr1, %tmp_gpr2
3319
+ // cvtsi2sd/cvtsi2ss %tmp_gpr2, %dst
3320
+ // addsd/addss %dst, %dst
3321
+ //
3322
+ // done:
3323
+
3324
+ assert_ne!(src, tmp_gpr1);
3325
+ assert_ne!(src, tmp_gpr2);
3326
+ assert_ne!(tmp_gpr1, tmp_gpr2);
3327
+
3328
+ let handle_negative = sink.get_label();
3329
+ let done = sink.get_label();
3330
+
3331
+ // If x seen as a signed int64 is not negative, a signed-conversion will do the right
3332
+ // thing.
3333
+ // TODO use tst src, src here.
3334
+ let inst = Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::imm(0), src);
3335
+ inst.emit(&[], sink, info, state);
3336
+
3337
+ one_way_jmp(sink, CC::L, handle_negative);
3338
+
3339
+ // Handle a positive int64, which is the "easy" case: a signed conversion will do the
3340
+ // right thing.
3341
+ emit_signed_cvt(
3342
+ sink,
3343
+ info,
3344
+ state,
3345
+ src,
3346
+ Writable::from_reg(dst),
3347
+ *dst_size == OperandSize::Size64,
3348
+ );
3349
+
3350
+ let inst = Inst::jmp_known(done);
3351
+ inst.emit(&[], sink, info, state);
3352
+
3353
+ sink.bind_label(handle_negative, state.ctrl_plane_mut());
3354
+
3355
+ // Divide x by two to get it in range for the signed conversion, keep the LSB, and
3356
+ // scale it back up on the FP side.
3357
+ let inst = Inst::gen_move(Writable::from_reg(tmp_gpr1), src, types::I64);
3358
+ inst.emit(&[], sink, info, state);
3359
+
3360
+ // tmp_gpr1 := src >> 1
3361
+ let inst = Inst::shift_r(
3362
+ OperandSize::Size64,
3363
+ ShiftKind::ShiftRightLogical,
3364
+ Imm8Gpr::new(Imm8Reg::Imm8 { imm: 1 }).unwrap(),
3365
+ tmp_gpr1,
3366
+ Writable::from_reg(tmp_gpr1),
3367
+ );
3368
+ inst.emit(&[], sink, info, state);
3369
+
3370
+ let inst = Inst::gen_move(Writable::from_reg(tmp_gpr2), src, types::I64);
3371
+ inst.emit(&[], sink, info, state);
3372
+
3373
+ let inst = Inst::alu_rmi_r(
3374
+ OperandSize::Size64,
3375
+ AluRmiROpcode::And,
3376
+ RegMemImm::imm(1),
3377
+ Writable::from_reg(tmp_gpr2),
3378
+ );
3379
+ inst.emit(&[], sink, info, state);
3380
+
3381
+ let inst = Inst::alu_rmi_r(
3382
+ OperandSize::Size64,
3383
+ AluRmiROpcode::Or,
3384
+ RegMemImm::reg(tmp_gpr1),
3385
+ Writable::from_reg(tmp_gpr2),
3386
+ );
3387
+ inst.emit(&[], sink, info, state);
3388
+
3389
+ emit_signed_cvt(
3390
+ sink,
3391
+ info,
3392
+ state,
3393
+ tmp_gpr2,
3394
+ Writable::from_reg(dst),
3395
+ *dst_size == OperandSize::Size64,
3396
+ );
3397
+
3398
+ let add_op = if *dst_size == OperandSize::Size64 {
3399
+ SseOpcode::Addsd
3400
+ } else {
3401
+ SseOpcode::Addss
3402
+ };
3403
+ let inst = Inst::xmm_rm_r(add_op, RegMem::reg(dst), Writable::from_reg(dst));
3404
+ inst.emit(&[], sink, info, state);
3405
+
3406
+ sink.bind_label(done, state.ctrl_plane_mut());
3407
+ }
3408
+
3409
+ Inst::CvtFloatToSintSeq {
3410
+ src_size,
3411
+ dst_size,
3412
+ is_saturating,
3413
+ src,
3414
+ dst,
3415
+ tmp_gpr,
3416
+ tmp_xmm,
3417
+ } => {
3418
+ let src = allocs.next(src.to_reg());
3419
+ let dst = allocs.next(dst.to_reg().to_reg());
3420
+ let tmp_gpr = allocs.next(tmp_gpr.to_reg().to_reg());
3421
+ let tmp_xmm = allocs.next(tmp_xmm.to_reg().to_reg());
3422
+
3423
+ // Emits the following common sequence:
3424
+ //
3425
+ // cvttss2si/cvttsd2si %src, %dst
3426
+ // cmp %dst, 1
3427
+ // jno done
3428
+ //
3429
+ // Then, for saturating conversions:
3430
+ //
3431
+ // ;; check for NaN
3432
+ // cmpss/cmpsd %src, %src
3433
+ // jnp not_nan
3434
+ // xor %dst, %dst
3435
+ //
3436
+ // ;; positive inputs get saturated to INT_MAX; negative ones to INT_MIN, which is
3437
+ // ;; already in %dst.
3438
+ // xorpd %tmp_xmm, %tmp_xmm
3439
+ // cmpss/cmpsd %src, %tmp_xmm
3440
+ // jnb done
3441
+ // mov/movaps $INT_MAX, %dst
3442
+ //
3443
+ // done:
3444
+ //
3445
+ // Then, for non-saturating conversions:
3446
+ //
3447
+ // ;; check for NaN
3448
+ // cmpss/cmpsd %src, %src
3449
+ // jnp not_nan
3450
+ // ud2 trap BadConversionToInteger
3451
+ //
3452
+ // ;; check if INT_MIN was the correct result, against a magic constant:
3453
+ // not_nan:
3454
+ // movaps/mov $magic, %tmp_gpr
3455
+ // movq/movd %tmp_gpr, %tmp_xmm
3456
+ // cmpss/cmpsd %tmp_xmm, %src
3457
+ // jnb/jnbe $check_positive
3458
+ // ud2 trap IntegerOverflow
3459
+ //
3460
+ // ;; if positive, it was a real overflow
3461
+ // check_positive:
3462
+ // xorpd %tmp_xmm, %tmp_xmm
3463
+ // cmpss/cmpsd %src, %tmp_xmm
3464
+ // jnb done
3465
+ // ud2 trap IntegerOverflow
3466
+ //
3467
+ // done:
3468
+
3469
+ let (cast_op, cmp_op, trunc_op) = match src_size {
3470
+ OperandSize::Size64 => (SseOpcode::Movq, SseOpcode::Ucomisd, SseOpcode::Cvttsd2si),
3471
+ OperandSize::Size32 => (SseOpcode::Movd, SseOpcode::Ucomiss, SseOpcode::Cvttss2si),
3472
+ _ => unreachable!(),
3473
+ };
3474
+
3475
+ let done = sink.get_label();
3476
+
3477
+ // The truncation.
3478
+ let inst = Inst::xmm_to_gpr(trunc_op, src, Writable::from_reg(dst), *dst_size);
3479
+ inst.emit(&[], sink, info, state);
3480
+
3481
+ // Compare against 1, in case of overflow the dst operand was INT_MIN.
3482
+ let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(1), dst);
3483
+ inst.emit(&[], sink, info, state);
3484
+
3485
+ one_way_jmp(sink, CC::NO, done); // no overflow => done
3486
+
3487
+ // Check for NaN.
3488
+
3489
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), src);
3490
+ inst.emit(&[], sink, info, state);
3491
+
3492
+ if *is_saturating {
3493
+ let not_nan = sink.get_label();
3494
+ one_way_jmp(sink, CC::NP, not_nan); // go to not_nan if not a NaN
3495
+
3496
+ // For NaN, emit 0.
3497
+ let inst = Inst::alu_rmi_r(
3498
+ *dst_size,
3499
+ AluRmiROpcode::Xor,
3500
+ RegMemImm::reg(dst),
3501
+ Writable::from_reg(dst),
3502
+ );
3503
+ inst.emit(&[], sink, info, state);
3504
+
3505
+ let inst = Inst::jmp_known(done);
3506
+ inst.emit(&[], sink, info, state);
3507
+
3508
+ sink.bind_label(not_nan, state.ctrl_plane_mut());
3509
+
3510
+ // If the input was positive, saturate to INT_MAX.
3511
+
3512
+ // Zero out tmp_xmm.
3513
+ let inst = Inst::xmm_rm_r(
3514
+ SseOpcode::Xorpd,
3515
+ RegMem::reg(tmp_xmm),
3516
+ Writable::from_reg(tmp_xmm),
3517
+ );
3518
+ inst.emit(&[], sink, info, state);
3519
+
3520
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
3521
+ inst.emit(&[], sink, info, state);
3522
+
3523
+ // Jump if >= to done.
3524
+ one_way_jmp(sink, CC::NB, done);
3525
+
3526
+ // Otherwise, put INT_MAX.
3527
+ if *dst_size == OperandSize::Size64 {
3528
+ let inst = Inst::imm(
3529
+ OperandSize::Size64,
3530
+ 0x7fffffffffffffff,
3531
+ Writable::from_reg(dst),
3532
+ );
3533
+ inst.emit(&[], sink, info, state);
3534
+ } else {
3535
+ let inst = Inst::imm(OperandSize::Size32, 0x7fffffff, Writable::from_reg(dst));
3536
+ inst.emit(&[], sink, info, state);
3537
+ }
3538
+ } else {
3539
+ let inst = Inst::trap_if(CC::P, TrapCode::BadConversionToInteger);
3540
+ inst.emit(&[], sink, info, state);
3541
+
3542
+ // Check if INT_MIN was the correct result: determine the smallest floating point
3543
+ // number that would convert to INT_MIN, put it in a temporary register, and compare
3544
+ // against the src register.
3545
+ // If the src register is less (or in some cases, less-or-equal) than the threshold,
3546
+ // trap!
3547
+
3548
+ let mut no_overflow_cc = CC::NB; // >=
3549
+ let output_bits = dst_size.to_bits();
3550
+ match *src_size {
3551
+ OperandSize::Size32 => {
3552
+ let cst = Ieee32::pow2(output_bits - 1).neg().bits();
3553
+ let inst =
3554
+ Inst::imm(OperandSize::Size32, cst as u64, Writable::from_reg(tmp_gpr));
3555
+ inst.emit(&[], sink, info, state);
3556
+ }
3557
+ OperandSize::Size64 => {
3558
+ // An f64 can represent `i32::min_value() - 1` exactly with precision to spare,
3559
+ // so there are values less than -2^(N-1) that convert correctly to INT_MIN.
3560
+ let cst = if output_bits < 64 {
3561
+ no_overflow_cc = CC::NBE; // >
3562
+ Ieee64::fcvt_to_sint_negative_overflow(output_bits)
3563
+ } else {
3564
+ Ieee64::pow2(output_bits - 1).neg()
3565
+ };
3566
+ let inst =
3567
+ Inst::imm(OperandSize::Size64, cst.bits(), Writable::from_reg(tmp_gpr));
3568
+ inst.emit(&[], sink, info, state);
3569
+ }
3570
+ _ => unreachable!(),
3571
+ }
3572
+
3573
+ let inst = Inst::gpr_to_xmm(
3574
+ cast_op,
3575
+ RegMem::reg(tmp_gpr),
3576
+ *src_size,
3577
+ Writable::from_reg(tmp_xmm),
3578
+ );
3579
+ inst.emit(&[], sink, info, state);
3580
+
3581
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
3582
+ inst.emit(&[], sink, info, state);
3583
+
3584
+ // no trap if src >= or > threshold
3585
+ let inst = Inst::trap_if(no_overflow_cc.invert(), TrapCode::IntegerOverflow);
3586
+ inst.emit(&[], sink, info, state);
3587
+
3588
+ // If positive, it was a real overflow.
3589
+
3590
+ // Zero out the tmp_xmm register.
3591
+ let inst = Inst::xmm_rm_r(
3592
+ SseOpcode::Xorpd,
3593
+ RegMem::reg(tmp_xmm),
3594
+ Writable::from_reg(tmp_xmm),
3595
+ );
3596
+ inst.emit(&[], sink, info, state);
3597
+
3598
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
3599
+ inst.emit(&[], sink, info, state);
3600
+
3601
+ // no trap if 0 >= src
3602
+ let inst = Inst::trap_if(CC::B, TrapCode::IntegerOverflow);
3603
+ inst.emit(&[], sink, info, state);
3604
+ }
3605
+
3606
+ sink.bind_label(done, state.ctrl_plane_mut());
3607
+ }
3608
+
3609
+ Inst::CvtFloatToUintSeq {
3610
+ src_size,
3611
+ dst_size,
3612
+ is_saturating,
3613
+ src,
3614
+ dst,
3615
+ tmp_gpr,
3616
+ tmp_xmm,
3617
+ tmp_xmm2,
3618
+ } => {
3619
+ let src = allocs.next(src.to_reg());
3620
+ let dst = allocs.next(dst.to_reg().to_reg());
3621
+ let tmp_gpr = allocs.next(tmp_gpr.to_reg().to_reg());
3622
+ let tmp_xmm = allocs.next(tmp_xmm.to_reg().to_reg());
3623
+ let tmp_xmm2 = allocs.next(tmp_xmm2.to_reg().to_reg());
3624
+
3625
+ // The only difference in behavior between saturating and non-saturating is how we
3626
+ // handle errors. Emits the following sequence:
3627
+ //
3628
+ // movaps/mov 2**(int_width - 1), %tmp_gpr
3629
+ // movq/movd %tmp_gpr, %tmp_xmm
3630
+ // cmpss/cmpsd %tmp_xmm, %src
3631
+ // jnb is_large
3632
+ //
3633
+ // ;; check for NaN inputs
3634
+ // jnp not_nan
3635
+ // -- non-saturating: ud2 trap BadConversionToInteger
3636
+ // -- saturating: xor %dst, %dst; j done
3637
+ //
3638
+ // not_nan:
3639
+ // cvttss2si/cvttsd2si %src, %dst
3640
+ // cmp 0, %dst
3641
+ // jnl done
3642
+ // -- non-saturating: ud2 trap IntegerOverflow
3643
+ // -- saturating: xor %dst, %dst; j done
3644
+ //
3645
+ // is_large:
3646
+ // mov %src, %tmp_xmm2
3647
+ // subss/subsd %tmp_xmm, %tmp_xmm2
3648
+ // cvttss2si/cvttss2sd %tmp_x, %dst
3649
+ // cmp 0, %dst
3650
+ // jnl next_is_large
3651
+ // -- non-saturating: ud2 trap IntegerOverflow
3652
+ // -- saturating: movaps $UINT_MAX, %dst; j done
3653
+ //
3654
+ // next_is_large:
3655
+ // add 2**(int_width -1), %dst ;; 2 instructions for 64-bits integers
3656
+ //
3657
+ // done:
3658
+
3659
+ assert_ne!(tmp_xmm, src, "tmp_xmm clobbers src!");
3660
+
3661
+ let (sub_op, cast_op, cmp_op, trunc_op) = match src_size {
3662
+ OperandSize::Size32 => (
3663
+ SseOpcode::Subss,
3664
+ SseOpcode::Movd,
3665
+ SseOpcode::Ucomiss,
3666
+ SseOpcode::Cvttss2si,
3667
+ ),
3668
+ OperandSize::Size64 => (
3669
+ SseOpcode::Subsd,
3670
+ SseOpcode::Movq,
3671
+ SseOpcode::Ucomisd,
3672
+ SseOpcode::Cvttsd2si,
3673
+ ),
3674
+ _ => unreachable!(),
3675
+ };
3676
+
3677
+ let done = sink.get_label();
3678
+
3679
+ let cst = match src_size {
3680
+ OperandSize::Size32 => Ieee32::pow2(dst_size.to_bits() - 1).bits() as u64,
3681
+ OperandSize::Size64 => Ieee64::pow2(dst_size.to_bits() - 1).bits(),
3682
+ _ => unreachable!(),
3683
+ };
3684
+
3685
+ let inst = Inst::imm(*src_size, cst, Writable::from_reg(tmp_gpr));
3686
+ inst.emit(&[], sink, info, state);
3687
+
3688
+ let inst = Inst::gpr_to_xmm(
3689
+ cast_op,
3690
+ RegMem::reg(tmp_gpr),
3691
+ *src_size,
3692
+ Writable::from_reg(tmp_xmm),
3693
+ );
3694
+ inst.emit(&[], sink, info, state);
3695
+
3696
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
3697
+ inst.emit(&[], sink, info, state);
3698
+
3699
+ let handle_large = sink.get_label();
3700
+ one_way_jmp(sink, CC::NB, handle_large); // jump to handle_large if src >= large_threshold
3701
+
3702
+ if *is_saturating {
3703
+ // If not NaN jump over this 0-return, otherwise return 0
3704
+ let not_nan = sink.get_label();
3705
+ one_way_jmp(sink, CC::NP, not_nan);
3706
+ let inst = Inst::alu_rmi_r(
3707
+ *dst_size,
3708
+ AluRmiROpcode::Xor,
3709
+ RegMemImm::reg(dst),
3710
+ Writable::from_reg(dst),
3711
+ );
3712
+ inst.emit(&[], sink, info, state);
3713
+
3714
+ let inst = Inst::jmp_known(done);
3715
+ inst.emit(&[], sink, info, state);
3716
+ sink.bind_label(not_nan, state.ctrl_plane_mut());
3717
+ } else {
3718
+ // Trap.
3719
+ let inst = Inst::trap_if(CC::P, TrapCode::BadConversionToInteger);
3720
+ inst.emit(&[], sink, info, state);
3721
+ }
3722
+
3723
+ // Actual truncation for small inputs: if the result is not positive, then we had an
3724
+ // overflow.
3725
+
3726
+ let inst = Inst::xmm_to_gpr(trunc_op, src, Writable::from_reg(dst), *dst_size);
3727
+ inst.emit(&[], sink, info, state);
3728
+
3729
+ let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst);
3730
+ inst.emit(&[], sink, info, state);
3731
+
3732
+ one_way_jmp(sink, CC::NL, done); // if dst >= 0, jump to done
3733
+
3734
+ if *is_saturating {
3735
+ // The input was "small" (< 2**(width -1)), so the only way to get an integer
3736
+ // overflow is because the input was too small: saturate to the min value, i.e. 0.
3737
+ let inst = Inst::alu_rmi_r(
3738
+ *dst_size,
3739
+ AluRmiROpcode::Xor,
3740
+ RegMemImm::reg(dst),
3741
+ Writable::from_reg(dst),
3742
+ );
3743
+ inst.emit(&[], sink, info, state);
3744
+
3745
+ let inst = Inst::jmp_known(done);
3746
+ inst.emit(&[], sink, info, state);
3747
+ } else {
3748
+ // Trap.
3749
+ let inst = Inst::trap(TrapCode::IntegerOverflow);
3750
+ inst.emit(&[], sink, info, state);
3751
+ }
3752
+
3753
+ // Now handle large inputs.
3754
+
3755
+ sink.bind_label(handle_large, state.ctrl_plane_mut());
3756
+
3757
+ let inst = Inst::gen_move(Writable::from_reg(tmp_xmm2), src, types::F64);
3758
+ inst.emit(&[], sink, info, state);
3759
+
3760
+ let inst = Inst::xmm_rm_r(sub_op, RegMem::reg(tmp_xmm), Writable::from_reg(tmp_xmm2));
3761
+ inst.emit(&[], sink, info, state);
3762
+
3763
+ let inst = Inst::xmm_to_gpr(trunc_op, tmp_xmm2, Writable::from_reg(dst), *dst_size);
3764
+ inst.emit(&[], sink, info, state);
3765
+
3766
+ let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst);
3767
+ inst.emit(&[], sink, info, state);
3768
+
3769
+ if *is_saturating {
3770
+ let next_is_large = sink.get_label();
3771
+ one_way_jmp(sink, CC::NL, next_is_large); // if dst >= 0, jump to next_is_large
3772
+
3773
+ // The input was "large" (>= 2**(width -1)), so the only way to get an integer
3774
+ // overflow is because the input was too large: saturate to the max value.
3775
+ let inst = Inst::imm(
3776
+ OperandSize::Size64,
3777
+ if *dst_size == OperandSize::Size64 {
3778
+ u64::max_value()
3779
+ } else {
3780
+ u32::max_value() as u64
3781
+ },
3782
+ Writable::from_reg(dst),
3783
+ );
3784
+ inst.emit(&[], sink, info, state);
3785
+
3786
+ let inst = Inst::jmp_known(done);
3787
+ inst.emit(&[], sink, info, state);
3788
+ sink.bind_label(next_is_large, state.ctrl_plane_mut());
3789
+ } else {
3790
+ let inst = Inst::trap_if(CC::L, TrapCode::IntegerOverflow);
3791
+ inst.emit(&[], sink, info, state);
3792
+ }
3793
+
3794
+ if *dst_size == OperandSize::Size64 {
3795
+ let inst = Inst::imm(OperandSize::Size64, 1 << 63, Writable::from_reg(tmp_gpr));
3796
+ inst.emit(&[], sink, info, state);
3797
+
3798
+ let inst = Inst::alu_rmi_r(
3799
+ OperandSize::Size64,
3800
+ AluRmiROpcode::Add,
3801
+ RegMemImm::reg(tmp_gpr),
3802
+ Writable::from_reg(dst),
3803
+ );
3804
+ inst.emit(&[], sink, info, state);
3805
+ } else {
3806
+ let inst = Inst::alu_rmi_r(
3807
+ OperandSize::Size32,
3808
+ AluRmiROpcode::Add,
3809
+ RegMemImm::imm(1 << 31),
3810
+ Writable::from_reg(dst),
3811
+ );
3812
+ inst.emit(&[], sink, info, state);
3813
+ }
3814
+
3815
+ sink.bind_label(done, state.ctrl_plane_mut());
3816
+ }
3817
+
3818
+ Inst::LoadExtName {
3819
+ dst,
3820
+ name,
3821
+ offset,
3822
+ distance,
3823
+ } => {
3824
+ let dst = allocs.next(dst.to_reg());
3825
+
3826
+ if info.flags.is_pic() {
3827
+ // Generates: movq symbol@GOTPCREL(%rip), %dst
3828
+ let enc_dst = int_reg_enc(dst);
3829
+ sink.put1(0x48 | ((enc_dst >> 3) & 1) << 2);
3830
+ sink.put1(0x8B);
3831
+ sink.put1(0x05 | ((enc_dst & 7) << 3));
3832
+ emit_reloc(sink, Reloc::X86GOTPCRel4, name, -4);
3833
+ sink.put4(0);
3834
+ // Offset in the relocation above applies to the address of the *GOT entry*, not
3835
+ // the loaded address; so we emit a separate add or sub instruction if needed.
3836
+ if *offset < 0 {
3837
+ assert!(*offset >= -i32::MAX as i64);
3838
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
3839
+ sink.put1(0x81);
3840
+ sink.put1(0xe8 | (enc_dst & 7));
3841
+ sink.put4((-*offset) as u32);
3842
+ } else if *offset > 0 {
3843
+ assert!(*offset <= i32::MAX as i64);
3844
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
3845
+ sink.put1(0x81);
3846
+ sink.put1(0xc0 | (enc_dst & 7));
3847
+ sink.put4(*offset as u32);
3848
+ }
3849
+ } else if distance == &RelocDistance::Near {
3850
+ // If we know the distance to the name is within 2GB (e.g., a module-local function),
3851
+ // we can generate a RIP-relative address, with a relocation.
3852
+ // Generates: lea $name(%rip), $dst
3853
+ let enc_dst = int_reg_enc(dst);
3854
+ sink.put1(0x48 | ((enc_dst >> 3) & 1) << 2);
3855
+ sink.put1(0x8D);
3856
+ sink.put1(0x05 | ((enc_dst & 7) << 3));
3857
+ emit_reloc(sink, Reloc::X86CallPCRel4, name, -4);
3858
+ sink.put4(0);
3859
+ } else {
3860
+ // The full address can be encoded in the register, with a relocation.
3861
+ // Generates: movabsq $name, %dst
3862
+ let enc_dst = int_reg_enc(dst);
3863
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
3864
+ sink.put1(0xB8 | (enc_dst & 7));
3865
+ emit_reloc(sink, Reloc::Abs8, name, *offset);
3866
+ sink.put8(0);
3867
+ }
3868
+ }
3869
+
3870
+ Inst::LockCmpxchg {
3871
+ ty,
3872
+ replacement,
3873
+ expected,
3874
+ mem,
3875
+ dst_old,
3876
+ } => {
3877
+ let replacement = allocs.next(*replacement);
3878
+ let expected = allocs.next(*expected);
3879
+ let dst_old = allocs.next(dst_old.to_reg());
3880
+ let mem = mem.with_allocs(allocs);
3881
+
3882
+ debug_assert_eq!(expected, regs::rax());
3883
+ debug_assert_eq!(dst_old, regs::rax());
3884
+
3885
+ // lock cmpxchg{b,w,l,q} %replacement, (mem)
3886
+ // Note that 0xF0 is the Lock prefix.
3887
+ let (prefix, opcodes) = match *ty {
3888
+ types::I8 => (LegacyPrefixes::_F0, 0x0FB0),
3889
+ types::I16 => (LegacyPrefixes::_66F0, 0x0FB1),
3890
+ types::I32 => (LegacyPrefixes::_F0, 0x0FB1),
3891
+ types::I64 => (LegacyPrefixes::_F0, 0x0FB1),
3892
+ _ => unreachable!(),
3893
+ };
3894
+ let rex = RexFlags::from((OperandSize::from_ty(*ty), replacement));
3895
+ let amode = mem.finalize(state, sink);
3896
+ emit_std_reg_mem(sink, prefix, opcodes, 2, replacement, &amode, rex, 0);
3897
+ }
3898
+
3899
+ Inst::AtomicRmwSeq {
3900
+ ty,
3901
+ op,
3902
+ mem,
3903
+ operand,
3904
+ temp,
3905
+ dst_old,
3906
+ } => {
3907
+ let operand = allocs.next(*operand);
3908
+ let temp = allocs.next_writable(*temp);
3909
+ let dst_old = allocs.next_writable(*dst_old);
3910
+ debug_assert_eq!(dst_old.to_reg(), regs::rax());
3911
+ let mem = mem.finalize(state, sink).with_allocs(allocs);
3912
+
3913
+ // Emit this:
3914
+ // mov{zbq,zwq,zlq,q} (%r_address), %rax // rax = old value
3915
+ // again:
3916
+ // movq %rax, %r_temp // rax = old value, r_temp = old value
3917
+ // `op`q %r_operand, %r_temp // rax = old value, r_temp = new value
3918
+ // lock cmpxchg{b,w,l,q} %r_temp, (%r_address) // try to store new value
3919
+ // jnz again // If this is taken, rax will have a "revised" old value
3920
+ //
3921
+ // Operand conventions: IN: %r_address, %r_operand OUT: %rax (old
3922
+ // value), %r_temp (trashed), %rflags (trashed)
3923
+ //
3924
+ // In the case where the operation is 'xchg', the "`op`q"
3925
+ // instruction is instead: movq %r_operand,
3926
+ // %r_temp so that we simply write in the destination, the "2nd
3927
+ // arg for `op`".
3928
+ //
3929
+ // TODO: this sequence can be significantly improved (e.g., to `lock
3930
+ // <op>`) when it is known that `dst_old` is not used later, see
3931
+ // https://github.com/bytecodealliance/wasmtime/issues/2153.
3932
+ let again_label = sink.get_label();
3933
+
3934
+ // mov{zbq,zwq,zlq,q} (%r_address), %rax
3935
+ // No need to call `add_trap` here, since the `i1` emit will do that.
3936
+ let i1 = Inst::load(*ty, mem.clone(), dst_old, ExtKind::ZeroExtend);
3937
+ i1.emit(&[], sink, info, state);
3938
+
3939
+ // again:
3940
+ sink.bind_label(again_label, state.ctrl_plane_mut());
3941
+
3942
+ // movq %rax, %r_temp
3943
+ let i2 = Inst::mov_r_r(OperandSize::Size64, dst_old.to_reg(), temp);
3944
+ i2.emit(&[], sink, info, state);
3945
+
3946
+ let operand_rmi = RegMemImm::reg(operand);
3947
+ use inst_common::MachAtomicRmwOp as RmwOp;
3948
+ match op {
3949
+ RmwOp::Xchg => {
3950
+ // movq %r_operand, %r_temp
3951
+ let i3 = Inst::mov_r_r(OperandSize::Size64, operand, temp);
3952
+ i3.emit(&[], sink, info, state);
3953
+ }
3954
+ RmwOp::Nand => {
3955
+ // andq %r_operand, %r_temp
3956
+ let i3 =
3957
+ Inst::alu_rmi_r(OperandSize::Size64, AluRmiROpcode::And, operand_rmi, temp);
3958
+ i3.emit(&[], sink, info, state);
3959
+
3960
+ // notq %r_temp
3961
+ let i4 = Inst::not(OperandSize::Size64, temp);
3962
+ i4.emit(&[], sink, info, state);
3963
+ }
3964
+ RmwOp::Umin | RmwOp::Umax | RmwOp::Smin | RmwOp::Smax => {
3965
+ // cmp %r_temp, %r_operand
3966
+ let i3 = Inst::cmp_rmi_r(
3967
+ OperandSize::from_ty(*ty),
3968
+ RegMemImm::reg(temp.to_reg()),
3969
+ operand,
3970
+ );
3971
+ i3.emit(&[], sink, info, state);
3972
+
3973
+ // cmovcc %r_operand, %r_temp
3974
+ let cc = match op {
3975
+ RmwOp::Umin => CC::BE,
3976
+ RmwOp::Umax => CC::NB,
3977
+ RmwOp::Smin => CC::LE,
3978
+ RmwOp::Smax => CC::NL,
3979
+ _ => unreachable!(),
3980
+ };
3981
+ let i4 = Inst::cmove(OperandSize::Size64, cc, RegMem::reg(operand), temp);
3982
+ i4.emit(&[], sink, info, state);
3983
+ }
3984
+ _ => {
3985
+ // opq %r_operand, %r_temp
3986
+ let alu_op = match op {
3987
+ RmwOp::Add => AluRmiROpcode::Add,
3988
+ RmwOp::Sub => AluRmiROpcode::Sub,
3989
+ RmwOp::And => AluRmiROpcode::And,
3990
+ RmwOp::Or => AluRmiROpcode::Or,
3991
+ RmwOp::Xor => AluRmiROpcode::Xor,
3992
+ RmwOp::Xchg
3993
+ | RmwOp::Nand
3994
+ | RmwOp::Umin
3995
+ | RmwOp::Umax
3996
+ | RmwOp::Smin
3997
+ | RmwOp::Smax => unreachable!(),
3998
+ };
3999
+ let i3 = Inst::alu_rmi_r(OperandSize::Size64, alu_op, operand_rmi, temp);
4000
+ i3.emit(&[], sink, info, state);
4001
+ }
4002
+ }
4003
+
4004
+ // lock cmpxchg{b,w,l,q} %r_temp, (%r_address)
4005
+ // No need to call `add_trap` here, since the `i4` emit will do that.
4006
+ let i4 = Inst::LockCmpxchg {
4007
+ ty: *ty,
4008
+ replacement: temp.to_reg(),
4009
+ expected: dst_old.to_reg(),
4010
+ mem: mem.into(),
4011
+ dst_old,
4012
+ };
4013
+ i4.emit(&[], sink, info, state);
4014
+
4015
+ // jnz again
4016
+ one_way_jmp(sink, CC::NZ, again_label);
4017
+ }
4018
+
4019
+ Inst::Fence { kind } => {
4020
+ sink.put1(0x0F);
4021
+ sink.put1(0xAE);
4022
+ match kind {
4023
+ FenceKind::MFence => sink.put1(0xF0), // mfence = 0F AE F0
4024
+ FenceKind::LFence => sink.put1(0xE8), // lfence = 0F AE E8
4025
+ FenceKind::SFence => sink.put1(0xF8), // sfence = 0F AE F8
4026
+ }
4027
+ }
4028
+
4029
+ Inst::Hlt => {
4030
+ sink.put1(0xcc);
4031
+ }
4032
+
4033
+ Inst::Ud2 { trap_code } => {
4034
+ sink.add_trap(*trap_code);
4035
+ if let Some(s) = state.take_stack_map() {
4036
+ sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
4037
+ }
4038
+ sink.put_data(Inst::TRAP_OPCODE);
4039
+ }
4040
+
4041
+ Inst::VirtualSPOffsetAdj { offset } => {
4042
+ state.adjust_virtual_sp_offset(*offset);
4043
+ }
4044
+
4045
+ Inst::Nop { len } => {
4046
+ // These encodings can all be found in Intel's architecture manual, at the NOP
4047
+ // instruction description.
4048
+ let mut len = *len;
4049
+ while len != 0 {
4050
+ let emitted = u8::min(len, 9);
4051
+ match emitted {
4052
+ 0 => {}
4053
+ 1 => sink.put1(0x90), // NOP
4054
+ 2 => {
4055
+ // 66 NOP
4056
+ sink.put1(0x66);
4057
+ sink.put1(0x90);
4058
+ }
4059
+ 3 => {
4060
+ // NOP [EAX]
4061
+ sink.put1(0x0F);
4062
+ sink.put1(0x1F);
4063
+ sink.put1(0x00);
4064
+ }
4065
+ 4 => {
4066
+ // NOP 0(EAX), with 0 a 1-byte immediate.
4067
+ sink.put1(0x0F);
4068
+ sink.put1(0x1F);
4069
+ sink.put1(0x40);
4070
+ sink.put1(0x00);
4071
+ }
4072
+ 5 => {
4073
+ // NOP [EAX, EAX, 1]
4074
+ sink.put1(0x0F);
4075
+ sink.put1(0x1F);
4076
+ sink.put1(0x44);
4077
+ sink.put1(0x00);
4078
+ sink.put1(0x00);
4079
+ }
4080
+ 6 => {
4081
+ // 66 NOP [EAX, EAX, 1]
4082
+ sink.put1(0x66);
4083
+ sink.put1(0x0F);
4084
+ sink.put1(0x1F);
4085
+ sink.put1(0x44);
4086
+ sink.put1(0x00);
4087
+ sink.put1(0x00);
4088
+ }
4089
+ 7 => {
4090
+ // NOP 0[EAX], but 0 is a 4 bytes immediate.
4091
+ sink.put1(0x0F);
4092
+ sink.put1(0x1F);
4093
+ sink.put1(0x80);
4094
+ sink.put1(0x00);
4095
+ sink.put1(0x00);
4096
+ sink.put1(0x00);
4097
+ sink.put1(0x00);
4098
+ }
4099
+ 8 => {
4100
+ // NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
4101
+ sink.put1(0x0F);
4102
+ sink.put1(0x1F);
4103
+ sink.put1(0x84);
4104
+ sink.put1(0x00);
4105
+ sink.put1(0x00);
4106
+ sink.put1(0x00);
4107
+ sink.put1(0x00);
4108
+ sink.put1(0x00);
4109
+ }
4110
+ 9 => {
4111
+ // 66 NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
4112
+ sink.put1(0x66);
4113
+ sink.put1(0x0F);
4114
+ sink.put1(0x1F);
4115
+ sink.put1(0x84);
4116
+ sink.put1(0x00);
4117
+ sink.put1(0x00);
4118
+ sink.put1(0x00);
4119
+ sink.put1(0x00);
4120
+ sink.put1(0x00);
4121
+ }
4122
+ _ => unreachable!(),
4123
+ }
4124
+ len -= emitted;
4125
+ }
4126
+ }
4127
+
4128
+ Inst::ElfTlsGetAddr { ref symbol, dst } => {
4129
+ let dst = allocs.next(dst.to_reg().to_reg());
4130
+ debug_assert_eq!(dst, regs::rax());
4131
+
4132
+ // N.B.: Must be exactly this byte sequence; the linker requires it,
4133
+ // because it must know how to rewrite the bytes.
4134
+
4135
+ // data16 lea gv@tlsgd(%rip),%rdi
4136
+ sink.put1(0x66); // data16
4137
+ sink.put1(0b01001000); // REX.W
4138
+ sink.put1(0x8d); // LEA
4139
+ sink.put1(0x3d); // ModRM byte
4140
+ emit_reloc(sink, Reloc::ElfX86_64TlsGd, symbol, -4);
4141
+ sink.put4(0); // offset
4142
+
4143
+ // data16 data16 callq __tls_get_addr-4
4144
+ sink.put1(0x66); // data16
4145
+ sink.put1(0x66); // data16
4146
+ sink.put1(0b01001000); // REX.W
4147
+ sink.put1(0xe8); // CALL
4148
+ emit_reloc(
4149
+ sink,
4150
+ Reloc::X86CallPLTRel4,
4151
+ &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
4152
+ -4,
4153
+ );
4154
+ sink.put4(0); // offset
4155
+ }
4156
+
4157
+ Inst::MachOTlsGetAddr { ref symbol, dst } => {
4158
+ let dst = allocs.next(dst.to_reg().to_reg());
4159
+ debug_assert_eq!(dst, regs::rax());
4160
+
4161
+ // movq gv@tlv(%rip), %rdi
4162
+ sink.put1(0x48); // REX.w
4163
+ sink.put1(0x8b); // MOV
4164
+ sink.put1(0x3d); // ModRM byte
4165
+ emit_reloc(sink, Reloc::MachOX86_64Tlv, symbol, -4);
4166
+ sink.put4(0); // offset
4167
+
4168
+ // callq *(%rdi)
4169
+ sink.put1(0xff);
4170
+ sink.put1(0x17);
4171
+ }
4172
+
4173
+ Inst::CoffTlsGetAddr {
4174
+ ref symbol,
4175
+ dst,
4176
+ tmp,
4177
+ } => {
4178
+ let dst = allocs.next(dst.to_reg().to_reg());
4179
+ debug_assert_eq!(dst, regs::rax());
4180
+
4181
+ // tmp is used below directly as %rcx
4182
+ let tmp = allocs.next(tmp.to_reg().to_reg());
4183
+ debug_assert_eq!(tmp, regs::rcx());
4184
+
4185
+ // See: https://gcc.godbolt.org/z/M8or9x6ss
4186
+ // And: https://github.com/bjorn3/rustc_codegen_cranelift/issues/388#issuecomment-532930282
4187
+
4188
+ // Emit the following sequence
4189
+ // movl (%rip), %eax ; IMAGE_REL_AMD64_REL32 _tls_index
4190
+ // movq %gs:88, %rcx
4191
+ // movq (%rcx,%rax,8), %rax
4192
+ // leaq (%rax), %rax ; Reloc: IMAGE_REL_AMD64_SECREL symbol
4193
+
4194
+ // Load TLS index for current thread
4195
+ // movl (%rip), %eax
4196
+ sink.put1(0x8b); // mov
4197
+ sink.put1(0x05);
4198
+ emit_reloc(
4199
+ sink,
4200
+ Reloc::X86PCRel4,
4201
+ &ExternalName::KnownSymbol(KnownSymbol::CoffTlsIndex),
4202
+ -4,
4203
+ );
4204
+ sink.put4(0); // offset
4205
+
4206
+ // movq %gs:88, %rcx
4207
+ // Load the TLS Storage Array pointer
4208
+ // The gs segment register refers to the base address of the TEB on x64.
4209
+ // 0x58 is the offset in the TEB for the ThreadLocalStoragePointer member on x64:
4210
+ sink.put_data(&[
4211
+ 0x65, 0x48, // REX.W
4212
+ 0x8b, // MOV
4213
+ 0x0c, 0x25, 0x58, // 0x58 - ThreadLocalStoragePointer offset
4214
+ 0x00, 0x00, 0x00,
4215
+ ]);
4216
+
4217
+ // movq (%rcx,%rax,8), %rax
4218
+ // Load the actual TLS entry for this thread.
4219
+ // Computes ThreadLocalStoragePointer + _tls_index*8
4220
+ sink.put_data(&[0x48, 0x8b, 0x04, 0xc1]);
4221
+
4222
+ // leaq (%rax), %rax
4223
+ sink.put1(0x48);
4224
+ sink.put1(0x8d);
4225
+ sink.put1(0x80);
4226
+ emit_reloc(sink, Reloc::X86SecRel, symbol, 0);
4227
+ sink.put4(0); // offset
4228
+ }
4229
+
4230
+ Inst::Unwind { ref inst } => {
4231
+ sink.add_unwind(inst.clone());
4232
+ }
4233
+
4234
+ Inst::DummyUse { .. } => {
4235
+ // Nothing.
4236
+ }
4237
+ }
4238
+
4239
+ state.clear_post_insn();
4240
+ }
4241
+
4242
+ /// Emit the common sequence used for both direct and indirect tail calls:
4243
+ ///
4244
+ /// * Copy the new frame's stack arguments over the top of our current frame.
4245
+ ///
4246
+ /// * Restore the old frame pointer.
4247
+ ///
4248
+ /// * Initialize the tail callee's stack pointer (simultaneously deallocating
4249
+ /// the temporary stack space we allocated when creating the new frame's stack
4250
+ /// arguments).
4251
+ ///
4252
+ /// * Move the return address into its stack slot.
4253
+ fn emit_return_call_common_sequence(
4254
+ allocs: &mut AllocationConsumer<'_>,
4255
+ sink: &mut MachBuffer<Inst>,
4256
+ info: &EmitInfo,
4257
+ state: &mut EmitState,
4258
+ new_stack_arg_size: u32,
4259
+ old_stack_arg_size: u32,
4260
+ ret_addr: Option<Gpr>,
4261
+ fp: Gpr,
4262
+ tmp: WritableGpr,
4263
+ uses: &CallArgList,
4264
+ ) {
4265
+ assert!(
4266
+ info.flags.preserve_frame_pointers(),
4267
+ "frame pointers aren't fundamentally required for tail calls, \
4268
+ but the current implementation relies on them being present"
4269
+ );
4270
+
4271
+ for u in uses {
4272
+ let _ = allocs.next(u.vreg);
4273
+ }
4274
+
4275
+ let ret_addr = ret_addr.map(|r| Gpr::new(allocs.next(*r)).unwrap());
4276
+
4277
+ let fp = allocs.next(*fp);
4278
+
4279
+ let tmp = allocs.next(tmp.to_reg().to_reg());
4280
+ let tmp = Gpr::new(tmp).unwrap();
4281
+ let tmp_w = WritableGpr::from_reg(tmp);
4282
+
4283
+ // Copy the new frame (which is `frame_size` bytes above the SP)
4284
+ // onto our current frame, using only volatile, non-argument
4285
+ // registers.
4286
+ //
4287
+ //
4288
+ // The current stack layout is the following:
4289
+ //
4290
+ // | ... |
4291
+ // +---------------------+
4292
+ // | ... |
4293
+ // | stack arguments |
4294
+ // | ... |
4295
+ // current | return address |
4296
+ // frame | old FP | <-- FP
4297
+ // | ... |
4298
+ // | old stack slots |
4299
+ // | ... |
4300
+ // +---------------------+
4301
+ // | ... |
4302
+ // new | new stack arguments |
4303
+ // frame | ... | <-- SP
4304
+ // +---------------------+
4305
+ //
4306
+ // We need to restore the old FP, copy the new stack arguments over the old
4307
+ // stack arguments, write the return address into the correct slot just
4308
+ // after the new stack arguments, adjust SP to point to the new return
4309
+ // address, and then jump to the callee (which will push the old FP again).
4310
+
4311
+ // Restore the old FP into `rbp`.
4312
+ Inst::Mov64MR {
4313
+ src: SyntheticAmode::Real(Amode::ImmReg {
4314
+ simm32: 0,
4315
+ base: fp,
4316
+ flags: MemFlags::trusted(),
4317
+ }),
4318
+ dst: Writable::from_reg(Gpr::new(regs::rbp()).unwrap()),
4319
+ }
4320
+ .emit(&[], sink, info, state);
4321
+
4322
+ // The new lowest address (top of stack) -- relative to FP -- for
4323
+ // our tail callee. We compute this now so that we can move our
4324
+ // stack arguments into place.
4325
+ let callee_sp_relative_to_fp = i64::from(old_stack_arg_size) - i64::from(new_stack_arg_size);
4326
+
4327
+ // Copy over each word, using `tmp` as a temporary register.
4328
+ //
4329
+ // Note that we have to do this from stack slots with the highest
4330
+ // address to lowest address because in the case of when the tail
4331
+ // callee has more stack arguments than we do, we might otherwise
4332
+ // overwrite some of our stack arguments before they've been copied
4333
+ // into place.
4334
+ assert_eq!(
4335
+ new_stack_arg_size % 8,
4336
+ 0,
4337
+ "stack argument space sizes should always be 8-byte aligned"
4338
+ );
4339
+ for i in (0..new_stack_arg_size / 8).rev() {
4340
+ Inst::Mov64MR {
4341
+ src: SyntheticAmode::Real(Amode::ImmReg {
4342
+ simm32: (i * 8).try_into().unwrap(),
4343
+ base: regs::rsp(),
4344
+ flags: MemFlags::trusted(),
4345
+ }),
4346
+ dst: tmp_w,
4347
+ }
4348
+ .emit(&[], sink, info, state);
4349
+ Inst::MovRM {
4350
+ size: OperandSize::Size64,
4351
+ src: tmp,
4352
+ dst: SyntheticAmode::Real(Amode::ImmReg {
4353
+ // Add 2 because we need to skip over the old FP and the
4354
+ // return address.
4355
+ simm32: (callee_sp_relative_to_fp + i64::from((i + 2) * 8))
4356
+ .try_into()
4357
+ .unwrap(),
4358
+ base: fp,
4359
+ flags: MemFlags::trusted(),
4360
+ }),
4361
+ }
4362
+ .emit(&[], sink, info, state);
4363
+ }
4364
+
4365
+ // Initialize SP for the tail callee, deallocating the temporary
4366
+ // stack arguments space at the same time.
4367
+ Inst::LoadEffectiveAddress {
4368
+ size: OperandSize::Size64,
4369
+ addr: SyntheticAmode::Real(Amode::ImmReg {
4370
+ // NB: We add a word to `callee_sp_relative_to_fp` here because the
4371
+ // callee will push FP, not us.
4372
+ simm32: callee_sp_relative_to_fp.wrapping_add(8).try_into().unwrap(),
4373
+ base: fp,
4374
+ flags: MemFlags::trusted(),
4375
+ }),
4376
+ dst: Writable::from_reg(Gpr::new(regs::rsp()).unwrap()),
4377
+ }
4378
+ .emit(&[], sink, info, state);
4379
+
4380
+ state.adjust_virtual_sp_offset(-i64::from(new_stack_arg_size));
4381
+
4382
+ // Write the return address into the correct stack slot.
4383
+ if let Some(ret_addr) = ret_addr {
4384
+ Inst::MovRM {
4385
+ size: OperandSize::Size64,
4386
+ src: ret_addr,
4387
+ dst: SyntheticAmode::Real(Amode::ImmReg {
4388
+ simm32: 0,
4389
+ base: regs::rsp(),
4390
+ flags: MemFlags::trusted(),
4391
+ }),
4392
+ }
4393
+ .emit(&[], sink, info, state);
4394
+ }
4395
+ }