wasmtime 10.0.0 → 11.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +146 -140
- data/ext/Cargo.toml +6 -6
- data/ext/cargo-vendor/addr2line-0.21.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/aho-corasick-1.0.4/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/aho-corasick-1.0.4/src/ahocorasick.rs +2789 -0
- data/ext/cargo-vendor/aho-corasick-1.0.4/src/dfa.rs +816 -0
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- data/ext/cargo-vendor/aho-corasick-1.0.4/src/nfa/contiguous.rs +1141 -0
- data/ext/cargo-vendor/aho-corasick-1.0.4/src/nfa/noncontiguous.rs +1710 -0
- data/ext/cargo-vendor/anyhow-1.0.75/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/anyhow-1.0.75/build.rs +131 -0
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- data/ext/cargo-vendor/anyhow-1.0.75/src/context.rs +193 -0
- data/ext/cargo-vendor/anyhow-1.0.75/src/error.rs +996 -0
- data/ext/cargo-vendor/anyhow-1.0.75/src/kind.rs +119 -0
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- data/ext/cargo-vendor/async-trait-0.1.73/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/async-trait-0.1.73/src/expand.rs +484 -0
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- data/ext/cargo-vendor/async-trait-0.1.73/tests/ui/consider-restricting.stderr +35 -0
- data/ext/cargo-vendor/async-trait-0.1.73/tests/ui/send-not-implemented.stderr +49 -0
- data/ext/cargo-vendor/backtrace-0.3.69/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/backtrace-0.3.69/build.rs +49 -0
- data/ext/cargo-vendor/backtrace-0.3.69/src/print/fuchsia.rs +441 -0
- data/ext/cargo-vendor/backtrace-0.3.69/src/print.rs +320 -0
- data/ext/cargo-vendor/backtrace-0.3.69/src/symbolize/gimli/parse_running_mmaps_unix.rs +295 -0
- data/ext/cargo-vendor/backtrace-0.3.69/src/symbolize/mod.rs +485 -0
- data/ext/cargo-vendor/backtrace-0.3.69/src/windows.rs +693 -0
- data/ext/cargo-vendor/cc-1.0.83/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cc-1.0.83/Cargo.toml +43 -0
- data/ext/cargo-vendor/cc-1.0.83/src/lib.rs +4024 -0
- data/ext/cargo-vendor/cc-1.0.83/tests/test.rs +477 -0
- data/ext/cargo-vendor/cranelift-bforest-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.98.1/Cargo.toml +31 -0
- data/ext/cargo-vendor/cranelift-codegen-0.98.1/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/isa/x64/inst/emit.rs +4298 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/isa/x64/inst.isle +5079 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/isle_prelude.rs +894 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/machinst/abi.rs +2605 -0
- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/machinst/buffer.rs +2255 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/machinst/reg.rs +556 -0
- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/machinst/vcode.rs +1580 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/prelude.isle +594 -0
- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/prelude_lower.isle +1024 -0
- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/settings.rs +601 -0
- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/timing.rs +271 -0
- data/ext/cargo-vendor/cranelift-codegen-0.98.1/src/unionfind.rs +74 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.98.1/Cargo.toml +23 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.98.1/src/cdsl/settings.rs +429 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.98.1/src/isa/x86.rs +409 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.98.1/src/shared/instructions.rs +3847 -0
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- data/ext/cargo-vendor/cranelift-codegen-shared-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.98.1/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.98.1/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.98.1/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-frontend-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.98.1/Cargo.toml +53 -0
- data/ext/cargo-vendor/cranelift-isle-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.98.1/Cargo.toml +37 -0
- data/ext/cargo-vendor/cranelift-native-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.98.1/Cargo.toml +38 -0
- data/ext/cargo-vendor/cranelift-native-0.98.1/src/lib.rs +204 -0
- data/ext/cargo-vendor/cranelift-wasm-0.98.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.98.1/Cargo.toml +85 -0
- data/ext/cargo-vendor/cranelift-wasm-0.98.1/src/code_translator.rs +3544 -0
- data/ext/cargo-vendor/cranelift-wasm-0.98.1/src/environ/spec.rs +852 -0
- data/ext/cargo-vendor/gimli-0.28.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/gimli-0.28.0/CHANGELOG.md +987 -0
- data/ext/cargo-vendor/gimli-0.28.0/Cargo.toml +109 -0
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- data/ext/cargo-vendor/gimli-0.28.0/src/arch.rs +768 -0
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- data/ext/cargo-vendor/gimli-0.28.0/src/constants.rs +1435 -0
- data/ext/cargo-vendor/gimli-0.28.0/src/endianity.rs +256 -0
- data/ext/cargo-vendor/gimli-0.28.0/src/leb128.rs +612 -0
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- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/string6.wat.err +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/string7.wat +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/string7.wat.err +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/string8.wat +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/string8.wat.err +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/string9.wat +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/string9.wat.err +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/unbalanced.wat +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail/unbalanced.wat.err +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/parse-fail.rs +0 -0
- /data/ext/cargo-vendor/{wast-62.0.1 → wast-63.0.0}/tests/recursive.rs +0 -0
- /data/ext/cargo-vendor/{wat-1.0.69 → wat-1.0.70}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wat-1.0.69 → wat-1.0.70}/README.md +0 -0
- /data/ext/cargo-vendor/{wat-1.0.69 → wat-1.0.70}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/README.md +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/src/borrow.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/src/error.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/src/guest_type.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/src/region.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-10.0.0 → wiggle-11.0.0}/src/wasmtime.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/README.md +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/codegen_settings.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/config.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/funcs.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/lifetimes.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/module_trait.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/names.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/types/error.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/types/flags.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/types/handle.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/types/mod.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/types/record.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/types/variant.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-10.0.0 → wiggle-generate-11.0.0}/src/wasmtime.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-macro-10.0.0 → wiggle-macro-11.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-macro-10.0.0 → wiggle-macro-11.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/build.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/src/abi/local.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/src/frame/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/src/isa/aarch64/address.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/src/isa/aarch64/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/src/isa/aarch64/regs.rs +0 -0
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- /data/ext/cargo-vendor/{winch-codegen-0.8.0 → winch-codegen-0.9.0}/src/regset.rs +0 -0
- /data/ext/cargo-vendor/{windows-targets-0.48.1 → windows-targets-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows-targets-0.48.1 → windows-targets-0.48.5}/license-mit +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_gnullvm-0.48.0 → windows_aarch64_gnullvm-0.48.5}/build.rs +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_gnullvm-0.48.0 → windows_aarch64_gnullvm-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_gnullvm-0.48.0 → windows_aarch64_gnullvm-0.48.5}/license-mit +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_gnullvm-0.48.0 → windows_aarch64_gnullvm-0.48.5}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_msvc-0.48.0 → windows_aarch64_msvc-0.48.5}/build.rs +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_msvc-0.48.0 → windows_aarch64_msvc-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_msvc-0.48.0 → windows_aarch64_msvc-0.48.5}/license-mit +0 -0
- /data/ext/cargo-vendor/{windows_aarch64_msvc-0.48.0 → windows_aarch64_msvc-0.48.5}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{windows_i686_gnu-0.48.0 → windows_i686_gnu-0.48.5}/build.rs +0 -0
- /data/ext/cargo-vendor/{windows_i686_gnu-0.48.0 → windows_i686_gnu-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows_i686_gnu-0.48.0 → windows_i686_gnu-0.48.5}/license-mit +0 -0
- /data/ext/cargo-vendor/{windows_i686_gnu-0.48.0 → windows_i686_gnu-0.48.5}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{windows_i686_msvc-0.48.0 → windows_i686_msvc-0.48.5}/build.rs +0 -0
- /data/ext/cargo-vendor/{windows_i686_msvc-0.48.0 → windows_i686_msvc-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows_i686_msvc-0.48.0 → windows_i686_msvc-0.48.5}/license-mit +0 -0
- /data/ext/cargo-vendor/{windows_i686_msvc-0.48.0 → windows_i686_msvc-0.48.5}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnu-0.48.0 → windows_x86_64_gnu-0.48.5}/build.rs +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnu-0.48.0 → windows_x86_64_gnu-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnu-0.48.0 → windows_x86_64_gnu-0.48.5}/license-mit +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnu-0.48.0 → windows_x86_64_gnu-0.48.5}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnullvm-0.48.0 → windows_x86_64_gnullvm-0.48.5}/build.rs +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnullvm-0.48.0 → windows_x86_64_gnullvm-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnullvm-0.48.0 → windows_x86_64_gnullvm-0.48.5}/license-mit +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_gnullvm-0.48.0 → windows_x86_64_gnullvm-0.48.5}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_msvc-0.48.0 → windows_x86_64_msvc-0.48.5}/build.rs +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_msvc-0.48.0 → windows_x86_64_msvc-0.48.5}/license-apache-2.0 +0 -0
- /data/ext/cargo-vendor/{windows_x86_64_msvc-0.48.0 → windows_x86_64_msvc-0.48.5}/license-mit +0 -0
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//! ISLE integration glue code for s390x lowering.
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// Pull in the ISLE generated code.
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pub mod generated_code;
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use crate::ir::ExternalName;
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// Types that the generated ISLE code uses via `use super::*`.
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use crate::isa::s390x::abi::{S390xMachineDeps, REG_SAVE_AREA_SIZE};
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use crate::isa::s390x::inst::{
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gpr, stack_reg, writable_gpr, zero_reg, CallIndInfo, CallInfo, Cond, Inst as MInst, LaneOrder,
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MemArg, MemArgPair, RegPair, SymbolReloc, UImm12, UImm16Shifted, UImm32Shifted,
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WritableRegPair,
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};
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use crate::isa::s390x::S390xBackend;
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use crate::machinst::isle::*;
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use crate::machinst::{MachLabel, Reg};
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use crate::{
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ir::{
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condcodes::*, immediates::*, types::*, ArgumentPurpose, AtomicRmwOp, BlockCall, Endianness,
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Inst, InstructionData, KnownSymbol, LibCall, MemFlags, Opcode, TrapCode, Value, ValueList,
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},
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isa::unwind::UnwindInst,
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isa::CallConv,
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machinst::abi::ABIMachineSpec,
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machinst::{
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ArgPair, CallArgList, CallArgPair, CallRetList, CallRetPair, InstOutput, Lower, MachInst,
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VCodeConstant, VCodeConstantData,
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},
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};
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use crate::{isle_common_prelude_methods, isle_lower_prelude_methods};
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use regalloc2::PReg;
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use smallvec::smallvec;
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use std::boxed::Box;
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use std::cell::Cell;
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use std::convert::TryFrom;
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use std::vec::Vec;
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/// Information describing a library call to be emitted.
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pub struct LibCallInfo {
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libcall: LibCall,
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uses: CallArgList,
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defs: CallRetList,
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tls_symbol: Option<SymbolReloc>,
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}
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type BoxCallInfo = Box<CallInfo>;
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type BoxCallIndInfo = Box<CallIndInfo>;
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type VecMachLabel = Vec<MachLabel>;
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type BoxExternalName = Box<ExternalName>;
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type BoxSymbolReloc = Box<SymbolReloc>;
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type VecMInst = Vec<MInst>;
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type VecMInstBuilder = Cell<Vec<MInst>>;
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type VecArgPair = Vec<ArgPair>;
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type CallArgListBuilder = Cell<CallArgList>;
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/// The main entry point for lowering with ISLE.
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pub(crate) fn lower(
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backend: &S390xBackend,
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inst: Inst,
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) -> Option<InstOutput> {
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generated_code::constructor_lower(&mut isle_ctx, inst)
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}
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/// The main entry point for branch lowering with ISLE.
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pub(crate) fn lower_branch(
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lower_ctx: &mut Lower<MInst>,
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backend: &S390xBackend,
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branch: Inst,
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targets: &[MachLabel],
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) -> Option<()> {
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// TODO: reuse the ISLE context across lowerings so we can reuse its
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let mut isle_ctx = IsleContext { lower_ctx, backend };
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generated_code::constructor_lower_branch(&mut isle_ctx, branch, &targets.to_vec())
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}
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impl generated_code::Context for IsleContext<'_, '_, MInst, S390xBackend> {
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isle_lower_prelude_methods!();
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#[inline]
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fn args_builder_new(&mut self) -> CallArgListBuilder {
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Cell::new(CallArgList::new())
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}
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#[inline]
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fn args_builder_push(
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&mut self,
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builder: &CallArgListBuilder,
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) -> Unit {
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args.push(CallArgPair {
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vreg,
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});
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builder.set(args);
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}
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#[inline]
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fn args_builder_finish(&mut self, builder: &CallArgListBuilder) -> CallArgList {
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builder.take()
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}
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fn defs_init(&mut self, abi: Sig) -> CallRetList {
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// Allocate writable registers for all retval regs, except for StructRet args.
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let mut defs = smallvec![];
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for i in 0..self.lower_ctx.sigs().num_rets(abi) {
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if let &ABIArg::Slots {
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ref slots, purpose, ..
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} = &self.lower_ctx.sigs().get_ret(abi, i)
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{
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if purpose == ArgumentPurpose::StructReturn {
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continue;
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}
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for slot in slots {
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match slot {
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&ABIArgSlot::Reg { reg, ty, .. } => {
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let value_regs = self.lower_ctx.alloc_tmp(ty);
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defs.push(CallRetPair {
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preg: reg.into(),
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});
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}
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_ => {}
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}
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}
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defs
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}
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fn defs_lookup(&mut self, defs: &CallRetList, reg: RealReg) -> Reg {
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for def in defs {
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return def.vreg.to_reg();
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}
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}
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unreachable!()
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}
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fn abi_sig(&mut self, sig_ref: SigRef) -> Sig {
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self.lower_ctx.sigs().abi_sig_for_sig_ref(sig_ref)
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}
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fn abi_first_ret(&mut self, sig_ref: SigRef, abi: Sig) -> usize {
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// any StructReturn that might have been added to Sig.
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self.lower_ctx.sigs().num_rets(abi) - sig.returns.len()
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}
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fn abi_lane_order(&mut self, abi: Sig) -> LaneOrder {
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lane_order_for_call_conv(self.lower_ctx.sigs()[abi].call_conv())
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}
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fn abi_accumulate_outgoing_args_size(&mut self, abi: Sig) -> Unit {
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let off = self.lower_ctx.sigs()[abi].sized_stack_arg_space()
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+ self.lower_ctx.sigs()[abi].sized_stack_ret_space();
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self.lower_ctx
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.abi_mut()
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.accumulate_outgoing_args_size(off as u32);
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}
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fn abi_call_info(
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&mut self,
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abi: Sig,
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name: ExternalName,
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uses: &CallArgList,
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defs: &CallRetList,
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opcode: &Opcode,
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) -> BoxCallInfo {
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let clobbers = self.lower_ctx.sigs().call_clobbers::<S390xMachineDeps>(abi);
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Box::new(CallInfo {
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dest: name.clone(),
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uses: uses.clone(),
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defs: defs.clone(),
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clobbers,
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opcode: *opcode,
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caller_callconv: self.lower_ctx.abi().call_conv(self.lower_ctx.sigs()),
|
186
|
-
callee_callconv: self.lower_ctx.sigs()[abi].call_conv(),
|
187
|
-
tls_symbol: None,
|
188
|
-
})
|
189
|
-
}
|
190
|
-
|
191
|
-
fn abi_call_ind_info(
|
192
|
-
&mut self,
|
193
|
-
abi: Sig,
|
194
|
-
target: Reg,
|
195
|
-
uses: &CallArgList,
|
196
|
-
defs: &CallRetList,
|
197
|
-
opcode: &Opcode,
|
198
|
-
) -> BoxCallIndInfo {
|
199
|
-
let clobbers = self.lower_ctx.sigs().call_clobbers::<S390xMachineDeps>(abi);
|
200
|
-
Box::new(CallIndInfo {
|
201
|
-
rn: target,
|
202
|
-
uses: uses.clone(),
|
203
|
-
defs: defs.clone(),
|
204
|
-
clobbers,
|
205
|
-
opcode: *opcode,
|
206
|
-
caller_callconv: self.lower_ctx.abi().call_conv(self.lower_ctx.sigs()),
|
207
|
-
callee_callconv: self.lower_ctx.sigs()[abi].call_conv(),
|
208
|
-
})
|
209
|
-
}
|
210
|
-
|
211
|
-
fn lib_call_info_memcpy(&mut self, dst: Reg, src: Reg, len: Reg) -> LibCallInfo {
|
212
|
-
LibCallInfo {
|
213
|
-
libcall: LibCall::Memcpy,
|
214
|
-
uses: smallvec![
|
215
|
-
CallArgPair {
|
216
|
-
vreg: dst,
|
217
|
-
preg: gpr(2),
|
218
|
-
},
|
219
|
-
CallArgPair {
|
220
|
-
vreg: src,
|
221
|
-
preg: gpr(3),
|
222
|
-
},
|
223
|
-
CallArgPair {
|
224
|
-
vreg: len,
|
225
|
-
preg: gpr(4),
|
226
|
-
},
|
227
|
-
],
|
228
|
-
defs: smallvec![],
|
229
|
-
tls_symbol: None,
|
230
|
-
}
|
231
|
-
}
|
232
|
-
|
233
|
-
fn lib_call_info_tls_get_offset(
|
234
|
-
&mut self,
|
235
|
-
tls_offset: WritableReg,
|
236
|
-
got: Reg,
|
237
|
-
got_offset: Reg,
|
238
|
-
tls_symbol: &SymbolReloc,
|
239
|
-
) -> LibCallInfo {
|
240
|
-
LibCallInfo {
|
241
|
-
libcall: LibCall::ElfTlsGetOffset,
|
242
|
-
uses: smallvec![
|
243
|
-
CallArgPair {
|
244
|
-
vreg: got,
|
245
|
-
preg: gpr(12),
|
246
|
-
},
|
247
|
-
CallArgPair {
|
248
|
-
vreg: got_offset,
|
249
|
-
preg: gpr(2),
|
250
|
-
},
|
251
|
-
],
|
252
|
-
defs: smallvec![CallRetPair {
|
253
|
-
vreg: tls_offset,
|
254
|
-
preg: gpr(2),
|
255
|
-
},],
|
256
|
-
tls_symbol: Some(tls_symbol.clone()),
|
257
|
-
}
|
258
|
-
}
|
259
|
-
|
260
|
-
fn lib_accumulate_outgoing_args_size(&mut self, _: &LibCallInfo) -> Unit {
|
261
|
-
// Libcalls only require the register save area.
|
262
|
-
self.lower_ctx
|
263
|
-
.abi_mut()
|
264
|
-
.accumulate_outgoing_args_size(REG_SAVE_AREA_SIZE);
|
265
|
-
}
|
266
|
-
|
267
|
-
fn lib_call_info(&mut self, info: &LibCallInfo) -> BoxCallInfo {
|
268
|
-
let caller_callconv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
269
|
-
let callee_callconv = CallConv::for_libcall(&self.backend.flags, caller_callconv);
|
270
|
-
|
271
|
-
// Clobbers are defined by the calling convention. Remove defs from clobbers.
|
272
|
-
let mut clobbers = S390xMachineDeps::get_regs_clobbered_by_call(callee_callconv);
|
273
|
-
for reg in &info.defs {
|
274
|
-
clobbers.remove(PReg::from(reg.preg.to_real_reg().unwrap()));
|
275
|
-
}
|
276
|
-
|
277
|
-
Box::new(CallInfo {
|
278
|
-
dest: ExternalName::LibCall(info.libcall),
|
279
|
-
uses: info.uses.clone(),
|
280
|
-
defs: info.defs.clone(),
|
281
|
-
clobbers,
|
282
|
-
opcode: Opcode::Call,
|
283
|
-
caller_callconv,
|
284
|
-
callee_callconv,
|
285
|
-
tls_symbol: info.tls_symbol.clone(),
|
286
|
-
})
|
287
|
-
}
|
288
|
-
|
289
|
-
#[inline]
|
290
|
-
fn box_symbol_reloc(&mut self, symbol_reloc: &SymbolReloc) -> BoxSymbolReloc {
|
291
|
-
Box::new(symbol_reloc.clone())
|
292
|
-
}
|
293
|
-
|
294
|
-
#[inline]
|
295
|
-
fn mie2_enabled(&mut self, _: Type) -> Option<()> {
|
296
|
-
if self.backend.isa_flags.has_mie2() {
|
297
|
-
Some(())
|
298
|
-
} else {
|
299
|
-
None
|
300
|
-
}
|
301
|
-
}
|
302
|
-
|
303
|
-
#[inline]
|
304
|
-
fn mie2_disabled(&mut self, _: Type) -> Option<()> {
|
305
|
-
if !self.backend.isa_flags.has_mie2() {
|
306
|
-
Some(())
|
307
|
-
} else {
|
308
|
-
None
|
309
|
-
}
|
310
|
-
}
|
311
|
-
|
312
|
-
#[inline]
|
313
|
-
fn vxrs_ext2_enabled(&mut self, _: Type) -> Option<()> {
|
314
|
-
if self.backend.isa_flags.has_vxrs_ext2() {
|
315
|
-
Some(())
|
316
|
-
} else {
|
317
|
-
None
|
318
|
-
}
|
319
|
-
}
|
320
|
-
|
321
|
-
#[inline]
|
322
|
-
fn vxrs_ext2_disabled(&mut self, _: Type) -> Option<()> {
|
323
|
-
if !self.backend.isa_flags.has_vxrs_ext2() {
|
324
|
-
Some(())
|
325
|
-
} else {
|
326
|
-
None
|
327
|
-
}
|
328
|
-
}
|
329
|
-
|
330
|
-
#[inline]
|
331
|
-
fn writable_gpr(&mut self, regno: u8) -> WritableReg {
|
332
|
-
writable_gpr(regno)
|
333
|
-
}
|
334
|
-
|
335
|
-
#[inline]
|
336
|
-
fn zero_reg(&mut self) -> Reg {
|
337
|
-
zero_reg()
|
338
|
-
}
|
339
|
-
|
340
|
-
#[inline]
|
341
|
-
fn gpr32_ty(&mut self, ty: Type) -> Option<Type> {
|
342
|
-
match ty {
|
343
|
-
I8 | I16 | I32 => Some(ty),
|
344
|
-
_ => None,
|
345
|
-
}
|
346
|
-
}
|
347
|
-
|
348
|
-
#[inline]
|
349
|
-
fn gpr64_ty(&mut self, ty: Type) -> Option<Type> {
|
350
|
-
match ty {
|
351
|
-
I64 | R64 => Some(ty),
|
352
|
-
_ => None,
|
353
|
-
}
|
354
|
-
}
|
355
|
-
|
356
|
-
#[inline]
|
357
|
-
fn vr128_ty(&mut self, ty: Type) -> Option<Type> {
|
358
|
-
match ty {
|
359
|
-
I128 => Some(ty),
|
360
|
-
_ if ty.is_vector() && ty.bits() == 128 => Some(ty),
|
361
|
-
_ => None,
|
362
|
-
}
|
363
|
-
}
|
364
|
-
|
365
|
-
#[inline]
|
366
|
-
fn uimm32shifted(&mut self, n: u32, shift: u8) -> UImm32Shifted {
|
367
|
-
UImm32Shifted::maybe_with_shift(n, shift).unwrap()
|
368
|
-
}
|
369
|
-
|
370
|
-
#[inline]
|
371
|
-
fn uimm16shifted(&mut self, n: u16, shift: u8) -> UImm16Shifted {
|
372
|
-
UImm16Shifted::maybe_with_shift(n, shift).unwrap()
|
373
|
-
}
|
374
|
-
|
375
|
-
#[inline]
|
376
|
-
fn i64_nonequal(&mut self, val: i64, cmp: i64) -> Option<i64> {
|
377
|
-
if val != cmp {
|
378
|
-
Some(val)
|
379
|
-
} else {
|
380
|
-
None
|
381
|
-
}
|
382
|
-
}
|
383
|
-
|
384
|
-
#[inline]
|
385
|
-
fn u64_pair_split(&mut self, n: u128) -> (u64, u64) {
|
386
|
-
((n >> 64) as u64, n as u64)
|
387
|
-
}
|
388
|
-
|
389
|
-
#[inline]
|
390
|
-
fn u64_pair_concat(&mut self, hi: u64, lo: u64) -> u128 {
|
391
|
-
(hi as u128) << 64 | (lo as u128)
|
392
|
-
}
|
393
|
-
|
394
|
-
#[inline]
|
395
|
-
fn u32_pair_split(&mut self, n: u64) -> (u32, u32) {
|
396
|
-
((n >> 32) as u32, n as u32)
|
397
|
-
}
|
398
|
-
|
399
|
-
#[inline]
|
400
|
-
fn u32_pair_concat(&mut self, hi: u32, lo: u32) -> u64 {
|
401
|
-
(hi as u64) << 32 | (lo as u64)
|
402
|
-
}
|
403
|
-
|
404
|
-
#[inline]
|
405
|
-
fn u16_pair_split(&mut self, n: u32) -> (u16, u16) {
|
406
|
-
((n >> 16) as u16, n as u16)
|
407
|
-
}
|
408
|
-
|
409
|
-
#[inline]
|
410
|
-
fn u16_pair_concat(&mut self, hi: u16, lo: u16) -> u32 {
|
411
|
-
(hi as u32) << 16 | (lo as u32)
|
412
|
-
}
|
413
|
-
|
414
|
-
#[inline]
|
415
|
-
fn u8_pair_split(&mut self, n: u16) -> (u8, u8) {
|
416
|
-
((n >> 8) as u8, n as u8)
|
417
|
-
}
|
418
|
-
|
419
|
-
#[inline]
|
420
|
-
fn u8_pair_concat(&mut self, hi: u8, lo: u8) -> u16 {
|
421
|
-
(hi as u16) << 8 | (lo as u16)
|
422
|
-
}
|
423
|
-
|
424
|
-
#[inline]
|
425
|
-
fn u8_as_u16(&mut self, n: u8) -> u16 {
|
426
|
-
n as u16
|
427
|
-
}
|
428
|
-
|
429
|
-
#[inline]
|
430
|
-
fn u64_truncate_to_u32(&mut self, n: u64) -> u32 {
|
431
|
-
n as u32
|
432
|
-
}
|
433
|
-
|
434
|
-
#[inline]
|
435
|
-
fn u64_as_i16(&mut self, n: u64) -> i16 {
|
436
|
-
n as i16
|
437
|
-
}
|
438
|
-
|
439
|
-
#[inline]
|
440
|
-
fn u64_nonzero_hipart(&mut self, n: u64) -> Option<u64> {
|
441
|
-
let part = n & 0xffff_ffff_0000_0000;
|
442
|
-
if part != 0 {
|
443
|
-
Some(part)
|
444
|
-
} else {
|
445
|
-
None
|
446
|
-
}
|
447
|
-
}
|
448
|
-
|
449
|
-
#[inline]
|
450
|
-
fn u64_nonzero_lopart(&mut self, n: u64) -> Option<u64> {
|
451
|
-
let part = n & 0x0000_0000_ffff_ffff;
|
452
|
-
if part != 0 {
|
453
|
-
Some(part)
|
454
|
-
} else {
|
455
|
-
None
|
456
|
-
}
|
457
|
-
}
|
458
|
-
|
459
|
-
#[inline]
|
460
|
-
fn i32_from_u64(&mut self, n: u64) -> Option<i32> {
|
461
|
-
if let Ok(imm) = i32::try_from(n as i64) {
|
462
|
-
Some(imm)
|
463
|
-
} else {
|
464
|
-
None
|
465
|
-
}
|
466
|
-
}
|
467
|
-
|
468
|
-
#[inline]
|
469
|
-
fn i16_from_u64(&mut self, n: u64) -> Option<i16> {
|
470
|
-
if let Ok(imm) = i16::try_from(n as i64) {
|
471
|
-
Some(imm)
|
472
|
-
} else {
|
473
|
-
None
|
474
|
-
}
|
475
|
-
}
|
476
|
-
|
477
|
-
#[inline]
|
478
|
-
fn i16_from_u32(&mut self, n: u32) -> Option<i16> {
|
479
|
-
if let Ok(imm) = i16::try_from(n as i32) {
|
480
|
-
Some(imm)
|
481
|
-
} else {
|
482
|
-
None
|
483
|
-
}
|
484
|
-
}
|
485
|
-
|
486
|
-
#[inline]
|
487
|
-
fn uimm32shifted_from_u64(&mut self, n: u64) -> Option<UImm32Shifted> {
|
488
|
-
UImm32Shifted::maybe_from_u64(n)
|
489
|
-
}
|
490
|
-
|
491
|
-
#[inline]
|
492
|
-
fn uimm16shifted_from_u64(&mut self, n: u64) -> Option<UImm16Shifted> {
|
493
|
-
UImm16Shifted::maybe_from_u64(n)
|
494
|
-
}
|
495
|
-
|
496
|
-
#[inline]
|
497
|
-
fn lane_order(&mut self) -> LaneOrder {
|
498
|
-
lane_order_for_call_conv(self.lower_ctx.abi().call_conv(self.lower_ctx.sigs()))
|
499
|
-
}
|
500
|
-
|
501
|
-
#[inline]
|
502
|
-
fn be_lane_idx(&mut self, ty: Type, idx: u8) -> u8 {
|
503
|
-
match self.lane_order() {
|
504
|
-
LaneOrder::LittleEndian => ty.lane_count() as u8 - 1 - idx,
|
505
|
-
LaneOrder::BigEndian => idx,
|
506
|
-
}
|
507
|
-
}
|
508
|
-
|
509
|
-
#[inline]
|
510
|
-
fn be_vec_const(&mut self, ty: Type, n: u128) -> u128 {
|
511
|
-
match self.lane_order() {
|
512
|
-
LaneOrder::LittleEndian => n,
|
513
|
-
LaneOrder::BigEndian => {
|
514
|
-
let lane_count = ty.lane_count();
|
515
|
-
let lane_bits = ty.lane_bits();
|
516
|
-
let lane_mask = (1u128 << lane_bits) - 1;
|
517
|
-
let mut n_le = n;
|
518
|
-
let mut n_be = 0u128;
|
519
|
-
for _ in 0..lane_count {
|
520
|
-
n_be = (n_be << lane_bits) | (n_le & lane_mask);
|
521
|
-
n_le = n_le >> lane_bits;
|
522
|
-
}
|
523
|
-
n_be
|
524
|
-
}
|
525
|
-
}
|
526
|
-
}
|
527
|
-
|
528
|
-
#[inline]
|
529
|
-
fn lane_byte_mask(&mut self, ty: Type, idx: u8) -> u16 {
|
530
|
-
let lane_bytes = (ty.lane_bits() / 8) as u8;
|
531
|
-
let lane_mask = (1u16 << lane_bytes) - 1;
|
532
|
-
lane_mask << (16 - ((idx + 1) * lane_bytes))
|
533
|
-
}
|
534
|
-
|
535
|
-
#[inline]
|
536
|
-
fn shuffle_mask_from_u128(&mut self, idx: u128) -> (u128, u16) {
|
537
|
-
let bytes = match self.lane_order() {
|
538
|
-
LaneOrder::LittleEndian => idx.to_be_bytes().map(|x| {
|
539
|
-
if x < 16 {
|
540
|
-
15 - x
|
541
|
-
} else if x < 32 {
|
542
|
-
47 - x
|
543
|
-
} else {
|
544
|
-
128
|
545
|
-
}
|
546
|
-
}),
|
547
|
-
LaneOrder::BigEndian => idx.to_le_bytes().map(|x| if x < 32 { x } else { 128 }),
|
548
|
-
};
|
549
|
-
let and_mask = bytes.iter().fold(0, |acc, &x| (acc << 1) | (x < 32) as u16);
|
550
|
-
let permute_mask = u128::from_be_bytes(bytes);
|
551
|
-
(permute_mask, and_mask)
|
552
|
-
}
|
553
|
-
|
554
|
-
#[inline]
|
555
|
-
fn u64_from_value(&mut self, val: Value) -> Option<u64> {
|
556
|
-
let inst = self.lower_ctx.dfg().value_def(val).inst()?;
|
557
|
-
let constant = self.lower_ctx.get_constant(inst)?;
|
558
|
-
let ty = self.lower_ctx.output_ty(inst, 0);
|
559
|
-
Some(zero_extend_to_u64(constant, self.ty_bits(ty)))
|
560
|
-
}
|
561
|
-
|
562
|
-
#[inline]
|
563
|
-
fn u64_from_inverted_value(&mut self, val: Value) -> Option<u64> {
|
564
|
-
let inst = self.lower_ctx.dfg().value_def(val).inst()?;
|
565
|
-
let constant = self.lower_ctx.get_constant(inst)?;
|
566
|
-
let ty = self.lower_ctx.output_ty(inst, 0);
|
567
|
-
Some(zero_extend_to_u64(!constant, self.ty_bits(ty)))
|
568
|
-
}
|
569
|
-
|
570
|
-
#[inline]
|
571
|
-
fn u32_from_value(&mut self, val: Value) -> Option<u32> {
|
572
|
-
let constant = self.u64_from_value(val)?;
|
573
|
-
let imm = u32::try_from(constant).ok()?;
|
574
|
-
Some(imm)
|
575
|
-
}
|
576
|
-
|
577
|
-
#[inline]
|
578
|
-
fn u8_from_value(&mut self, val: Value) -> Option<u8> {
|
579
|
-
let constant = self.u64_from_value(val)?;
|
580
|
-
let imm = u8::try_from(constant).ok()?;
|
581
|
-
Some(imm)
|
582
|
-
}
|
583
|
-
|
584
|
-
#[inline]
|
585
|
-
fn u64_from_signed_value(&mut self, val: Value) -> Option<u64> {
|
586
|
-
let inst = self.lower_ctx.dfg().value_def(val).inst()?;
|
587
|
-
let constant = self.lower_ctx.get_constant(inst)?;
|
588
|
-
let ty = self.lower_ctx.output_ty(inst, 0);
|
589
|
-
Some(sign_extend_to_u64(constant, self.ty_bits(ty)))
|
590
|
-
}
|
591
|
-
|
592
|
-
#[inline]
|
593
|
-
fn i64_from_value(&mut self, val: Value) -> Option<i64> {
|
594
|
-
let constant = self.u64_from_signed_value(val)? as i64;
|
595
|
-
Some(constant)
|
596
|
-
}
|
597
|
-
|
598
|
-
#[inline]
|
599
|
-
fn i32_from_value(&mut self, val: Value) -> Option<i32> {
|
600
|
-
let constant = self.u64_from_signed_value(val)? as i64;
|
601
|
-
let imm = i32::try_from(constant).ok()?;
|
602
|
-
Some(imm)
|
603
|
-
}
|
604
|
-
|
605
|
-
#[inline]
|
606
|
-
fn i16_from_value(&mut self, val: Value) -> Option<i16> {
|
607
|
-
let constant = self.u64_from_signed_value(val)? as i64;
|
608
|
-
let imm = i16::try_from(constant).ok()?;
|
609
|
-
Some(imm)
|
610
|
-
}
|
611
|
-
|
612
|
-
#[inline]
|
613
|
-
fn i16_from_swapped_value(&mut self, val: Value) -> Option<i16> {
|
614
|
-
let constant = self.u64_from_signed_value(val)? as i64;
|
615
|
-
let imm = i16::try_from(constant).ok()?;
|
616
|
-
Some(imm.swap_bytes())
|
617
|
-
}
|
618
|
-
|
619
|
-
#[inline]
|
620
|
-
fn i64_from_negated_value(&mut self, val: Value) -> Option<i64> {
|
621
|
-
let constant = self.u64_from_signed_value(val)? as i64;
|
622
|
-
let imm = constant.wrapping_neg();
|
623
|
-
Some(imm)
|
624
|
-
}
|
625
|
-
|
626
|
-
#[inline]
|
627
|
-
fn i32_from_negated_value(&mut self, val: Value) -> Option<i32> {
|
628
|
-
let constant = self.u64_from_signed_value(val)? as i64;
|
629
|
-
let imm = i32::try_from(constant.wrapping_neg()).ok()?;
|
630
|
-
Some(imm)
|
631
|
-
}
|
632
|
-
|
633
|
-
#[inline]
|
634
|
-
fn i16_from_negated_value(&mut self, val: Value) -> Option<i16> {
|
635
|
-
let constant = self.u64_from_signed_value(val)? as i64;
|
636
|
-
let imm = i16::try_from(constant.wrapping_neg()).ok()?;
|
637
|
-
Some(imm)
|
638
|
-
}
|
639
|
-
|
640
|
-
#[inline]
|
641
|
-
fn uimm16shifted_from_value(&mut self, val: Value) -> Option<UImm16Shifted> {
|
642
|
-
let constant = self.u64_from_value(val)?;
|
643
|
-
UImm16Shifted::maybe_from_u64(constant)
|
644
|
-
}
|
645
|
-
|
646
|
-
#[inline]
|
647
|
-
fn uimm32shifted_from_value(&mut self, val: Value) -> Option<UImm32Shifted> {
|
648
|
-
let constant = self.u64_from_value(val)?;
|
649
|
-
UImm32Shifted::maybe_from_u64(constant)
|
650
|
-
}
|
651
|
-
|
652
|
-
#[inline]
|
653
|
-
fn uimm16shifted_from_inverted_value(&mut self, val: Value) -> Option<UImm16Shifted> {
|
654
|
-
let constant = self.u64_from_inverted_value(val)?;
|
655
|
-
let imm = UImm16Shifted::maybe_from_u64(constant)?;
|
656
|
-
Some(imm.negate_bits())
|
657
|
-
}
|
658
|
-
|
659
|
-
#[inline]
|
660
|
-
fn uimm32shifted_from_inverted_value(&mut self, val: Value) -> Option<UImm32Shifted> {
|
661
|
-
let constant = self.u64_from_inverted_value(val)?;
|
662
|
-
let imm = UImm32Shifted::maybe_from_u64(constant)?;
|
663
|
-
Some(imm.negate_bits())
|
664
|
-
}
|
665
|
-
|
666
|
-
#[inline]
|
667
|
-
fn len_minus_one(&mut self, len: u64) -> Option<u8> {
|
668
|
-
if len > 0 && len <= 256 {
|
669
|
-
Some((len - 1) as u8)
|
670
|
-
} else {
|
671
|
-
None
|
672
|
-
}
|
673
|
-
}
|
674
|
-
|
675
|
-
#[inline]
|
676
|
-
fn mask_amt_imm(&mut self, ty: Type, amt: i64) -> u8 {
|
677
|
-
let mask = ty.lane_bits() - 1;
|
678
|
-
(amt as u8) & (mask as u8)
|
679
|
-
}
|
680
|
-
|
681
|
-
#[inline]
|
682
|
-
fn mask_as_cond(&mut self, mask: u8) -> Cond {
|
683
|
-
Cond::from_mask(mask)
|
684
|
-
}
|
685
|
-
|
686
|
-
#[inline]
|
687
|
-
fn intcc_as_cond(&mut self, cc: &IntCC) -> Cond {
|
688
|
-
Cond::from_intcc(*cc)
|
689
|
-
}
|
690
|
-
|
691
|
-
#[inline]
|
692
|
-
fn floatcc_as_cond(&mut self, cc: &FloatCC) -> Cond {
|
693
|
-
Cond::from_floatcc(*cc)
|
694
|
-
}
|
695
|
-
|
696
|
-
#[inline]
|
697
|
-
fn invert_cond(&mut self, cond: &Cond) -> Cond {
|
698
|
-
Cond::invert(*cond)
|
699
|
-
}
|
700
|
-
|
701
|
-
#[inline]
|
702
|
-
fn signed(&mut self, cc: &IntCC) -> Option<()> {
|
703
|
-
if condcode_is_signed(*cc) {
|
704
|
-
Some(())
|
705
|
-
} else {
|
706
|
-
None
|
707
|
-
}
|
708
|
-
}
|
709
|
-
|
710
|
-
#[inline]
|
711
|
-
fn unsigned(&mut self, cc: &IntCC) -> Option<()> {
|
712
|
-
if !condcode_is_signed(*cc) {
|
713
|
-
Some(())
|
714
|
-
} else {
|
715
|
-
None
|
716
|
-
}
|
717
|
-
}
|
718
|
-
|
719
|
-
#[inline]
|
720
|
-
fn vec_length_minus1(&mut self, vec: &VecMachLabel) -> u32 {
|
721
|
-
u32::try_from(vec.len()).unwrap() - 1
|
722
|
-
}
|
723
|
-
|
724
|
-
#[inline]
|
725
|
-
fn vec_element(&mut self, vec: &VecMachLabel, index: u8) -> MachLabel {
|
726
|
-
vec[usize::from(index)]
|
727
|
-
}
|
728
|
-
|
729
|
-
#[inline]
|
730
|
-
fn zero_offset(&mut self) -> Offset32 {
|
731
|
-
Offset32::new(0)
|
732
|
-
}
|
733
|
-
|
734
|
-
#[inline]
|
735
|
-
fn i64_from_offset(&mut self, off: Offset32) -> i64 {
|
736
|
-
i64::from(off)
|
737
|
-
}
|
738
|
-
|
739
|
-
#[inline]
|
740
|
-
fn fcvt_to_uint_ub32(&mut self, size: u8) -> u64 {
|
741
|
-
(2.0_f32).powi(size.into()).to_bits() as u64
|
742
|
-
}
|
743
|
-
|
744
|
-
#[inline]
|
745
|
-
fn fcvt_to_uint_lb32(&mut self) -> u64 {
|
746
|
-
(-1.0_f32).to_bits() as u64
|
747
|
-
}
|
748
|
-
|
749
|
-
#[inline]
|
750
|
-
fn fcvt_to_uint_ub64(&mut self, size: u8) -> u64 {
|
751
|
-
(2.0_f64).powi(size.into()).to_bits()
|
752
|
-
}
|
753
|
-
|
754
|
-
#[inline]
|
755
|
-
fn fcvt_to_uint_lb64(&mut self) -> u64 {
|
756
|
-
(-1.0_f64).to_bits()
|
757
|
-
}
|
758
|
-
|
759
|
-
#[inline]
|
760
|
-
fn fcvt_to_sint_ub32(&mut self, size: u8) -> u64 {
|
761
|
-
(2.0_f32).powi((size - 1).into()).to_bits() as u64
|
762
|
-
}
|
763
|
-
|
764
|
-
#[inline]
|
765
|
-
fn fcvt_to_sint_lb32(&mut self, size: u8) -> u64 {
|
766
|
-
let lb = (-2.0_f32).powi((size - 1).into());
|
767
|
-
std::cmp::max(lb.to_bits() + 1, (lb - 1.0).to_bits()) as u64
|
768
|
-
}
|
769
|
-
|
770
|
-
#[inline]
|
771
|
-
fn fcvt_to_sint_ub64(&mut self, size: u8) -> u64 {
|
772
|
-
(2.0_f64).powi((size - 1).into()).to_bits()
|
773
|
-
}
|
774
|
-
|
775
|
-
#[inline]
|
776
|
-
fn fcvt_to_sint_lb64(&mut self, size: u8) -> u64 {
|
777
|
-
let lb = (-2.0_f64).powi((size - 1).into());
|
778
|
-
std::cmp::max(lb.to_bits() + 1, (lb - 1.0).to_bits())
|
779
|
-
}
|
780
|
-
|
781
|
-
#[inline]
|
782
|
-
fn littleendian(&mut self, flags: MemFlags) -> Option<()> {
|
783
|
-
let endianness = flags.endianness(Endianness::Big);
|
784
|
-
if endianness == Endianness::Little {
|
785
|
-
Some(())
|
786
|
-
} else {
|
787
|
-
None
|
788
|
-
}
|
789
|
-
}
|
790
|
-
|
791
|
-
#[inline]
|
792
|
-
fn bigendian(&mut self, flags: MemFlags) -> Option<()> {
|
793
|
-
let endianness = flags.endianness(Endianness::Big);
|
794
|
-
if endianness == Endianness::Big {
|
795
|
-
Some(())
|
796
|
-
} else {
|
797
|
-
None
|
798
|
-
}
|
799
|
-
}
|
800
|
-
|
801
|
-
#[inline]
|
802
|
-
fn memflags_trusted(&mut self) -> MemFlags {
|
803
|
-
MemFlags::trusted()
|
804
|
-
}
|
805
|
-
|
806
|
-
#[inline]
|
807
|
-
fn memarg_flags(&mut self, mem: &MemArg) -> MemFlags {
|
808
|
-
mem.get_flags()
|
809
|
-
}
|
810
|
-
|
811
|
-
#[inline]
|
812
|
-
fn memarg_reg_plus_reg(&mut self, x: Reg, y: Reg, bias: u8, flags: MemFlags) -> MemArg {
|
813
|
-
MemArg::BXD12 {
|
814
|
-
base: x,
|
815
|
-
index: y,
|
816
|
-
disp: UImm12::maybe_from_u64(bias as u64).unwrap(),
|
817
|
-
flags,
|
818
|
-
}
|
819
|
-
}
|
820
|
-
|
821
|
-
#[inline]
|
822
|
-
fn memarg_reg_plus_off(&mut self, reg: Reg, off: i64, bias: u8, flags: MemFlags) -> MemArg {
|
823
|
-
MemArg::reg_plus_off(reg, off + (bias as i64), flags)
|
824
|
-
}
|
825
|
-
|
826
|
-
#[inline]
|
827
|
-
fn memarg_stack_off(&mut self, base: i64, off: i64) -> MemArg {
|
828
|
-
MemArg::reg_plus_off(stack_reg(), base + off, MemFlags::trusted())
|
829
|
-
}
|
830
|
-
|
831
|
-
#[inline]
|
832
|
-
fn memarg_initial_sp_offset(&mut self, off: i64) -> MemArg {
|
833
|
-
MemArg::InitialSPOffset { off }
|
834
|
-
}
|
835
|
-
|
836
|
-
#[inline]
|
837
|
-
fn memarg_symbol(&mut self, name: ExternalName, offset: i32, flags: MemFlags) -> MemArg {
|
838
|
-
MemArg::Symbol {
|
839
|
-
name: Box::new(name),
|
840
|
-
offset,
|
841
|
-
flags,
|
842
|
-
}
|
843
|
-
}
|
844
|
-
|
845
|
-
#[inline]
|
846
|
-
fn memarg_got(&mut self) -> MemArg {
|
847
|
-
MemArg::Symbol {
|
848
|
-
name: Box::new(ExternalName::KnownSymbol(KnownSymbol::ElfGlobalOffsetTable)),
|
849
|
-
offset: 0,
|
850
|
-
flags: MemFlags::trusted(),
|
851
|
-
}
|
852
|
-
}
|
853
|
-
|
854
|
-
#[inline]
|
855
|
-
fn memarg_symbol_offset_sum(&mut self, off1: i64, off2: i64) -> Option<i32> {
|
856
|
-
let off = i32::try_from(off1 + off2).ok()?;
|
857
|
-
if off & 1 == 0 {
|
858
|
-
Some(off)
|
859
|
-
} else {
|
860
|
-
None
|
861
|
-
}
|
862
|
-
}
|
863
|
-
|
864
|
-
#[inline]
|
865
|
-
fn memarg_pair_from_memarg(&mut self, mem: &MemArg) -> Option<MemArgPair> {
|
866
|
-
MemArgPair::maybe_from_memarg(mem)
|
867
|
-
}
|
868
|
-
|
869
|
-
#[inline]
|
870
|
-
fn memarg_pair_from_reg(&mut self, reg: Reg, flags: MemFlags) -> MemArgPair {
|
871
|
-
MemArgPair {
|
872
|
-
base: reg,
|
873
|
-
disp: UImm12::zero(),
|
874
|
-
flags,
|
875
|
-
}
|
876
|
-
}
|
877
|
-
|
878
|
-
#[inline]
|
879
|
-
fn inst_builder_new(&mut self) -> VecMInstBuilder {
|
880
|
-
Cell::new(Vec::<MInst>::new())
|
881
|
-
}
|
882
|
-
|
883
|
-
#[inline]
|
884
|
-
fn inst_builder_push(&mut self, builder: &VecMInstBuilder, inst: &MInst) -> Unit {
|
885
|
-
let mut vec = builder.take();
|
886
|
-
vec.push(inst.clone());
|
887
|
-
builder.set(vec);
|
888
|
-
}
|
889
|
-
|
890
|
-
#[inline]
|
891
|
-
fn inst_builder_finish(&mut self, builder: &VecMInstBuilder) -> Vec<MInst> {
|
892
|
-
builder.take()
|
893
|
-
}
|
894
|
-
|
895
|
-
#[inline]
|
896
|
-
fn real_reg(&mut self, reg: WritableReg) -> Option<WritableReg> {
|
897
|
-
if reg.to_reg().is_real() {
|
898
|
-
Some(reg)
|
899
|
-
} else {
|
900
|
-
None
|
901
|
-
}
|
902
|
-
}
|
903
|
-
|
904
|
-
#[inline]
|
905
|
-
fn same_reg(&mut self, dst: WritableReg, src: Reg) -> Option<Reg> {
|
906
|
-
if dst.to_reg() == src {
|
907
|
-
Some(src)
|
908
|
-
} else {
|
909
|
-
None
|
910
|
-
}
|
911
|
-
}
|
912
|
-
|
913
|
-
#[inline]
|
914
|
-
fn sinkable_inst(&mut self, val: Value) -> Option<Inst> {
|
915
|
-
let input = self.lower_ctx.get_value_as_source_or_const(val);
|
916
|
-
if let Some((inst, 0)) = input.inst.as_inst() {
|
917
|
-
return Some(inst);
|
918
|
-
}
|
919
|
-
None
|
920
|
-
}
|
921
|
-
|
922
|
-
#[inline]
|
923
|
-
fn emit(&mut self, inst: &MInst) -> Unit {
|
924
|
-
self.lower_ctx.emit(inst.clone());
|
925
|
-
}
|
926
|
-
|
927
|
-
#[inline]
|
928
|
-
fn preg_stack(&mut self) -> PReg {
|
929
|
-
stack_reg().to_real_reg().unwrap().into()
|
930
|
-
}
|
931
|
-
|
932
|
-
#[inline]
|
933
|
-
fn preg_gpr_0(&mut self) -> PReg {
|
934
|
-
gpr(0).to_real_reg().unwrap().into()
|
935
|
-
}
|
936
|
-
|
937
|
-
#[inline]
|
938
|
-
fn writable_regpair(&mut self, hi: WritableReg, lo: WritableReg) -> WritableRegPair {
|
939
|
-
WritableRegPair { hi, lo }
|
940
|
-
}
|
941
|
-
|
942
|
-
#[inline]
|
943
|
-
fn writable_regpair_hi(&mut self, w: WritableRegPair) -> WritableReg {
|
944
|
-
w.hi
|
945
|
-
}
|
946
|
-
|
947
|
-
#[inline]
|
948
|
-
fn writable_regpair_lo(&mut self, w: WritableRegPair) -> WritableReg {
|
949
|
-
w.lo
|
950
|
-
}
|
951
|
-
|
952
|
-
#[inline]
|
953
|
-
fn regpair(&mut self, hi: Reg, lo: Reg) -> RegPair {
|
954
|
-
RegPair { hi, lo }
|
955
|
-
}
|
956
|
-
|
957
|
-
#[inline]
|
958
|
-
fn regpair_hi(&mut self, w: RegPair) -> Reg {
|
959
|
-
w.hi
|
960
|
-
}
|
961
|
-
|
962
|
-
#[inline]
|
963
|
-
fn regpair_lo(&mut self, w: RegPair) -> Reg {
|
964
|
-
w.lo
|
965
|
-
}
|
966
|
-
}
|
967
|
-
|
968
|
-
/// Lane order to be used for a given calling convention.
|
969
|
-
#[inline]
|
970
|
-
fn lane_order_for_call_conv(call_conv: CallConv) -> LaneOrder {
|
971
|
-
if call_conv.extends_wasmtime() {
|
972
|
-
LaneOrder::LittleEndian
|
973
|
-
} else {
|
974
|
-
LaneOrder::BigEndian
|
975
|
-
}
|
976
|
-
}
|
977
|
-
|
978
|
-
/// Zero-extend the low `from_bits` bits of `value` to a full u64.
|
979
|
-
#[inline]
|
980
|
-
fn zero_extend_to_u64(value: u64, from_bits: u8) -> u64 {
|
981
|
-
assert!(from_bits <= 64);
|
982
|
-
if from_bits >= 64 {
|
983
|
-
value
|
984
|
-
} else {
|
985
|
-
value & ((1u64 << from_bits) - 1)
|
986
|
-
}
|
987
|
-
}
|
988
|
-
|
989
|
-
/// Sign-extend the low `from_bits` bits of `value` to a full u64.
|
990
|
-
#[inline]
|
991
|
-
fn sign_extend_to_u64(value: u64, from_bits: u8) -> u64 {
|
992
|
-
assert!(from_bits <= 64);
|
993
|
-
if from_bits >= 64 {
|
994
|
-
value
|
995
|
-
} else {
|
996
|
-
(((value << (64 - from_bits)) as i64) >> (64 - from_bits)) as u64
|
997
|
-
}
|
998
|
-
}
|
999
|
-
|
1000
|
-
/// Determines whether this condcode interprets inputs as signed or
|
1001
|
-
/// unsigned. See the documentation for the `icmp` instruction in
|
1002
|
-
/// cranelift-codegen/meta/src/shared/instructions.rs for further insights
|
1003
|
-
/// into this.
|
1004
|
-
#[inline]
|
1005
|
-
fn condcode_is_signed(cc: IntCC) -> bool {
|
1006
|
-
match cc {
|
1007
|
-
IntCC::Equal => false,
|
1008
|
-
IntCC::NotEqual => false,
|
1009
|
-
IntCC::SignedGreaterThanOrEqual => true,
|
1010
|
-
IntCC::SignedGreaterThan => true,
|
1011
|
-
IntCC::SignedLessThanOrEqual => true,
|
1012
|
-
IntCC::SignedLessThan => true,
|
1013
|
-
IntCC::UnsignedGreaterThanOrEqual => false,
|
1014
|
-
IntCC::UnsignedGreaterThan => false,
|
1015
|
-
IntCC::UnsignedLessThanOrEqual => false,
|
1016
|
-
IntCC::UnsignedLessThan => false,
|
1017
|
-
}
|
1018
|
-
}
|