verilog_gen 0.0.1 → 0.0.2

data/features/vscan/interface_param_override.feature

@@ -0,0 +1,27 @@
+Feature: convert a system verilog format to ruby.
+  @wip
+  Scenario: System Verilog interfaces (with parameters)
+  Given a file named "leaf.sv" with: 
+  """
+  interface intf #(PARAM1=3) (
+    input  logic [PARAM1:0]   in1, in2,
+    output       [PARAM1-1:0] out
+  );
+  wire pin;
+  endinterface: intf
+  """
+  And a file named "expect.rb" with:
+  """
+  class Intf_wide < VerilogGen::HdlInterface
+    set_proxy true
+    set_file_name "leaf.sv"
+    set_interface_name "intf"
+    add_port "in1", direction: "input", type: "logic", packed: "[5:0]"
+    add_port "in2", direction: "output", type: "logic", packed: "[5:0]"
+    add_port "out", direction: "output", type: "logic", packed: "[4:0]"
+  end
+  """
+  When I run `csh -c '../../bin/vscan PARAM1=5 -class Intf_wide leaf.sv > Intf_wide.rb'`
+  Then a file named "Intf_wide.rb" should exist 
+  When I run `hdl_equal expect.rb Intf_wide.rb`
+  Then the exit status should be 0

data/features/vscan/interface_port.feature

@@ -0,0 +1,41 @@
+Feature: convert a system verilog format to ruby.
+  @wip
+  Scenario: System Verilog interfaces
+  Given a file named "leaf.sv" with: 
+  """
+  interface intf (
+    input  logic [3:0] in1, in2,
+    output       [2:0] out
+  );
+  wire pin;
+  endinterface: intf
+
+  module leaf (
+    input wire clk,
+          intf port_interface
+  );
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true
+    set_file_name "leaf.sv"
+    set_module_name "leaf"
+    add_port "clk", direction: "input", type: "wire"
+    add_interface "port_interface", type: "intf"
+  end
+  class Intf < VerilogGen::HdlInterface
+    set_proxy true
+    set_file_name "leaf.sv"
+    set_interface_name "intf"
+    add_port "in1", direction: "input", type: "logic", packed: "[3:0]"
+    add_port "in2", direction: "output", type: "logic", packed: "[3:0]"
+    add_port "out", direction: "output", type: "logic", packed: "[2:0]"
+    end
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.sv > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/interface_sv.feature

@@ -0,0 +1,35 @@
+Feature: convert a system verilog format to ruby.
+  @wip
+  Scenario: System Verilog interfaces
+  Given a file named "leaf.sv" with: 
+  """
+  interface intf;
+    logic [3:0] in1, in2;
+    logic [2:0] out;
+  endinterface: intf
+
+  module leaf (
+    input wire clk,
+          intf port_interface
+  );
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true
+    set_file_name "leaf.sv"
+    set_module_name "leaf"
+    add_port "clk", direction: "input", type: "wire"
+    add_interface "port_interface", type: "intf"
+  end
+  class Intf < VerilogGen::HdlInterface
+    set_proxy true
+    set_file_name "leaf.sv"
+    set_interface_name "intf"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.sv > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/leaf_1995.feature

@@ -0,0 +1,27 @@
+Feature: convert a verilog 1364 format to ruby.
+
+  Scenario: Single input port
+  Given a file named "leaf.v" with: 
+  """
+  module leaf (
+    in,
+    out
+  );
+  input in;
+  output out;
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true                  
+    set_file_name "leaf.v"          
+    set_module_name "leaf"          
+    add_port "in", direction: "input", type: "wire"
+    add_port "out", direction: "output", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/leaf_2001.feature

@@ -0,0 +1,25 @@
+Feature: convert a verilog 1364-2001 format to ruby.
+
+  Scenario: Single input port
+  Given a file named "leaf.v" with: 
+  """
+  module leaf (
+    input  in,
+    output out
+  );
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true
+    set_file_name "leaf.v"
+    set_module_name "leaf"
+    add_port "in", direction: "input", type: "wire"
+    add_port "out", direction: "output", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/leaf_negative_1995.feature

@@ -0,0 +1,24 @@
+Feature: convert a verilog 1364 format to ruby.
+
+  Scenario: Single input port, negative test
+  Given a file named "leaf.v" with: 
+  """
+  module leaf(in, out);
+    input in;
+    output out;
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true
+    set_file_name "leaf.v"
+    set_module_name "leaf"
+    add_port "in", direction: "output", type: "wire"
+    add_port "out", direction: "output", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should not be 0

data/features/vscan/leaf_sv.feature

@@ -0,0 +1,25 @@
+Feature: convert a system verilog format to ruby.
+
+  Scenario: Single input port
+  Given a file named "leaf.sv" with: 
+  """
+  module leaf (
+    input  logic [3:0] in,
+    output reg   [2:0] out,
+  );
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy  true
+    set_file_name "leaf.sv"
+    set_module_name  "leaf"
+    add_port "in", direction: "input", packed: "[3:0]", type: "logic"
+    add_port "out", direction: "output", packed: "[2:0]", type: "reg"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.sv > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/localparam_2001.feature

@@ -0,0 +1,38 @@
+Feature: convert a verilog 1364-2001 format to ruby.
+
+  Scenario: Parameterized ports, not externally changeable
+  Given a file named "leaf.v" with: 
+  """
+  module leaf 
+    #( localparam IN1_MSB = 5,
+       localparam IN1_LSB = 3,
+       localparam IN2_MSB = 7,
+                  IN2_LSB = 0,
+       localparam OUT1_MSB = 31,
+                  OUT1_LSB = 0,
+                  OUT2_MSB = 8,
+                  OUT2_LSB = 3 )
+  (
+    input  [IN1_MSB:IN1_LSB]   in1,
+    input  [IN2_MSB:IN2_LSB]   in2,
+    output [OUT1_MSB:OUT1_LSB] out1,
+    output [OUT2_MSB:OUT2_LSB] out2
+  );
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true
+    set_file_name "leaf.v"
+    set_module_name "leaf"
+    add_port "in1", direction: "input", packed: "[5:3]", type: "wire"
+    add_port "in2", direction: "input", packed: "[7:0]", type: "wire"
+    add_port "out1", direction: "output", packed: "[31:0]", type: "wire"
+    add_port "out2", direction: "output", packed: "[8:3]", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/missing_parameter.feature

@@ -0,0 +1,24 @@
+Feature: convert a verilog 1364-2001 format to ruby.
+
+  Scenario: Parameters in verilog file not specified
+  Given a file named "leaf.v" with: 
+  """
+  module leaf 
+    #( parameter IN1_MSB = 5,
+       parameter IN1_LSB = 3,
+       parameter IN2_MSB = 7,
+       parameter OUT1_MSB = 31,
+                 OUT1_LSB = 0)
+  (
+    input  [IN1_MSB:IN1_LSB]   in1,
+    input  [IN2_MSB:IN2_LSB]   in2,
+    output [OUT1_MSB:OUT1_LSB] out1,
+    output [OUT2_MSB:OUT2_LSB] out2
+  );
+  endmodule
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then it should fail with:
+  """
+  error: I/O declaration using undefined parameter.
+  """

data/features/vscan/multiple_class.feature

@@ -0,0 +1,9 @@
+Feature: Hello World
+
+  Scenario: print banner
+  When I run `csh -c '../../bin/vscan -class trunk -class leaf leaf.v > leaf.rb'`
+  Then it should fail with:
+  """
+  error: you can't specify more than one class overide.
+
+  """

data/features/vscan/multiple_flavors.feature

@@ -0,0 +1,64 @@
+Feature: convert a verilog 1364-2001 format to ruby.
+
+  Scenario: Parameterized ports, with class override into multiple flavors
+  Given a file named "leaf.v" with: 
+  """
+  module leaf 
+    #( parameter IN1_MSB = 5,
+       parameter IN1_LSB = 3,
+       parameter IN2_MSB = 7,
+                 IN2_LSB = 0,
+       parameter OUT1_MSB = 31,
+                 OUT1_LSB = 0,
+                 OUT2_MSB = 8,
+                 OUT2_LSB = 3,
+       parameter DEPTH = 7,
+                 WIDTH = 128 )
+  (
+    input  [IN1_MSB:IN1_LSB]   in1,
+    input  [IN2_MSB:IN2_LSB]   in2,
+    output [OUT1_MSB:OUT1_LSB] out1,
+    output [OUT2_MSB:OUT2_LSB] out2
+  );
+  endmodule
+  """
+  And a file named "expect_wide.rb" with:
+  """
+  class Leaf_wide < VerilogGen::HdlModule
+    set_proxy  true
+    set_file_name  "leaf.v"
+    set_module_name "leaf"
+
+    set_parameter OUT2_MSB: 10
+    set_parameter OUT2_LSB:  5
+    set_parameter WIDTH:  256
+
+    add_port "in1", direction: "input", packed: "[5:3]", type: "wire"
+    add_port "in2", direction: "input", packed: "[7:0]", type: "wire"
+    add_port "out1", direction: "output", packed: "[31:0]", type: "wire"
+    add_port "out2", direction: "output", packed: "[10:5]", type: "wire"
+  end
+  """
+  And a file named "expect_narrow.rb" with:
+  """
+  class Leaf_narrow < VerilogGen::HdlModule
+    set_proxy  true
+    set_file_name  "leaf.v"
+    set_module_name  "leaf"
+    set_parameter OUT1_MSB: 4
+    set_parameter OUT1_LSB: 2
+    set_parameter WIDTH: 32
+    add_port "in1", direction: "input", packed: "[5:3]", type: "wire"
+    add_port "in2", direction: "input", packed: "[7:0]", type: "wire"
+    add_port "out1", direction: "output", packed: "[4:2]", type: "wire"
+    add_port "out2", direction: "output", packed: "[8:3]", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan OUT2_MSB=10 OUT2_LSB=5 WIDTH=256 -class leaf_wide leaf.v > leaf_wide.rb'`
+  And I run `csh -c '../../bin/vscan OUT1_MSB=4 OUT1_LSB=2 WIDTH=32 -class leaf_narrow leaf.v > leaf_narrow.rb'`
+  Then a file named "leaf_wide.rb" should exist 
+  And a file named "leaf_narrow.rb" should exist 
+  When I run `hdl_equal expect_wide.rb leaf_wide.rb`
+  Then the exit status should be 0
+  When I run `hdl_equal expect_narrow.rb leaf_narrow.rb`
+  Then the exit status should be 0

data/features/vscan/multiple_modules.feature

@@ -0,0 +1,60 @@
+Feature: Check that module name and file name match
+  Scenario: Mismatched names
+  Given a file named "leaf.v" with: 
+  """
+  module mod_a (
+    input  in_a,
+    output out_a
+  );
+  mod_c mod_c (
+    .in  ( in_a  ),
+    .out ( out_a ),
+  );
+  endmodule
+
+  module mod_b (
+    input  in_b,
+    output out_b
+  );
+  mod_c mod_c (
+    .in  ( in_b  ),
+    .out ( out_b ),
+  );
+  endmodule
+
+  module mod_c (
+    input  in,
+    output out
+  );
+  assign out = in;
+  endmodule
+
+  """
+  And a file named "expect.rb" with:
+  """
+  class Mod_a < VerilogGen::HdlModule
+    set_proxy  true
+    set_file_name  "leaf.v"
+    set_module_name  "mod_a"
+    add_port "in_a", direction: "input", type: "wire"
+    add_port "out_a", direction: "output", type: "wire"
+  end
+  class Mod_b < VerilogGen::HdlModule
+    set_proxy  true
+    set_file_name  "leaf.v"
+    set_module_name  "mod_b"
+    add_port "in_b", direction: "input", type: "wire"
+    add_port "out_b", direction: "output", type: "wire"
+  end
+  class Mod_c < VerilogGen::HdlModule
+    set_proxy true
+    set_file_name "leaf.v"
+    set_module_name "mod_c"
+    add_port "in_c", direction: "input", type: "wire"
+    add_port "out_c", direction: "output", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then a file named "leaf.rb" should exist
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/name_mismatch.feature

@@ -0,0 +1,24 @@
+Feature: Check that module name and file name match
+
+  Scenario: Mismatched names
+  Given a file named "leaf.v" with: 
+  """
+  module trunk(in, out);
+    input in;
+    output out;
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Trunk < VerilogGen::HdlModule
+   set_proxy  true
+   set_file_name  "leaf.v"
+   set_module_name  "trunk"
+   add_port "in", direction: "input", type: "wire"
+   add_port "out", direction: "output", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then a file named "leaf.rb" should exist
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0

data/features/vscan/net_type.feature

@@ -0,0 +1,67 @@
+Feature: convert a verilog 1364-2001 format to ruby.
+
+  Scenario: Port list contains inout types
+  Given a file named "leaf.v" with: 
+  """
+  module leaf (
+    input reg       i_reg,
+    input logic     i_logic,
+    input bit       i_bit,
+    input byte      i_byte,
+    input shortint  i_shortint,
+    input int       i_int,
+    input longint   i_longint,
+    input time      i_time,
+    input realtime  i_realtime,
+    input shortreal i_shortreal,
+    input real      i_real,
+    input wand      i_wand,
+    input wor       i_wor,
+    input tri       i_tri,
+    input triand    i_triand,
+    input trior     i_trior,
+    input tri0      i_tri0,
+    input tri1      i_tri1,
+    input supply0   i_supply0,
+    input supply1   i_supply1,
+    input trireg    i_trireg,
+    input wire      i_wire,
+    input           i_implicit_wire
+  );
+  endmodule
+  """
+  And a file named "expect.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true
+    set_file_name  "leaf.v"
+    set_module_name  "leaf"
+    add_port "i_reg", direction: "input", type: "reg"
+    add_port "i_logic", direction: "input", type: "logic"
+    add_port "i_bit", direction: "input", type: "bit"
+    add_port "i_byte", direction: "input", type: "byte"
+    add_port "i_shortint", direction: "input", type: "shortint"
+    add_port "i_int", direction: "input", type: "int"
+    add_port "i_longint", direction: "input", type: "longint"
+    add_port "i_time", direction: "input", type: "time"
+    add_port "i_realtime", direction: "input", type: "realtime"
+    add_port "i_shortreal", direction: "input", type: "shortreal"
+    add_port "i_real", direction: "input", type: "real"
+    add_port "i_wand", direction: "input", type: "wire"
+    add_port "i_wor", direction: "input", type: "wire"
+    add_port "i_tri", direction: "input", type: "wire"
+    add_port "i_triand", direction: "input", type: "wire"
+    add_port "i_trior", direction: "input", type: "wire"
+    add_port "i_tri0", direction: "input", type: "wire"
+    add_port "i_tri1", direction: "input", type: "wire"
+    add_port "i_supply0", direction: "input", type: "wire"
+    add_port "i_supply1", direction: "input", type: "wire"
+    add_port "i_trireg", direction: "input", type: "wire"
+    add_port "i_wire", direction: "input", type: "wire"
+    add_port "i_implicit_wire", direction: "input", type: "wire"
+  end
+  """
+  When I run `csh -c '../../bin/vscan leaf.v > leaf.rb'`
+  Then a file named "leaf.rb" should exist 
+  When I run `hdl_equal expect.rb leaf.rb`
+  Then the exit status should be 0