verilog_gen 0.0.1 → 0.0.2

data/lib/verilog_gen/hookup.rb

@@ -0,0 +1,153 @@
+module VerilogGen
+  
+  # Check if all the ports in the list are inputs.
+  # @param [Array] port_lst is the list of ports
+  # @return [Boolean] True if all are inputs.
+  def self.unconnected_input_ports?(port_lst)
+    return false if port_lst.empty?
+    port_lst.each do |port|
+      return false unless port.direction == "input"
+    end
+    return true
+  end
+
+  # Check if all the ports in the list are outputs.
+  # @param [Array] port_lst is the list of ports
+  # @return [Boolean] True if all are outputs.
+  def self.unconnected_output_ports?(port_lst)
+    return false if port_lst.empty?
+    port_lst.each do |port|
+      return false unless port.direction == "output"
+    end
+    return true
+  end
+  
+  # Find the super width from a list of ports.
+  # @param [Array] list of ports
+  # @return [Array] lhs, rhs
+  # @note: 
+  #     Assumes that all ports in the list are of same endiannes..
+  #     FIXME: For this it looks at the port in the middle.
+  #     Should scan all the ports to detect it.
+  def self.super_port_width(port_lst)
+    sample_port = port_lst[port_lst.size/2]
+    lhs_values = []
+    rhs_values = []
+    port_lst.each do |port|
+      lhs_values << port.lhs
+      rhs_values << port.rhs
+    end
+    if sample_port.lhs > sample_port.rhs
+      return lhs_values.max, rhs_values.min
+    else
+      return lhs_values.min, rhs_values.max
+    end
+  end
+
+  # Adds a connect port to the hdl module class.
+  # @return nil
+  # @note The name of the connect port is the name of the pin
+  #       and the width of the port is the super width.
+  def self.add_new_connect_port(klass, pin_name, port_lst)
+    lhs, rhs = super_port_width(port_lst)
+    p = port_lst[0].create_connect_port(pin_name, lhs, rhs) 
+    klass.ports[pin_name] = p
+  end
+
+  # Create pins for unconnected ports in current instance.
+  # @param [Object] instance of hdl module
+  # @return [Fixnum] Number of pins added
+  # @note Ports with existing pins are skippped.
+  def self.create_missing_pins(instance)
+    num_pins_created = 0
+    instance.class.ports.each do |port_name, port|
+      unless instance.pins.key? port_name
+        instance.pins[port_name] = Pin.new(port)
+        num_pins_created += 1
+      end
+    end
+    num_pins_created
+  end
+
+  # Create  missing pins for all children below the instance.
+  # Use depth first to build all the leaf and then the rest of the
+  # modules.
+  # @param [Object] instance of the design.
+  # @return [nil] 
+  # @note Idempotent since port that have pins are skipped.
+  def self.create_missing_pins_depth_first(instance)
+    if instance.class.proxy
+      # Leaf do not change the ports. hence we don't need to do it again.
+      # But it is harmless if all ports are already connected. 
+      create_missing_pins instance
+    else 
+      instance.class.child_instances.each do |child_name, child|
+        create_missing_pins_depth_first child
+      end
+      # If new pins are created then we would need to create the connect ports
+      # in the current class. 
+      num_new_ports = create_connect_ports(instance.class) 
+
+      # Run custom user connect
+      instance.class.connect
+
+      # If we added new ports to the class then all instantiaton must get new pins.
+      create_missing_pins instance if num_new_ports > 0
+    end
+  end
+
+  # Create connectivity map for children of a hdl module.
+  # @param [Object] klass of the hdl module.
+  # @return [Hash] hash of array. PinName => [Port0, Port 10.....]
+  # 
+  def self.get_child_pins_connectivity(klass)
+    pin_connections = Hash.new {|hash, key| hash[key] = Array.new }
+    klass.child_instances.each do |child_name, child|
+      child.pins.each do |port_name, pin|
+        pin_connections[pin.name].push pin.port
+      end
+    end
+    pin_connections
+  end
+
+  # Create ports to provide connectivity to the child instances.
+  # @param [Object] klass HdlModule
+  # @return [Fixnum] number of ports created in the class. 
+  # @note
+  #     An input port is created if the children pins are inputs. 
+  #     A  output port is created if the children pins are output.
+  #     If mixture of input and output pins, then no ports are created.
+  #     The width of the port is the superset of the width. 
+  def self.create_connect_ports(klass)
+    num_connect_ports = 0
+    pin_connections = get_child_pins_connectivity(klass)
+    pin_connections.each do |pin_name, port_lst|
+      if unconnected_input_ports?(port_lst)
+        add_new_connect_port(klass, pin_name, port_lst)
+        num_connect_ports += 1
+      elsif unconnected_output_ports?(port_lst)
+        add_new_connect_port(klass, pin_name, port_lst)
+        num_connect_ports += 1
+      end
+    end 
+    num_connect_ports 
+  end
+
+  # Connect child instances and create hookup ports.
+  # @param [Object] top_level_class of the design.
+  # @note 
+  #     Start with each child instance.
+  #     
+  def self.hookup(top_level_class)
+    top_level_class.child_instances.each do |instance_name, instance|
+      create_missing_pins_depth_first(instance)
+    end
+    # Run custom user connect
+    top_level_class.connect
+
+    # Create the primary connect ports
+    create_connect_ports(top_level_class) 
+
+  end
+
+end

data/lib/verilog_gen/pin.rb

@@ -0,0 +1,39 @@
+module VerilogGen
+  # Model of a pin connected to a port
+  class Pin
+
+    attr_reader :port, :name, :type, :lhs, :rhs, :direction
+   
+    # A pin connects to a port. 
+    # @note By default the pin name, type and width is the same as port.
+    def initialize(port)
+      @port = port
+      @name = port.name
+      @type = port.type
+      @lhs = port.lhs 
+      @rhs = port.rhs 
+      @direction = port.direction
+    end
+
+    # Update a pin attributes.
+    # @param [String] name of the pin
+    # @param [Hash] params properties of pin
+    # @option params [String] :name of the pin
+    # @option params [String] :type of the pin
+    # @option params [Fixnum] :lhs left hand width of the pin
+    # @option params [Fixnum] :rhs right hand width of the pin
+    # @option params [String] :direction of the pin
+    def connect(pin_name, params = {})
+      @name = pin_name
+      params.each do |key, value|
+        raise ArgumentError, "Unknown attribute '#{key}' specified for pin" \
+              unless instance_variables.include?("@#{key}".to_sym)
+        instance_variable_set("@#{key}", value)
+      end
+    end
+
+    def width
+      (@lhs - @rhs + 1).abs
+     end
+  end
+end

data/lib/verilog_gen/port.rb

@@ -0,0 +1,109 @@
+module VerilogGen
+  # Model of a verilog port.
+  class Port
+    
+    @@DEFAULT_PARAMS = {
+                       :name => "", 
+                       :direction => "input", 
+                       :lhs => 0, 
+                       :rhs => 0,
+                       :type => "wire",
+                       :packed => "",
+                       :unpacked => ""
+                      }
+
+    # Construct a port.
+    # @param [Hash] params properties of the port
+    # @option params [String] :name name of the port
+    # @option params [String] :direction By default input
+    # @option params [Integer]:left By default 0 
+    # @option params [Integer] right hand digit. By default 0.
+    # @note If lhs and rhs are 0 then it is a scalar port else vector type.
+    def initialize(name, params = {})
+      @@DEFAULT_PARAMS.each do |key, value|
+        instance_variable_set("@#{key}", value)
+        self.class.send(:attr_reader, key.to_s)
+      end
+
+      @name = name
+
+      params.each do |key, value|
+        raise ArgumentError, 
+          "invalid value of port field '#{key}' with '#{value}'" \
+           unless @@DEFAULT_PARAMS.has_key? key
+        instance_variable_set("@#{key}", value)
+      end
+
+      #Enumeration checking.
+      raise ArgumentError, "direction '#{direction}' is not valid value" \
+                        unless @direction == "input" or @direction == "output"\
+                          or @direction == "inout"
+
+      # FIXME: Hack lhs and rhs
+      unless @packed == ""
+        m = /\[\s*(-*\d+)\s*:\s*(-*\d+)\s*\]/.match @packed
+        @lhs = m.captures[0].to_i
+        @rhs = m.captures[1].to_i
+      end 
+    end
+
+    # Equaltiy of port
+    # @param [Object] other port instance
+    # @return [Boolean] comparion result
+    def ==(other)
+      return false unless other.instance_of?(self.class)
+      name == other.name && direction == other.direction \
+        && lhs == other.lhs && rhs == other.rhs
+    end
+
+    # Well behaved hash keys
+    # @param [Object] other port instance
+    # @return [Boolean] true/false
+    # @note if a.eql?(b) then a.hash = b.hash
+    def eql?(other)
+      return self == other
+    end
+   
+    # Compute the hash key.
+    def hash
+      return name.hash ^ direction.hash ^ lhs.hash ^ rhs.hash
+    end
+
+    # Utility function to detect scalar vector port.
+    # @return [Boolean] true if this is a scalar port else vector.
+    # @note A port is scalar if lhs and rhs are both 0.
+    def scalar?
+      lhs == 0  and rhs == 0
+    end
+
+    # Utility function to return the width of the port
+    # @return [Integer] Width of the port
+    def width
+      (lhs > rhs) ? lhs - rhs + 1 : rhs - lhs + 1
+    end
+
+    # Utility routine to return the port declaration 
+    # @return [String] 
+    def type
+      if direction == "output" and width == 1
+        return "logic"
+      elsif direction == "output"
+        return "logic [#{lhs}:#{rhs}]"
+      elsif direction == "input" and not scalar? 
+        return "[#{lhs}:#{rhs}]"
+      else
+        return ""
+      end
+    end
+
+    # HACK for creating a connect port.
+    # Want to create  a port that is identical to the current port but
+    # has a different name and width.
+    # @note : This is a hack for getting the demo to work.
+    def create_connect_port(new_name, new_lhs, new_rhs)
+      p = Port.new(new_name,  direction: direction, 
+                   lhs: new_lhs , rhs: new_rhs, type: type,
+                   packed: "", unpacked: "")
+    end
+  end
+end

data/lib/verilog_gen/proxy.rb

@@ -0,0 +1,33 @@
+# Wrapper routines to import design into ruby.
+
+module VerilogGen
+  # Return the created class for subsequent access.
+  @@verilog_leaf_created = {}
+
+  # Invoke vscan to create the leaf proxy.
+  # @param [String] Class name of hdl leaf.
+  # @param [Hash] parameter to pass to vscan.
+  # @param file_name [Hash] name of the rtl file.
+  # @return Hdl module class.
+  # @note
+  # Once a class is created then subsequent access will return prev value.
+  def self.leaf(klass, params = {})
+    options = { parameter: "", file_name: klass.snakecase + ".v" }
+    params.each do |key, value|
+      raise ArgumentError, "invalid valid value of leaf '#{key}'" \
+        unless options.key? key
+      options[key] = params[key]
+    end
+      
+    key = klass + options[:parameter]
+    unless @@verilog_leaf_created.key?(key)
+      puts "Running vscan #{options[:parameter]} -class #{klass} #{options[:file_name]}"
+      output = `vscan #{options[:parameter]} -class #{klass} \
+                                            #{options[:file_name]}`
+      eval output, binding, __FILE__, __LINE__
+      @@verilog_leaf_created[key] = Object.const_get("VerilogGen::#{klass}")
+    end
+    @@verilog_leaf_created[key]
+  end
+end
+

data/lib/verilog_gen/string.rb

@@ -0,0 +1,38 @@
+class String
+  def camelize
+    self.split("_").each {|s| s.capitalize! }.join("")
+  end
+
+  def snakecase
+    #gsub(/::/, '/').
+    gsub(/([A-Z]+)([A-Z][a-z])/,'\1_\2').
+    gsub(/([a-z\d])([A-Z])/,'\1_\2').
+    tr('-', '_').
+    gsub(/\s/, '_').
+    gsub(/__+/, '_').
+    downcase
+  end
+
+  def constantize
+     names = self.split('::')
+     names.shift if names.empty? || names.first.empty?
+     names.inject(Object) do |constant, name|
+       if constant == Object
+         constant.const_get(name)
+       else
+         candidate = constant.const_get(name)
+         next candidate if constant.const_defined?(name, false)
+         next candidate unless Object.const_defined?(name)
+         # Go down the ancestors to check it it's owned
+         # directly before we reach Object or the end of ancestors.
+         constant = constant.ancestors.inject do |const, ancestor|
+           break const    if ancestor == Object
+           break ancestor if ancestor.const_defined?(name, false)
+           const
+         end
+         # owner is in Object, so raise
+         constant.const_get(name, false)
+       end
+     end
+   end
+end

data/lib/verilog_gen/version.rb

@@ -1,3 +1,3 @@
 module VerilogGen
-  VERSION = "0.0.1"
+  VERSION = "0.0.2"
 end

data/spec/fixture/generic_mem.v

@@ -0,0 +1,38 @@
+// --------------------------------------------------
+//
+// Generic memory
+//
+// This module is a generic memory with write/read enables and 
+// read data is available registered (next clock cycle).  The
+// Width and Depth of the memory are parameterizeable.
+//
+// --------------------------------------------------
+
+module generic_mem
+  #( parameter  DEPTH=8,
+     parameter  WIDTH=32,
+     localparam AWIDTH=$clog2(DEPTH) )
+(
+  input wire              clk,
+  input wire              mem_wr_en,
+  input wire [AWIDTH-1:0] mem_wr_addr,
+  input wire [WIDTH-1:0]  mem_wr_data,
+  input wire              mem_rd_en,
+  input wire [AWIDTH-1:0] mem_rd_addr,
+  input wire [WIDTH-1:0]  mem_rd_data
+);
+
+// The memory declaration
+reg [WIDTH-1:0] generic_memory [DEPTH-1:0];
+
+always @ (posedge clk) begin
+  if( mem_wr_en ) begin
+    generic_memory[mem_wr_addr] <= #0 mem_wr_data;
+  end
+
+  if( mem_rd_en ) begin
+    mem_rd_data <= #0 generic_memory[mem_rd_addr];
+  end
+end
+
+endmodule

data/spec/hdl_child_array_spec.rb

@@ -0,0 +1,29 @@
+require 'spec_helper'
+
+# Check the syntax for accessing child instances in array. 
+#
+describe VerilogGen::HdlModule do
+  before(:all) do
+    class Leaf < VerilogGen::HdlModule
+    end
+
+    class Node < VerilogGen::HdlModule; 
+      10.times do |i|
+        add_child_instance "leaf#{i}", Leaf
+      end
+    end
+
+  end
+  it "should have the correct number of chilren" do
+    expect(Node.child_instances.size).to eq(10) 
+  end
+  it "should support dot notation" do
+    expect(Node.leaf0.instance_name).to eq("leaf0") 
+  end
+  it "should support loop in dot notation" do
+    10.times do |i|
+      expect(Node.child_instances["leaf#{i}"].instance_name).to eq("leaf#{i}") 
+    end
+  end
+
+end