verilog_gen 0.0.1 → 0.0.2

data/features/sprint1/tie_port.feature

@@ -0,0 +1,40 @@
+Feature: Tie a child instance port to a fixed value.
+
+Scenario: Tie input port of a child to a constant value.
+  Given a file named "leaf.rb" with: 
+  """
+  class Leaf < HdlModule
+    def build
+      add_port "in1", direction: "input", width: 10
+      add_port "out1", direction: "output"
+    end
+  end
+  """
+  And a file named "dut.rb" with:
+  """
+  class Dut < HdlModule
+
+    def build
+       add_instance Leaf, "leaf1"
+       leaf1.in1.tie_to 48  #Tied port to a constant value
+       leaf1.out1.connect_pin "out" 
+    end
+
+  end
+  """
+
+  When I run `vgen leaf.rb dut.rb `
+  Then the file "dut.v" should contain:
+    """
+
+      module dut(out);
+      output out;
+
+      wire out;
+
+      Leaf leaf1(.in1(10'd48),
+                 .out1(out));
+
+      endmodule
+    """
+

data/features/sprint1/unused_port.feature

@@ -0,0 +1,41 @@
+Feature: Force a port to be unconnected.
+
+Scenario: Leave a port of a leaf unconnected
+  Given a file named "leaf.rb" with: 
+  """
+  class Leaf < HdlModule
+    def build
+      add_port "in1", direction: "input", width: 10
+      add_port "out1", direction: "output"
+    end
+  end
+  """
+  And a file named "dut.rb" with:
+  """
+  class Dut < HdlModule
+
+    def build
+       add_instance Leaf, "leaf1"
+       leaf1.in1.unused
+       leaf1.out1.connect_pin "out" 
+    end
+
+  end
+  """
+
+  When I run `vgen leaf.rb dut.rb `
+  Then the file "dut.v" should contain:
+    """
+
+      module dut(out);
+      output out;
+
+      wire [9:0] unused_leaf1_in1
+      wire out;
+
+      Leaf leaf1(.in1(unused_leaf1_in1),
+                 .out1(out));
+
+      endmodule
+    """
+

data/features/sprint1/vector_split.feature

@@ -0,0 +1,41 @@
+Feature: Rename a vector port to separate pins
+
+  Scenario: connect one leaf
+  Given a file named "leaf.rb" with: 
+  """
+  class Leaf < HdlModule
+    def build
+      add_port "in1", width: 10
+      add_port "out1", direction: "output", width: 5
+    end
+  end
+  """
+  And a file named "dut.rb" with:
+  """
+  class Dut < HdlModule
+    def build
+      add_instance Leaf "leaf1"
+      leaf1.in1.range(5,0).connect_pin("sub_in1")
+      leaf1.in1.range(9,6).connect_pin("sub_in2")
+      leaf1.out1.connect_pint("out")
+    end
+  end
+  """
+
+  When I run `vgen leaf.rb dut.rb `
+  Then the file "dut.v" should contain:
+    """
+
+      module dut(in, out);
+      input [9:0] in;
+      output [4:0] out1;
+
+      wire [5:0] sub_in1;
+      wire [3:0] sub_in2;
+      wire [4:0] out1;
+
+      Leaf leaf1(.in1({sub_in2, sub_in1}),
+                 .out1(out1));
+
+      endmodule
+    """

data/features/sprint1/wire_connect.feature

@@ -0,0 +1,46 @@
+Feature: Internal connections do not become primary input/output ports.
+
+  Scenario: Internal pin not connected to port
+  Given a file named "producer.rb" with: 
+  """
+  class Producer < HdlModule
+    def build
+      add_port "out1", width: 10, direction: "output"
+    end
+  end
+  """
+  And a file named "consumer.rb" with: 
+  """
+  class Consumer < HdlModule
+    def build
+      add_port "in1", width: 10, direction: "input"
+    end
+  end
+  """
+  And a file named "dut.rb" with:
+  """
+  class Dut < HdlModule
+
+    def build
+       add_instance Producer, "producer"
+       add_instance Consumer, "consumer"
+       producer.out1.connect "data"
+       consumer.in1.connect "data"
+    end
+
+  end
+  """
+  When I run `vgen leaf.rb dut.rb `
+  Then the file "dut.v" should contain:
+    """
+
+      module dut;
+      
+      wire[9:0] data;
+
+      producer producer(.out1(data))
+      consumer consumer(.in1(data))
+
+      endmodule
+    """
+

data/features/sprint2/expression_net.feature

@@ -0,0 +1,41 @@
+Feature: Rename the input and output pins
+
+  Scenario: connect one leaf
+  Given a file named "leaf.rb" with: 
+  """
+  class Leaf < HdlModule
+    def build
+      add_port "in1"
+      add_port "out1", direction: "output"
+    end
+  end
+  """
+  And a file named "dut.rb" with:
+  """
+  class Dut < HdlModule
+
+    def build
+       add_instance Leaf, "leaf1"
+       connect_port_to_pin leaf1.in1, "in" 
+       connect_port_to_pin leaf1.out1, "out" 
+    end
+
+  end
+  """
+
+  When I run `vgen leaf.rb dut.rb `
+  Then the file "dut.v" should contain:
+    """
+
+      module dut(in, out);
+      input in;
+      output out;
+
+      wire in;
+      wire out;
+
+      Leaf leaf1(.in1(in),
+                 .out1(out));
+
+      endmodule
+    """

data/features/sprint2/fifo.feature

@@ -0,0 +1,61 @@
+Feature: Create a simple fifo.
+
+  Scenario: Create a logical view
+  Given a file named "cntlr.rb" with: 
+  """
+  class Cntlr < HdlModule
+    def build
+      add_port "rst"
+      add_port "clk"
+      add_port "push"
+      add_port "wena"
+    end
+  end
+  """
+  And a file named "memory.rb" with:
+  """
+  class Memory < HdlModule
+    def build
+      add_port Port.new("rst")
+      add_port Port.new("clk")
+      add_port Port.new("write_enable")
+    end
+  end
+  """
+  And a file named "fifo.rb" with:
+  """
+  class Fifo < HdlModule
+    def build
+       add_instance Cntlr, "cntlr1"
+       add_instance Memory, "memory1"
+    end
+
+    def connect
+       #Create the pin
+       connect cntlr1.wen, "write_enable" 
+    end
+  end
+  """
+
+  When I run `vgen fifo.rb memory.rb fifo.rb `
+  Then the file "fifo.v" should contain:
+    """
+
+      module fifo(rst, clk, push);
+      input rst;
+      input clk;
+      input push;
+
+      wire rst;
+      wire clk;
+
+      Cntlr cntlr1(.rst(rst),
+                   .clk(clk),
+                   .wen(write_enable));
+
+      Memory memory1(.rst(rst),
+                     .clk(clk),
+                     .write_enable(write_enable));
+
+      endmodule
+    """

data/features/sprint2/wire_expression.feature

@@ -0,0 +1,48 @@
+Feature: Invert the output pin and connect to input pin.
+
+  Scenario: Invert output 
+  Given a file named "producer.rb" with: 
+  """
+  class Producer < HdlModule
+    def build
+      add_port "out1", width: 10, direction: "output"
+    end
+  end
+  """
+  And a file named "consumer.rb" with: 
+  """
+  class Consumer < HdlModule
+    def build
+      add_port "in1", width: 10, direction: "input"
+    end
+  end
+  """
+  And a file named "dut.rb" with:
+  """
+  class Dut < HdlModule
+
+    def build
+       add_instance Producer, "producer"
+       add_instance Consumer, "consumer"
+       producer.out1.connect "data"
+       add_instance InvGate, output: "data_inv", input: "data"
+       consumer.in1.connect "data_inv"
+    end
+
+  end
+  """
+  When I run `vgen leaf.rb dut.rb `
+  Then the file "dut.v" should contain:
+    """
+
+      module dut;
+      
+      wire[9:0] data;
+
+      producer producer(.out1(data));
+      assign data_inv = ~data;
+      consumer consumer(.in1(data_inv));
+
+      endmodule
+    """
+

data/features/step_definitions/vgen_steps.rb

@@ -0,0 +1,3 @@
+
+
+

data/features/support/env.rb

@@ -1,5 +1,7 @@
 require 'pathname'
+require 'aruba/cucumber'
 root = Pathname.new(__FILE__).parent.parent.parent
 
 ENV['PATH'] = "#{root.join('bin').to_s}#{File::PATH_SEPARATOR}#{ENV['PATH']}"
-puts ENV['PATH']
+
+puts "done loading support env"

data/features/vgen/add_child.feature

@@ -0,0 +1,60 @@
+Feature: Add a leaf node.
+
+  Scenario: No ports in leaf 
+  Given a file named "node.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_module_name  "leaf_module"
+    set_proxy true 
+  end
+  class Node1 < VerilogGen::HdlModule
+    set_module_name  "node1_module"
+    add_port "in", direction: "input", packed: "[3:0]", type: "wire"
+    add_port "out", direction: "output", packed: "[2:0]",type: "reg"
+    add_child_instance "leaf", Leaf
+  end
+  """
+  When I run `vgen -t Node1 node.rb`
+  Then a file named "node1_module.v" should exist 
+  And a file named "leaf_module.v" should not exist 
+  
+  Scenario: Ports in leaf 
+  Given a file named "node.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_module_name  "leaf_module"
+    set_proxy true 
+    add_port "in", direction: "input", packed: "[3:0]", type: "wire"
+    add_port "out", direction: "output", packed: "[2:0]",type: "reg"
+  end
+  class Node1 < VerilogGen::HdlModule
+    set_module_name  "node1_module"
+    add_port "in", direction: "input", packed: "[3:0]", type: "wire"
+    add_port "out", direction: "output", packed: "[2:0]",type: "reg"
+    add_child_instance "leaf", Leaf
+  end
+  """
+  When I run `vgen -t Node1 node.rb`
+  Then a file named "node1_module.v" should exist 
+  And a file named "leaf_module.v" should not exist 
+  
+  Scenario: Multiple leaves 
+  Given a file named "node.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_module_name  "leaf_module"
+    set_proxy true 
+    add_port "in", direction: "input", packed: "[3:0]", type: "wire"
+    add_port "out", direction: "output", packed: "[2:0]",type: "reg"
+  end
+  class Node1 < VerilogGen::HdlModule
+    set_module_name  "node1_module"
+    add_port "in", direction: "input", packed: "[3:0]", type: "wire"
+    add_port "out", direction: "output", packed: "[2:0]",type: "reg"
+    add_child_instance "leaf0", Leaf
+    add_child_instance "leaf1", Leaf
+  end
+  """
+  When I run `vgen -t Node1 node.rb`
+  Then a file named "node1_module.v" should exist 
+  And a file named "leaf_module.v" should not exist 

data/features/vgen/fifo_ctrl.feature

@@ -0,0 +1,24 @@
+Feature: Generate a v2k code for demo fifo ctrl
+
+  Scenario: Demo fifo ctrl 
+  Given a file named "fifo_ctrl.rb" with:
+  """
+class Fifo_ctrl_4d < VerilogGen::HdlModule
+  set_file_name "fifo_ctrl.v"
+  set_module_name "fifo_ctrl_4d"
+  set_parameter DEPTH: 4
+  add_port "clk", direction: "input", type: "wire"
+  add_port "empty", direction: "output", type: "reg"
+  add_port "full", direction: "output", type: "reg"
+  add_port "mem_rd_addr", direction: "output", type: "reg", packed: "[1:0]", lhs: 1, rhs: 0
+  add_port "mem_rd_en", direction: "output", type: "wire"
+  add_port "mem_wr_addr", direction: "output", type: "reg", packed: "[1:0]", lhs: 1, rhs: 0
+  add_port "mem_wr_en", direction: "output", type: "wire"
+  add_port "pop", direction: "input", type: "wire"
+  add_port "push", direction: "input", type: "wire"
+  add_port "reset", direction: "input", type: "wire"
+end
+
+  """
+  When I run `vgen -t Fifo_ctrl_4d fifo_ctrl.rb`
+  Then a file named "fifo_ctrl_4d.v" should exist 

data/features/vgen/hello.feature

@@ -0,0 +1,9 @@
+Feature: Hello World
+
+  Scenario: print banner
+  When I run `vgen`
+  Then it should fail with:
+  """
+  error: you must supply the top level class name.
+
+  """

data/features/vgen/leaf_node.feature

@@ -0,0 +1,15 @@
+Feature: Should not output leaf nodes.
+
+  Scenario: Leaf node
+  Given a file named "leaf.rb" with:
+  """
+  class Leaf < VerilogGen::HdlModule
+    set_proxy true 
+  end
+  class Node < VerilogGen::HdlModule
+    set_proxy false 
+  end
+  """
+  When I run `vgen -t Leaf leaf.rb`
+  Then a file named "leaf_module.v" should not exist 
+  And a file named "node.v" should exist